ounteis

a sequental ciscit used for

cloct þulses. for countingt
The Count
Sequence may be
bon - Iine linear
linear
(ascendin cescend ing)
A Counte io set of fb - flops whose stae ch
ange in
Steshun se to þulses apblied at clock the inut to he
Counte.
A Count ma be an U or don Count4 An ub.
County Counts in Ubwael diectn ie l,23- n qne
Cuunts in doun w ad diection
mn-, n-2- ,0.

lountus ae of to o ty beo
Async hronus Rpble Caunty
Synchonous | poN allal ceunty.

0 Asynchro nous Countos OR Ri-ble cuuntt:

To desgn a aipþle countor,the no fF Heqired

depends on the nunbes 0f sStates.

Ihe maxi mum num bet of state of a Co onter is 2",

where n is the no: of FF in the Cuunte .

The no o outut tate of countey is called

he oeulus (MOD) of the coutn.
of o/bs
I4 we have 2 FF, the max. þoss1 ble no
thyå Cuntuy
statts a 2 y wo Can na me

Mop-4 Cuunty.
 2 bit Asynchroous Cuonter 09 MoD- Cuunt : (uy rt

(Ma

JA
CLK
JL Ko

Mod- 4 Count with Th FE

(Ub)
CLK

) o0

Timig Diagag

(00

De tnats
29

May. Gunt
3bit Asynchro nou Csunty (P)
AACLSO)

Te e

t he

Lojic Diafgm

(löy

Timg Diagam
 As,y nch tonus Down (ount The D
Do n CoUrrte4
Sequence is a alesCe nal ing
0Hde We Can me
mo dity U Counten bytllo
ys to make + den Cousti.
E) maki the fF taggen on tve edage
2
13y Cone etmg one ff Com blerment /p
to the Ff Jb
3·
By +ahing 4Nhe Coutey atut mitcadu.
Methocl
Vee

Je

lo
2 Bit Ri bble Ub /Dn CouUstet - (on Cnenth both dsie c.
AContol tem

Kosed to choose
c hoose he
he cli91e
1g1e ctim
ctm of Cuat

Lgc

Ks

BN Ribble Ceunty
Design of Divide

-ve ede
fn
cale
lon

4 ve
 M= 0 cOunter acts as down counter

6.17 DESIGN OF DIVIDE-BY-N RIPPLE COUNTER

Counters can also be designed to have number of states in their sequence which are less than 2". The
aeulting sequence is called a "truncated sequence". To obtain the truncated sequence, it is necessary
n force the counter to recycle before going through all of its normal states.
Whenever we want to count to a base n, which is not a power of 2, then we have to consider
bw' factor, which is same as the modulus. These counters are called 'divide
divide-by-n"
ounter is modified to produce the required MOD numbers which are less than 2" by counters. The basic
to skip states that are not part of the counting sequence. One allowing the counter
of the most common method for doing
o this is by making all flip-flops to reset after the count N with
the feedback gate (n feedback provided
hy a NAND gate) in the circuit.
 OD-10Ripple
Decade
-follows a sequence of ten Counter or BCD Counter
any visible
nal
COunter
called states and returns to 0
their sequence are decade counters. A after the count of
t/001)is counter
also called a BCD counter
because it has counter witha count 9.The counters
shows
thestate diagram of a BCD ipple
counter. ten-states sequence issequence of 0
the BCD code.(0000)
Fig.
0000 0001 (0010)
0011
(0100
1001 1000 0111)
Fig. 5.23(a) State diagram of
0110)0101
decode counter with
MOD-10 counter.
fur bitaasynchronous four JK flip-flops is shown in
to count 1010. the NAND gate output goes Fig. 5.23(b). When
10th clock LOW and all the flip-flops are in clear
Thus, when pulse occurs, the counter output Ois 0000 instead of 1010.
HIGH Q,(LSB)
Q,(MSB)

A
Kg
CLR CLR CLR CLR

D
Fig. 5.23(6) MOD-10 ripple counter.
 ,Pocesdure fur a
Sncharvus Cunte
Desgo
Circuit nfurmatn.
Dbtarn state elieg4m f'sn
Detne

(3 Jgte eatatn lle fev ffr.

Sxcrtatntalle.
Dovel Cvcut
Stote
talle
5
Use k-map fo finl e«bfr Cores bandig

Coeut
Desgo Moc 4 Chuntes usig Ir FE
y. indiCate no of states So Count
O,l23.

2"2 N
2^24
2^2 22
n= 2

-o
X

0. Rtate tal le
 Ke

CLK
 of a 5.23
An
its Sequence,
Sequence
up certain
The the
DOWN sequence UP/DOWN
UP/DOWN
counter
arrOWS sequence.
i.e. 1.e.,
modes n, 0, is
and7,6, in counter
the controlled
n-1, SYNCHRONOUS
1, An
of
Table n-2,. 2, up/down is
operation. 5, 3,
5.6 ..1,4, ..., by one
3, n.UP/
indicate 2, When counter that
Fig. 1, 0.DOWN is
For capable
5.28 0
the for 3-bit UP COUNTER is
shows down DOWNsignal.
state-to-state / also
counters, called of
progressing
the sequence. When
three signal
bidirectional
movement these this
bit is
signal in
up/down sequences LOW, ascending
of
counter.
is
the
then
HIGH,
counter. are
counter the Usually or
0,:counter
counter
descenaing
for 1,
2, up/down
both 3, goes
folows
4, ordeT
its 3, irough operatio
UP 6,revers
7 iroug
/Coumers

Table5.6 State table for three bit 375

up-down counter
UP
DOWN

1
0
0

0
1
3
1 0
2
1
1

1
0

1 1 1

up-down synchronous counter, using Tilip-flop. The

counter.
excitation table for 3-bit
control Input Present state Next state
UP0 DOWN Flip flop inputs
(U,) QA lc+B+1A+1 Tc Tg |TA
le--e-eele--" 0
0
1
1 1
1
0 0
1 0 1
0 1 1
0 0
0 0
1 1
0 1 1 1
1 0 0
0 0 0
1
0 1
1 1 1 1
1 0
0 0
1 0 1
1 1 0 1 1
1 0 1 0
1 1 0 1 1
1 1
1
1 0 0
0
0 1 1
0 1 1
1 0 1
1 1 0 1 1
 376
K-Map Simplification

For Tc For Te
ForT
00 01 11 10 00 01 11 10
00 01
00 1 3 2 00 0, 1 3
00 11
01 4! 5 7 6 01 4 5 7 6
01
4 5
1
11 12 h3 |15-14 11 12 h3 I15 14
1) 11 121
|1 3 1 15
10 11! 10 11 10
10 8
9 1/ 10 8
1
Tç =U@g@a+UoQg@A

Logic diagram

LSB MSB
A B

HIGH

T T

Clock

Fig. 5.28 Three bit synchronous UP/DOWN Counter.

 Fig. Ex. 5.6(b)
flop with an
Example 5.7 Design a counter by using T flip flop
and 7.
iregular binary count sequence of 1, 2, 5
Solution. State diagram
001
010

111
101

Fig. Ex. 5.7(a)

Thestate iagram is as shown in the
Ce reauired to implement this Fig. Ex. 5.8(a). Although there are
only
ence does not include all sequence because the maximum binary count is four states, a3 bit counter
e don't care
the possible binary states, the seven. Since the required
condition in the invalid states (0, 3, 4 and 6) can be
state. vou must make sure thatdesign. However, if the counter should treated
it goes back to a valid
Next state table is developed from state. erroneously get into an invalid
the state diagram and is given in
State Table table.
Presentstate Next state Flip flop inputs
CA+1 B+1 TA TB Tc
1
1
1 1 1 1
1 1 1 1
1 1 0
1 1 0
Unused states are 000,
011, 100, 110.
 Also
present state K-maps.
382
The T input is plotted on the 100 care don't
cells corresponding
to the invalid states 000, 011, and 110, as conition by can
indicated
conditions).
advantage of as many of the don't care he be Xa
taking states asis
Group the l's,Notice that all cells in a map are grouped, the expression
simplification.
follows.
each T input from the maps is as
expression for
Expression for TA Expression for Ta
10 QaQc 00
QeQc 00 01 11 01
QA 11
QA 2
1 10
1i 0 X
X 1 X
X
1
6 4 5
5 7! 1
4 6
1 1 X X 1
X

T,=Q, T=1
Expression for Te
QeQc 00 01 11 10
QA 3_ 2
1
X 1 X 1|
----

4 5 7 6
X X

Te=Oa
Logic diagram

Q Voc =+5 V Qc

TA Tc Qc
Ta

CLK

Fig. Ex. 5.7(6)

 5.24 SHIFT REGISTER COUNTER
Ashift register counter is basically a shift register with the serial output connected
input to produce special sequences. These devices
special sequence of states. Two of the most common
are classified as
types of shift counters
register
because
counters are
backiohey cte
and the Johnson counter. the ingu
5.24.1 Ring Counter
Figure 5.29 shows the logic circuit for a 4 bit ring counter. It isconstructed from
length n, where n is the number of flip flops. D flip flops result the simplest circuits,
in shift regsles
the first flip flop Qo is connected to the input of second flip flop and soSo on as shown in Figs
The output of last flip flop , is connected to the input of first flip flop Do. Initially the
reset by applying a LOW signal at CLR input. All the flip flops reset except the first fip lop
presets when the CLR is active LOW. So the initial output word is
Qol,0,2, = 1000
The first positive clock edge shifts MSB to LSB position and other bits to one position lef y
successive outputs are OoQ,OOa = 0100. This process continues on second and third nositv.
edges so that successive outputs are 0010 and 0001. Table5.7 shows the truth table of rine
 Qo 385

LSB

MSB
o,PREQ, D, D

CLK

CLA
Fig. 5.29 4 bit ring
counter.
Table 5.7 Truth table of a 4 bit ring
counter
CLK CLR
0 0
1 0 0 1
1 1
1 1
0 0 0
1 1 0 0
1 1
0
1
1 1
1
1 1
0

hnson Counter
CoOunter is a
tlngth 2N, Wherevariation of a shift register
ai he last Nis the number of flip counter. Johnson counters have basic
iit flip flop is connected back to flops. In Johnson counter, the complement counting
of the
S30
produces a
unique sequence of states.
the D input of the first
flip flop. This feedback
showsa is4bit Johnson counter. The last flip flop of . is connected to the input of first
1, so at the
rising pulse of the first cycle Q will change to 1. The output
Vut state wil o=0001 after first clock pulse,clock
to 230,0, =0011 andthen atthe rising pulse of the second clock
pdsg thoute out state change
he
so on till at the rising pulse of the fourth
Changes to 1111, At the fifth rising pulse the state then becomes I110, at
sate becomes 1100 and so
on at the eight pulse it becomes 0000. Table 5.8 shows
COunter.,
 Q,
386 Qo Qz

Q
D, Q, D2 Da
Do

4 bit Johnson counter.

CLK Fig. 5.30 Logic circuit for
Table 5.8Truth table of 4 bit Johnson counter
olo
Clock
0 1
0
1 0 1
1 0
1 1 0 1
2
1
3 1
1 1
4 1 1
0 1
5
0 0 0
6 1
0 0
7 0
0 0 1
0