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Rocking DFT Script

The document discusses the increasing costs of testing chips post-manufacturing and the advantages of Design for Testability (DFT) in improving yield and reducing defect risks. It outlines the DFT process, including the use of ATPG and MBIST, and emphasizes the need for hardware emulation to accelerate DFT verification cycles. The DFT app enhances the design schedule by enabling comprehensive gate-level simulations and is compatible with industry-standard testing formats.

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5 views2 pages

Rocking DFT Script

The document discusses the increasing costs of testing chips post-manufacturing and the advantages of Design for Testability (DFT) in improving yield and reducing defect risks. It outlines the DFT process, including the use of ATPG and MBIST, and emphasizes the need for hardware emulation to accelerate DFT verification cycles. The DFT app enhances the design schedule by enabling comprehensive gate-level simulations and is compatible with industry-standard testing formats.

Uploaded by

kshitij.kulshk008
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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Script :

1. The cost of testing a batch of chips after manufacturing to determine which


parts are free of manufacturing defects has reached an alarming threshold of 40% of
the cost of building the chip.

2. What are the main advantages of the DFT , why it is required ?

a) DFT can eliminate the risk of passing a problem device that eventually will be
caught in the field at a cost much higher than if found on the manufacturing floor.

b) avoid the rejection of faultless devices, thus increasing the yield.

3. DFT Porcess

a) ATPG and MBIST , insertion of the On chip test infrastructure , Such as Scan
chian , MBIST
and compression/Decompression logic

b)Scan chain adds controllability and observability through serial shift-registers

c) With scan chain, the problem of testing a circuit is simplified

d) The ability to automatically generate test patterns via ATPG tools can alleviate
the time-consuming and tiresome task of creating test vectors

e) from the design viewpoint the creation and insertion of the DFT structures are
rather simple

f) From the density and size perspective, however, the design gets rather large,
and the volume of test patterns required to test the design significantly increases
size

DFT Verification :

Simulator-based verification is too slow for gate-level checks when design sizes
are reaching into the hundreds of million gates

Chips often are taped-out with minimal DFT verification, and thorough DFT testing
is performed after tape-out, too late to fix design faults.

DFT verification comes in various forms, including custom initialization patterns


that need to be verified

It could be an on chip clock controller inserted by an automatic test pattern


generation tool that needs to be dynamically verified

logic added for MBIST that requires functional verification of the associated
logic with the test pattern

An SoC may include a custom initialization pattern that configures a test and
causes a transition from a functional mode to a test mode. Other test modes may
have low-power techniques where parts of the chip are put into a low-power mode
during test, which requires validating the test infrastructure under appropriate
conditions.

Need of the Hardware Emulation with a DFT App


1. Hardware acceleration accelerates the simulation cycles required to do a
thorough DFT verification. It can enable verification the chip functionality,
regardless of its size and complexity.

2. While hardware emulation has been used for 30 years to increase verification
cycles by deploying re-programmable hardware, new deployment modes are making it a
far more viable verification tool and paved the way for an “apps” approach

3. he DFT app accelerates a chip design schedule that requires comprehensive gate-
level simulations. Taking advantage of automatically generated patterns, the design
team can shorten the overall pattern development cycle.

4. This type of hardware emulation’s scalable hardware and compiler enable test
pattern validation for large gate-level designs, with scan and other test
structures embedded into the design. Its high performance enables more simulation
cycles, speeding DFT analysis.

5/ The DFT app is interoperable with other tools because it supports the industry-
standard STIL format file used on the production tester to identify chips damaged
during manufacturing.

6. DFT apps for hardware emulation change the compilation flow and run-time
execution in the deployment process of a hardware emulator.

7. These are a change in the compilation flow and in the run-time execution. A
gate-level design with scan and MBIST is fed into the hardware emulation’s
compiler.

8. he compiler creates the necessary testing infrastructure for reading test


vectors from the STIL file, applying them to the synthesized device under test
(DUT) and comparing outputs

9.. The compiler re-compiles and synthesizes the user netlist into a structural
description compatible with hardware emulation.

10. At compile time, the emulator creates the necessary infrastructure for reading
test vectors from the STIL file and applying them to the synthesized DUT, then re-
compiles and synthesizes the netlist to a structural description compatible with
emulation. The test harness includes a mechanism to compare the outputs.

11. DFT apps enable execution of complete pattern sets for DFT verification to
shorten the pattern development cycle

12. Once the chip has been manufactured, the same STIL file can be used on the
testing floor. Loaded into an ATE, the test vectors exercise the chip and its
responses get compared with the expected values in the STIL file.

13, Hardware emulation does not simulate at incrementally better speeds than
simulation – it is orders of magnitude faster.

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