MUX Implementation
MUX Implementation
Sol.)
Example for MUX Implementation
Sol.)
1. There are 3 I/P variables, so
we can select MUX with 3 D0
select I/P (so use 8:1 MUX). D1
2. Use the select I/Ps S2, S1, S0 D2
for the I/P variables A, B, C D3
respectively. D4
3. Since F=1 (O/P), ODD 1’s D5
detector, we connect logic 1 to D6
data I/Ps D1, D2, D4, & D7. D7
remaining is connected with
logic 0.
Example for MUX Implementation
Q1.) Use MUX to implement the logic function
• F=A B C
Select I/Ps
Sol1.)
D0
D1
D2
D3
D4
D5
D6
D7
MUX behaves in exactly the same way that a set of logic gates implementing the
function F would behave.
Example for MUX Implementation
D0
D1
D2
D3
D4
D5
D6
D7
Example for MUX Implementation
D0
D1
D2
D3
D4
D5
D6
D7
Example for MUX Implementation
ABC
ABC
ABC D
ABC D’
D’
Example for MUX Implementation
Q3.) Use a MUX having 3 select I/Ps to implement the logic function
given below.
• F (A, B, C, D)= S m (0, 1, 2, 3, 4, 10, 11, 14, 15)
Sol.) Given function is a four variable.
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
Example for MUX Implementation
Q3.) Use a MUX having 3 select I/Ps to implement the logic function
given below.
• F (A, B, C, D)= S m (0, 1, 2, 3, 4, 10, 11, 14, 15)
Sol.) Select I/Ps
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
Example for MUX Implementation
Q3.) Use a MUX having 3 select I/Ps to implement the logic function
given below.
• F (A, B, C, D)= S m (0, 1, 2, 3, 4, 10, 11, 14, 15)
Sol.) Select I/Ps
D0
D2 D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
Example for MUX Implementation
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
Example for MUX Implementation
I0
I1
S2 S1 S0 Y
4:1
I2 MUX 0 0 0 I0
I3 0 0 1 I1
2:1 0 1 0 I2
S1 S0 MUX Y 0 1 1 I3
I4 1 0 0 I4
I5 4:1 1 0 1 I5
I6 MUX 1 1 0 I6
S2
I7 1 1 1 I7
S1 S0
Larger Multiplexers
When
I0
I1 S2S1S0 = 000 S2 S1 S0 Y
4:1 I0
I2 MUX 0 0 0 I0
I3 0 0 1 I1
2:1
I0 0 1 0 I2
S1 S0 MUX Y 0 1 1 I3
I4 1 0 0 I4
I5 4:1 1 0 1 I5
I6 MUX I4 S2
1 1 0 I6
I7 1 1 1 I7
S1 S0
Larger Multiplexers
When
I0
I1 S2S1S0 = 001 S2 S1 S0 Y
4:1 I1
I2 MUX 0 0 0 I0
I3 0 0 1 I1
2:1
I1 0 1 0 I2
S1 S0 MUX Y 0 1 1 I3
I4 1 0 0 I4
I5 4:1 1 0 1 I5
I6 MUX I5 S2
1 1 0 I6
I7 1 1 1 I7
S1 S0
Larger Multiplexers
When
I0
I1 S2S1S0 = 110 S2 S1 S0 Y
4:1 I2
I2 MUX 0 0 0 I0
I3 0 0 1 I1
2:1
I6 0 1 0 I2
S1 S0 MUX Y 0 1 1 I3
I4 1 0 0 I4
I5 4:1 1 0 1 I5
I6 MUX I6 S2
1 1 0 I6
I7 1 1 1 I7
S1 S0
Larger Multiplexers
Implementation of an 8-to-1 multiplexer using smaller
multiplexers:
When
I0 2:1 I0 S2S1S0 = 000 S2 S1 S0 Y
I1 MUX 0 0 0 I0
0 0 1 I1
I2 2:1 I2 S0 0 1 0 I2
I3 MUX 0 1 1 I3
I0
1 0 0 I4
4:1 1 0 1 I5
S0 MUX Y
1 1 0 I6
I4 2:1 I4 1 1 1 I7
I5 MUX
S2 S1
S0 I6 2:1
I7 MUX I6
Q: Can we use only 2:1 multiplexers?
S0
End of the Class