Digital Electronics

Outline
 2 Level Gate Implementation
 Combinational Design

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 Logic Gates

Six points to Discuss:

1. Symbol
2.Truth Table
3. Associative Law
4. Commutative Law
5. Enable/ Disable
6.Unused Input

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 OR Operation

We implement OR Operation (plus sign) using OR Gate.

3. Associative Law: OR Gate follows it

(A+B)+C=A+(B+C)
4. Commutative Law: OR Gate follows it
A+B=B+A
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 OR Gate

4. Enable & Disable: A B Y

0 0 0
0 1 1
1 0 1
1 1 1

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 OR Gate

4. Enable & Disable: A B Y

Enable 0 0 0
/Buffer 0 1 1
Disable 1 0 1
o/p=1 1 1 1
Note: “0” is Enable for OR Gate.

5. Unused Inputs (3 ways to connect):

(a) Connect it to “0”
(b) Connect to one of the used inputs.
(c) For TTL Logic unused input is 1 & For ECL Logic unused input is 0.

(Floating I/O) 0 Y=B

B Buffer
5
Question

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 NAND Gate

Y=A’+B’

A A’
X=(A.B)’ A Y=A’+B’
B B
B’
AND-NOT
NOT-OR
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 NAND Gate or Bubbled OR
A’
A
Y=A’+B’
B
B’

A Y B Y=A’+B’
=
B B
Bubbled OR
Y=(A.B)’ Y=A’+B’
A B W Y A B A’ B’ Y
0 0 0 1 0 0 1 1 1
0 1 0 1 0 1 1 0 1
1 0 0 1 1 0 0 1 1
1 1 1 0 1 1 0 0 0 8
 NOR Gate

Y=A’.B’

OR-NOT
A’
A W
X=(A+B)’ A Y=A’.B’

B B
B’
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 NOR Gate or Bubbled AND
A’ Y=A’.B’
A
B
B’

A A
Y = Y
A B

Y =(A+B)’ Y =A’.B’

A B Y A B A’ B’ Y
0 0 1 0 0 1 1 1
0 1 0 0 1 1 0 0
1 0 0 1 0 0 1 0
1 1 0 1 1 0 0 0 10
 NAND and NOR Properties

3. Associative Law: Only Two logic gates doesn't follow it.

4. Commutative Law: Both gates follows it.
5. Enable & Disable:
NAND NOR
X Y Z X Y Z
0 0 1 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 0

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 NAND and NOR Properties

5. Enable & Disable:

NAND NOR
X Y Z X Y Z
Disable 0 0 1 Enable 0 0 1
o/p=1 0 1 1 /Inverter 0 1 0
Enable 1 0 1 Disable 1 0 0
/Inverter 1 1 0 o/p=0 1 1 0

6. Unused Inputs:
1. For NAND gate unused inputs is treated as same as in AND gate.
2. For NOR gate unused inputs is treated as same as in OR gate.

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 Exclusive-OR Gate (EX-OR/XOR)

X = AB’ + A’B
X= (A+B).(A’+B’)

Internal circuit can be drawn as:

A A.B’

B A’.B

Note: Output is HIGH whenever A and B disagree. 13

 Exclusive-NOR Gate (EX-NOR/XNOR)
Truth table
The Boolean expression is: X = AB + A’B’
Inputs Output
A B X
Note: Output is HIGH whenever A and B agree. 0 0 1
0 1 0
1 0 0
1 1 1

Internal circuit:

A Symbols:
X
B
=1

Logic/ Traditional IEEE

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 XOR and XNOR Properties

Enable & Disable:

XOR XNOR
X Y Z X Y Z
0 0 0 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 1

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 XOR and XNOR Properties

Enable & Disable:

XOR:Controlled Inverter XNOR
X Y Z X Y Z
Enable 0 0 0 Enable 0 0 1
/Buffer 0 1 1 /Inverter 0 1 0
Enable 1 0 1 Enable 1 0 0
/Inverter 1 1 0 /Buffer 1 1 1

0
XOR Y=B =
B
Buffer
1
XOR Y=B’ =
B
Inverter 16
 XNOR
XOR

 Generalized:
A A A ………………n =A,When n is Odd (same for NOR)
=0,When n is Even (1 for NOR)
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 XOR and XNOR Properties

 Example:
A B C =A B C (Odd inputs)

A B C D =(A B C D)’ (Even inputs)

For A B C (Prove)

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 NAND as Universal Gates

 NAND gates used to produce the other basic Boolean functions.

X=(A.B)’ Y=A’+B’

A A A AB
B
Inverter AND gate

A A
A+B A+B
B B

OR gate NOR gate

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 EXOR using NAND Gates

 NAND as EXOR: AB’+A’B

Q.) No. of NAND gates we require ?

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 EXOR using NAND Gates

 NAND as EXOR: AB’+A’B

Q.) No. of NAND gates we require ?

 2 NOT needs 2 NAND gates for its implementation

 2 AND needs 4 NAND gates for its implementation
 1 OR needs 3 NAND gates for its implementation
 Total we need 9 NAND Gates

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 EXOR using NAND Gates

A A’B (A’B)’
B
Y=AB’
+A’B
A AB’
B
(AB’)’

NOT AND OR

Y=AB’+A’B Y= ((A’B)’.(A.B’)’)’ Y=A’B+AB’

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 EXOR using NAND Gates

(A’B)’ (A’B)’

A A’B (A’B)’
B
Y=AB’
+A’B
A AB’
B
(AB’)’

NOT AND OR 24
 EXOR using NAND Gates
A (A’B)’
B

Y=AB’+A’B

A
B
(AB’)’
4 NAND Gates can be reduce to 3

=(AB’)’

=(A’B)’

 4 NAND Gates is the most efficient implementation 25

 XNOR using NAND Gates

A
Y=AB+A’B’
EXOR
B
1 NAND Gates
4 NAND Gates

 5 NAND Gates is the most efficient implementation 26

 NOR as Universal Gate

(A + B)’

 NOR gates can form all of the basic gates.

A A A A+ B
B
Inverter OR gate

A A
AB AB
B B

AND gate NAND gate

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XOR and XNOR using NOR Gate

Y=AB+A’B’

XNOR gate using NOR gate

Y=AB’+A’B

NOT

XOR gates using NOR gate

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Two-level Implementations

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 Two-level Implementations

Two-level Implementations:
The implementation of a logic expression such that each one of the I/P
has to pass through only two gates to reach the O/P.

Form of a two-level implementation:

1. SOP (AND-OR)
2. POS (OR-AND)
3. NAND-NAND
4. NOR-NOR

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AND-OR (SOP) Emulation Using NANDs
a) Original SOP (b) Implementation with NANDs

Two-level implementations

Verify:
(a) G = WXY + YZ

(b) G = ( (WXY)’ • (YZ)’ )’

= (WXY)’’ + (YZ)’’ = WXY + YZ 31
 NAND Implementation

NAND gates can be used to implement a SOP form of a Boolean

equation.
To see this, let us construct a two level NAND-NAND gate function
thus: A
B
G(A,B,C,D)
C
G(A,B,C,D) = A*B + C*D
D
The first level uses AND-Invert symbol.
The second level uses Invert-OR symbol.
Using the NAND relationship, we have:

G(A,B,C,D) = ((AB)'(CD)')'
= ((AB)')'+((CD)')'
= (AB) + (CD)
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 NOR Implementation

NOR gates can be used to implement a POS form of a Boolean

equation.
To see this, let us construct a two level NOR-NOR gate function
thus: a

b
G(a,b,c,d)
c

d
G(a,b,c,d) = (a+b)*(c+d)

Using the NOR relationship:

G = ((a+b)'+(c+d)')'
= ((a+b)')'((c+d)')'
= (a+b)(c+d)
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 Two-Level NAND Gate Implementation -
Example

F (X,Y,Z) = m(0,6)
1. Express F in SOP form:
F = X’Y’Z’ + XYZ’
2. Obtain the AND-OR implementation for F.
3. Add bubbles and inverters to transform AND-OR to NAND-NAND gates.

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Example (cont.)

Two-level implementation with NANDs

F = X’Y’Z’ + XYZ’

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 Two-Level NOR Gate Implementation -
Example
F(X,Y,Z) = m(0,6)
1. Express F’ in SOP form:
1. F’ = m(1,2,3,4,5,7)
= X’Y’Z + X’YZ’ + X’YZ + XY’Z’ + XY’Z + XYZ
2. F’ = XY’ + X’Y + Z
2. Take the complement of F’ to get F in the POS form:
F = (F’)' = (X'+Y)(X+Y')Z'
3. Obtain the OR-AND implementation for F.
4. Add bubbles and inverters to transform OR-AND
implementation to NOR-NOR implementation.

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 Example (cont.)

Two-level implementation with NORs

F = (F’)' = (X'+Y)(X+Y')Z'

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 Combinational Logic Circuits

 An example of an SOP implementation is shown.

 The SOP expression is an AND-OR combination of the input variables
and the appropriate complements.

A
B ABC
C X = ABC + DE SOP

D
DE
E

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 Combinational Logic Circuits

 When the output of a SOP form is inverted, the circuit is called an

AND-OR-Invert circuit. The AOI configuration lends itself to POS
implementation.

 An example of an AOI implementation is shown. The output

expression can be changed to a POS expression by applying
DeMorgan’s theorem.

A
B ABC
C X = ABC + DE X = ABC + DE AOI

D X = (ABC)(DE) DeMorgan
E DE X = (A + B + C)(D + E) POS

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General Implementations (Cont.)
Given a two level implementation desired, use the previous
transfromations to get it into one of the below forms. Then
follow the steps to transform the function to the desired form:
For Type: Use:
AND-OR Circle 1's in the K-Map and minimize
(SOP Form) (Also use for NAND-NAND)
AND-NOR Circle 0's in the K-Map and minimize
(SOP complemented)
OR-AND Circle 0's in the K-Map and minimize
(POS Form) SOP. Use DeMorgan's to transform to
POS. (Also use for NOR-NOR)
OR-NAND Circle 1's in the K-Map and minimize
(POS complemented) SOP. Use DeMorgan's to transform to
POS.
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 Implementation Example
Implement the function in NOR-OR.

F = B' + A'C' Use DeMorgan's Law:

F' = B(A+C)
B
1 1 0 1

A 1 1 0 0
B
C 1
1 1 0
A 1 1 0 0 A

C C
F
B
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 Examples

Q.) A Karnaugh map is drawn from a truth table. Read the minimum
SOP expression and draw the circuit.

C C

AB 1

AB 1 1

AB

AB

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 Examples

Circuit: A
C X= AC + AB
A
B

The result is shown as a SOP.

Q.) Convert the above circuit to one that uses only NAND gates.

A
C X= AC + AB
A
B
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Combinational Logic Circuit

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 Revision of Combinations Design
Logic circuits for digital systems may be either combinational or
sequential.

n input Combinational m output

variables Logic Circuit variables

 Specific functions
 Adders, subtractors, comparators, decoders, encoders, and
multiplexers

Characteristics of combinational circuits are as follows:

 The output at any instant of time, depends only on the levels present at
input terminals.

 It does not use any memory. The previous state of input does not have any
effect on the present state of the circuit.
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Combinational Arithmetic Circuits

1. Addition:
Half Adder (HA).
Full Adder (FA).
Carry Ripple Adders.
Carry Look-Ahead Adders.
2. Subtraction:
Half Subtractor.
Full Subtractor.
Borrow Ripple Subtractors.
Subtraction using adders.
3. Multiplication:
Combinational Array Multipliers.

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 Addition

The input variables designate the augend and addend bits.

X Y
Inputs Carry Sum
X Y C S
0 0
0 1
1 0
1 1 S C

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 Binary Half-Adder

AOI Logic
X Half S
Y Adder C-OUT

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 Addition

x y C-in C-out S
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1 X Y

C-out C-in

S 49
Full Adder

X Y

Full
C-out C-in
Adder

S 50
Full Adder

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Full Adder using AND-OR

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Full Adder

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 Full Adder using Half Adders

Simpler Schematic Representation of a One-Bit Full Adder

Full Adder Design Using Half Adders

 With this type of symbol, we can add two bits together.

 Taking a carry from the next lower order of magnitude, and sending a carry to
the next higher order of magnitude.

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Full Adder using Half Adders

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 Full Subtractor = full adder, almost

 X,Y are n-bit unsigned binary numbers

 Addition : S=X+Y
 Subtraction : D = X - Y = X + (-Y) =
= X+ (Two’s Complement of Y)
= X+ (One’s Complement of Y) + 1
= X+ Y’+ 1
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 Binary Arithmetic Operations
Subtraction
 Two binary numbers are subtracted by subtracting each pair of bits
together with borrowing, where needed.
Subtraction Example:

0 0 1 1 1 1 1 0 0 Borrow
X 229 1 1 1 0 0 1 0 1
Y - 46 - 0 0 1 0 1 1 1 0
183 1 0 1 1 0 1 1 1

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 Half Subtractor
Subtracting a single-bit binary value Y from another X (I.e. X -Y ) produces a
difference bit D and a borrow out bit B-out.
This operation is called half subtraction and the circuit to realize it is called a half
subtractor.

Half Subtractor Truth Table D(X,Y) =  (1,2)

Inputs Outputs D = X’Y + XY’
X Y D B-out D = XY
0 0 0 0
0 1 1 1 B-out(x, y, C-in) =  (1)
1 0 1 0 B-out = X’Y
1 1 0 0

X Difference
D
Y
X Half D
Y Subtractor B-OUT B-out

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 Full Subtractor
Subtracting two single-bit binary values, Y, B-in from Difference D X
a single-bit value X produces a difference bit D and
XY
a borrow out B-out bit. This is called full subtraction. B-in 00 01 11 10
0 2 6 4
0 1 1
Full Subtractor Truth Table 1 3 7 5
Inputs Outputs 1 1 1 B-in

X Y B-in D B-out Y
0 0 0 0 0 D = X’Y’(B-in) + XY’(B-in)’ + XY’(B-in)’ + XY(B-in)
D = X  Y  (B-in)
0 0 1 1 1
0 1 0 1 1 Borrow B-out X
0 1 1 0 1 XY
1 0 0 1 0 B-in 00 01 11 10
0 2 6 4
1 0 1 0 0 0 1
1 1 0 0 0 1 3 7 5
1 1 1 1 B-in
1 1 1 1 1
Y
S(X,Y, C-in) =  (1,2,4,7)
B-out = X’Y + X’(B-in) + Y(B-in)
C-out(x, y, C-in) =  (1,2,3,7)
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 Full Subtractor Circuit Using AND-OR
X’ X’Y’B-in
X Y’
X X’ B-in

X’
X’YB-in’ Difference D
Y
Y B-in’
Y Y’ X
Y
B-in B-in’ XY’B-in’
B-in B-in’ X
Y
B-in’ XYB-in

X Y X’ X’Y
Y
Full
B-out B-in X’
X’B-in
Subtractor B-out
B-in
Y
D
B-in YB-in

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 Full Subtractor Circuit Using XOR

D = X’Y’(B-in) + XY’(B-in)’ + XY’(B-in)’ + XY(B-in)

D = X  Y  (B-in)

Y Difference D
X Y B-in

Full X’ X’Y
B-out B-in
Subtractor Y

X’
X’B-in
B-out
D B-in
Y

B-in YB-in

B-out = X’Y + X’(B-in) + Y(B-in)

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End of the Class

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