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Advanced Verification Course Syllabus

The document outlines a comprehensive course curriculum for SystemVerilog and UVM, covering various topics such as data types, testbench architecture, verification features, and industry applications. It includes live sessions, hands-on experience, and discussions to enhance understanding and performance expectations. Additionally, it emphasizes the importance of Perl scripting and debugging in the context of SOC and IP testing.

Uploaded by

Aishwarya Pattanashetti
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© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
7 views

Advanced Verification Course Syllabus

The document outlines a comprehensive course curriculum for SystemVerilog and UVM, covering various topics such as data types, testbench architecture, verification features, and industry applications. It includes live sessions, hands-on experience, and discussions to enhance understanding and performance expectations. Additionally, it emphasizes the importance of Perl scripting and debugging in the context of SOC and IP testing.

Uploaded by

Aishwarya Pattanashetti
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Course Curriculum

Phone Number
+91-9599745251

Visit Our Website


www.semidesign.com
➢ SystemVerilog Overview
Live Session
➢ Standard Data types & Literals & Operators Theory & Labs
➢ User-Defined Data types & Structures
➢ Tb Architecture & Connectivity Hands on
Experience
➢ Testbench Components
➢ Static, Dynamic, Associative Arrays
➢ Queues Industry
➢ Tasks & Functions Guidance

➢ Interfaces, Virtual Interface


➢ Verification Features Live Doubt
➢ OOPs, Classes Discussion

➢ Polymorphism and Virtuality


Industry
➢ Inheritance, Encapsulation Applications
➢ Clocking Blocks
➢ Clocking Blocks
Live Session
➢ Random Stimulus Theory & Labs
➢ Class-Based Random Stimulus
➢ Code Coverage Hands on
Performance Expectations
Experience
Of Employees & Superiors
➢ Deep into Functional coverage
➢ Assertion Based Verification(ABV)
➢ SystemVerilog Assertions Industry
➢ Direct Programming Interface(DPI) Guidance

➢ Interprocess Synchronization
➢ Testbench Components Setting Performance
LiveStandards
Doubt
➢ Testbench Examples Discussion
➢ Testplans, Testcases
Industry
Applications
➢ Deep understanding of UVM in SOC | IP
Live Session
➢ Detailed explanation on UVC in SOC | IP Theory & Labs
➢ Introduction to UVM, Features
➢ Testbench Hierarchy, Components Hands on
Performance Expectations
Experience
➢ UVM Sequence Item, Sequence, Sequencer
Of Employees & Superiors

➢ Configuration, UVM config_db


➢ UVM Phases Industry
➢ UVM Driver Guidance

➢ UVM Monitor
➢ UVM Agent Setting Performance
LiveStandards
Doubt
➢ UVM Scoreboard Discussion
➢ UVM Environment
Industry
➢ UVM Test Applications
➢ Creating all Components in a flow
➢ Understanding of UVM RAL Model
Live Session
➢ Deep into UVM TLM Theory & Labs
➢ Callback
➢ Events Hands on
Performance Expectations
Experience
➢ UVM Test
Of Employees & Superiors

➢ UVM Testbench Examples


➢ UVM Testplan Creation Industry
➢ DTPs(Detailed Test Plan Exaplanation) Guidance

➢ Testcase scenarios
➢ Importance of Regressions Setting Performance
LiveStandards
Doubt
➢ How to Run the Regression Discussion
➢ How to check test pass or fail in SOC | IP
Industry
Level Applications
➢ Idea on debugging testcases, execution flow
➢ Importance of Perl Scripting
Live Session
➢ How to run the commands Theory & Labs
➢ Idea on Coverage analysis
➢ Upload and extract the coverage report Hands on
Performance Expectations
Experience
➢ Walk through perl concepts
Of Employees & Superiors

➢ Coding standards
➢ Explanation of Data types, Arrays Industry
➢ Hashes, Loops Guidance

➢ Operators, Subroutines
➢ Date & Time Setting Performance
LiveStandards
Doubt
➢ References, Formats Discussion
➢ Directories
Industry
➢ Error Handling Applications

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