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Why Are The Preset and Clear Arcs Written As Combinational Arcs in Extracted Timing Models

The document explains why preset and clear arcs in Extracted Timing Models are written as combinational arcs despite being defined as asynchronous in flip-flop library cells. Since 2001, PrimeTime has adopted this approach to avoid conflicts in timing sense during extraction. Users must enable the timing_enable_preset_clear_arcs variable to extract these arcs properly.

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46 views3 pages

Why Are The Preset and Clear Arcs Written As Combinational Arcs in Extracted Timing Models

The document explains why preset and clear arcs in Extracted Timing Models are written as combinational arcs despite being defined as asynchronous in flip-flop library cells. Since 2001, PrimeTime has adopted this approach to avoid conflicts in timing sense during extraction. Users must enable the timing_enable_preset_clear_arcs variable to extract these arcs properly.

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xylcool5
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© © All Rights Reserved
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Dec 11, 2019 • Knowledge

Title
Why are the preset and clear arcs written as combinational arcs in Extracted Timing Models?

Description
Why are the preset and clear arcs written as combinational arcs in Extracted Timing
Models?
Question:

While the definition for the asynchronous pins of flip-flop library cells have the timing_type attribute defined as preset and clear, why
does the extract_model command always writes out the timing_type attribute of these arcs as combinational?

Answer:

Since 2001, PrimeTime writes the preset and clear timing arcs in the extracted timing models as combinational arcs.

Note: By default, the preset and clear arcs are disabled during timing model extraction. Make sure that you set the
timing_enable_preset_clear_arcs variable to true before extracting the timing model to enable extraction of preset and clear arcs.

To understand this behavior, let us look at a D flip-flop with a rising edge clock, preset (active low), clear (active low), and Q as output:

The library definition of the corresponding cell is as follows:

etm.lib::

pin("OUT") {
direction : output ;
..
/* Other user defined attributes. */
original_pin : OUT;
timing () {
related_pin : "CLEAR" ;
timing_type : combinational ;
timing_sense : positive_unate ;
..

In normal operation, the preset arcs affect only the rise arrival time and the clear arcs affect only the fall arrival time of the arc's endpoint
pin, that is, timing_sense:negative_unate for the preset arcs and timing_sense:positive_unate for the clear arcs.

A preset arc indicates that you are asserting logic 1 on the output pin and a clear arc indicates that you are asserting logic 0 on the
output pin when the designated related_pin is asserted.

In the example, the extended timing arc from pin CLEAR to pin OUT traverses:

CLEAR -> FLOP/CDN -> FLOP/Q -> OUT


The corresponding timing_sense would be:

positive_unate (BUF1) -> positive_unate (FLOP's clear arc) -> negative_unate (INV)

Therefore, the final timing_sense at the port OUT would be negative_unate.

However, this CLEAR arc with negative_unate sense propagated to the port OUT would conflict with the default sense of the PRESET arc.

To avoid such situations, the extract_model command always sets the timing_type variable as combinational for both preset and clear
arcs.

Workaround

Product L1
PrimeTime (/s/detail/01t1U000003IY0JQAW)

Additional Product(s)

Article Number
000005021

Last Published Date


12/11/2019, 9:10 AM

Article Record Type


How To

URL Name
Why-are-the-preset-and-clear-arcs-written-as-combinational-arcs-in-Extracted-Timing-Models-1576002495494

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