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Visualizing Pipelined Scan-Enable Clusters in The Layout View

This document provides guidance on visualizing pipelined scan-enable clusters in the Design Compiler Graphical layout view using a Tcl procedure. It details the steps for implementing and highlighting these clusters, including command-line usage and configuration options for the layout view. Additionally, it summarizes the characteristics of the PSE clusters, such as the number of clusters and average wire lengths.

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8 views5 pages

Visualizing Pipelined Scan-Enable Clusters in The Layout View

This document provides guidance on visualizing pipelined scan-enable clusters in the Design Compiler Graphical layout view using a Tcl procedure. It details the steps for implementing and highlighting these clusters, including command-line usage and configuration options for the layout view. Additionally, it summarizes the characteristics of the PSE clusters, such as the number of clusters and average wire lengths.

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xylcool5
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© © All Rights Reserved
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Dec 24, 2019 • Knowledge

Title
Visualizing Pipelined Scan-Enable Clusters in the Layout View

Description

Pipelined Scan-Enable Clusters


When you use the pipelined scan-enable feature in a physical synthesis flow, the tool uses register placement information to create
physically compact clusters. You can use the Tcl procedure provided in this article to visualize how the clusters are distributed within
your design.

Note the following requirement for this Tcl procedure:

Although physical clustering is performed in both Design Compiler in topographical mode and Design Compiler Graphical, this Tcl
procedure requires Design Compiler Graphical because it requires detailed physical attributes and uses the layout GUI.

The pipelined scan-enable feature works by creating a registered scan-enable transition on the chip, just as an OCC controller generates
controlled at-speed clock pulses on the chip. The following figure shows the pipelined scan-enable logic structure.

In Design Compiler Graphical, for large or timing-critical designs, you can implement pipelined scan-enable clusters, each with their own
local pipelined scan-enable (PSE) construct. This improves the critical path delay between the pipeline registers and their scan cells.

To do this, use the -pipeline_fanout_limit option of the set_scan_configuration command to specify the number of scan cells per PSE
cluster:

dc_shell> set_scan_configuration \
-pipeline_scan_enable true \
-pipeline_fanout_limit 128

Visualizing the PSE Clusters


After running both DFT insertion and post-DFT optimization, you can run the Tcl procedure provided in this article to highlight the PSE
clusters in the Layout view of the Design Vision GUI:

dc_shell> insert_dft
dc_shell> compile_ultra -spg -scan -incremental
dc_shell> source highlight_PSE.tcl
dc_shell> highlight_PSE

Its command-line usage is as follows:


dc_shell> highlight_PSE -help
Usage: highlight_PSE # Highlights DFT PSE groups in the layout window
[-source source] (PSE register naming style:
Values: fc, dc)
[-no_gui] (Do not open the GUI)
[-hide_nets] (Do not highlight nets)
[-report] (Print detailed distance info)

The Tcl procedure works as follows:

Open the Design Vision GUI and create a Layout window, if not already done.
Iterate through all PSE clusters. For each,
Highlight the cells and nets in each cluster, from PSE register to scan cells. Buffer/inverter cells are included. Nets are shown as
flylines, not estimated routes.
Measure the total Manhattan wire length of the estimated routes in the cluster.
At the end, print the total and per-cluster average Manhattan wire lengths.

The clusters are highlighted using the Visual Mode feature of the GUI. Each scan cell cluster is listed by its register cell name and the PSE
registers themselves are in the "PSE cells" cluster. An object count column shows the number of objects (cells and nets) in each entry.
You can show or hide any entry by changing the checkbox settings then choose Apply. To identify the register name for a particular
cluster of interest, hover your pointer over that register to see its instance name in the tooltip.

To exclude the net flylines from highlighting in the clusters, use the -hide_nets option.

Here are the results for a 256x128 DesignWare register file with a fanout limit of 128 (click pictures for full-resolution view):

(https://solvnet.synopsys.com/retrieve/customer/script/attached_files/2552200/solvnet_2552200_2.png)
(https://solvnet.synopsys.com/retrieve/customer/script/attached_files/2552200/solvnet_2552200_3.png)

Configuring Your Layout View


The example above has all standard cells and macrocells hidden. You can configure your own layout view to show or hide items of
interest.

To hide all cells, run the following command:

gui_create_pref_key -category {layout} \


-key {showCell} -value_type {bool} -value {false}

To hide standard cells but show macrocells,

gui_create_pref_key -category {layout} \


-key {showCell} -value_type {bool} -value {true}
gui_create_pref_key -category {layout} \
-key {showCellCore} -value_type {bool} -value {false}
gui_create_pref_key -category {layout} \
-key {showCellHardMacro} -value_type {bool} -value {true}

To show standard cells in a dark gray color so you can see congested areas without obstructing the highlighting,

gui_create_pref_key -category {layout} \


-key {showCell} -value_type {bool} -value {true}
gui_create_pref_key -category {layout} \
-key {showCellCore} -value_type {bool} -value {true}
gui_create_pref_key -category {layout} \
-key {colorCellCore} -value_type {color} -value {gray25}
gui_create_pref_key -category {layout} \
-key {hatchCellCore} -value_type {string} -value {Dense4Pattern}

There are many other settings available. To configure your layout view manually, choose choosing View > Toolbars > View Settings (F8).
To save your view configuration as your new default, choose the Show Options gear icon, then choose Preferences > Save To Preferences.

Reporting the PSE Clusters


By default, the procedure reports a summary of the cluster characteristics:

- Number of PSE clusters : 256


- Average number of nets per PSE cluster : 5.620000
- Average PSE x+y wire length : 119187.922222
- Total PSE x+y wire length : 171630608.000000

To generate the report without opening the GUI, use the -no_gui option. This is useful in scripts to compare outcomes between runs.

You can also generate detailed reports for the clusters by using the -report option. For example,

dc_shell> highlight_PSE -no_gui -report


...
PSE Loads Net length Max dist Total dist PSE cell
-------------------------------------------------------------------------------------
132 664724.000000 37 2577 test_pipe_se_1_reg_0
133 549311.000000 34 2615 test_pipe_se_1_reg_1
132 689234.000000 41 2624 test_pipe_se_1_reg_2
132 758559.000000 37 2596 test_pipe_se_1_reg_3
133 512970.000000 36 2598 test_pipe_se_1_reg_4
132 729030.000000 33 2492 test_pipe_se_1_reg_5
132 702365.000000 38 2658 test_pipe_se_1_reg_6
133 552938.000000 46 2826 test_pipe_se_1_reg_7
133 496232.000000 37 2534 test_pipe_se_1_reg_8
133 510880.000000 36 2602 test_pipe_se_1_reg_9
132 751947.000000 34 2513 test_pipe_se_1_reg_10
132 665841.000000 33 2460 test_pipe_se_1_reg_11
...
133 505030.000000 36 2556 test_pipe_se_1_reg_252
133 503252.000000 37 2634 test_pipe_se_1_reg_253
133 674274.000000 61 3509 test_pipe_se_1_reg_254
135 969905.000000 89 6341 test_pipe_se_1_reg_255
-------------------------------------------------------------------------------------

** SUMMARY **
- Number of PSE clusters : 256
- Average number of nets per PSE cluster : 5.620000
- Average PSE x+y wire length : 119187.922222
- Total PSE x+y wire length : 171630608.000000
- Total PSE-load distance : 785186.000000

Files
highlight_PSE.tcl (https://solvnet.synopsys.com/retrieve/customer/script/attached_files/2552200/highlight_PSE.tcl) - version 1.3

# highlight_PSE.tcl
# highlight DFT pipelined scan-enable (PSE) clusters in Design Compiler Graphical mode
#
# v1.0 11/7/2016 chrispy
# initial release
# v1.1 02/06/2018 chrispy
# support more tools
# v1.2 05/09/19 danield
# extra command-line options, Visual Mode support
# v1.3 10/03/19 danield
# fixes renaming of dcrt to fc for -source issue

Workaround

Product L1
TestMAX DFT (/s/detail/01t1U000003IXzUQAW)

Additional Product(s)

Article Number
000031069

Last Published Date


12/24/2019, 12:23 PM

Article Record Type


Example/Script

URL Name
Visualizing-Pipelined-Scan-Enable-Clusters-in-the-Layout-View-1577133845119

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