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Why Do I Get An S1 DRC Violation in WRP - of Mode When Using An OCC Pipeline Clock

The document addresses S1 DRC violations encountered in wrp_of mode when using an OCC pipeline clock in DFT configurations. It explains that the issue arises because the OCC clock is not included in the outward-facing mode check if it only clocks pipeline registers and not wrapper cells. Solutions include using a non-OCC clock, ensuring the OCC clock clocks at least one wrapper cell, or modifying wrapper configurations to include the OCC clock information.

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80 views3 pages

Why Do I Get An S1 DRC Violation in WRP - of Mode When Using An OCC Pipeline Clock

The document addresses S1 DRC violations encountered in wrp_of mode when using an OCC pipeline clock in DFT configurations. It explains that the issue arises because the OCC clock is not included in the outward-facing mode check if it only clocks pipeline registers and not wrapper cells. Solutions include using a non-OCC clock, ensuring the OCC clock clocks at least one wrapper cell, or modifying wrapper configurations to include the OCC clock information.

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xylcool5
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© © All Rights Reserved
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Dec 11, 2019 • Knowledge

Title
Why Do I Get an S1 DRC Violation in wrp_of Mode When Using an OCC Pipeline Clock?

Description
Question:

My design uses the core wrapping, pipelined scan data, and on-chip clocking (OCC) controller DFT features. I have configured the pipeline
registers to use the OCC clock, as described in SolvNet article 2052076, "How Can I Specify OCC-Controlled Clocks for DFT Configuration
Commands?" (https://solvnet.synopsys.com/retrieve/2052076.html).

After DFT insertion, I verified that the OCC controller's output clock is correctly used to clock the pipeline registers.

However, during post-DFT DRC of the wrp_of mode, I get S1 DRC violations for pipeline registers:

-------------------------------------------------------------------------
DRC Violations which prevent scan chain shifting
-------------------------------------------------------------------------

Error: Chain WrapperChain_0 blocked at DFF gate SNPS_PipeTail_test_so1_2 after tracing 0 cells. (S1-1)
Error: Chain WrapperChain_1 blocked at DFF gate SNPS_PipeTail_test_so2_2 after tracing 0 cells. (S1-2)
Error: Chain WrapperChain_2 blocked at DFF gate SNPS_PipeTail_test_so3_2 after tracing 0 cells. (S1-3)
Error: Chain WrapperChain_3 blocked at DFF gate SNPS_PipeTail_test_so4_2 after tracing 0 cells. (S1-4)

What is causing this?

Answer:

In outward-facing wrapper modes, only the wrapper chain and I/Os are active for test; the internal core logic is not tested. The tool checks
the wrapper chain to determine if the OCC clock should be included in the outward-facing mode. If the OCC clock clocks any wrapper
cells, it is included; otherwise, it is not.

However, although the pipeline registers are included in the wrapper chains, they are not included in this check. If the OCC clock clocks
the pipeline registers but not any wrapper cells, then the OCC clock information is incorrectly omitted from the outward-facing mode,
resulting in the S1 DRC violations. This problem is captured by STAR 9000848030.

You can use the preview_dft command to preview the wrapper cell clocks that are to be used:

dc_shell> preview_dft -test_wrappers all

You can check the STIL protocol file (SPF) for the wrp_of test mode (or the ASCII CTL model for the design) to see if there is a
"ClockStructures wrp_of" construct describing the OCC clock:
ClockStructures wrp_of {
PLLStructures "my_pll_ctrl_b" {
PLLCycles 1;
Clocks {
"ate_clk" Reference;
"PLL_BLOCK/pll_clk" PLL {
OffState 0;
}
"my_pll_ctrl_b/U2/U2/Z" Internal {
OffState 0;
PLLSource "PLL_BLOCK/pll_clk";
Cycle 0 "snps_clk_chain_0/clk_ctrl_data" 1;
}
}

If there is no ClockStructures construct for the wrp_of mode, then the OCC clock information is not included for that mode.

You can resolve this issue as follows:

Use a non-OCC clock for the pipelined scan data clock.

If non-OCC clocks are available, you can use them for the pipeline clock as long as you apply the -head_scan_flop true option of the
set_pipeline_scan_data_configuration command.

Ensure that the OCC clock clocks at least one wrapper cell.

If the OCC clock is used for I/O logic in your design, you can do this using either of the following methods:

Use the maximized reuse flow.

If you are using the simple wrapping flow, consider using the maximized-reuse flow instead:

dc_shell> set_wrapper_configuration -class core_wrapper -maximize_reuse enable

This flow chooses wrapper cell clocks based on the I/O logic associated with each port.

Use system clocks in the simple wrapper flow.

If you must use the simple wrapper flow, use the shared wrapper cell style:

dc_shell> set_wrapper_configuration -class core_wrapper -style shared

Simple shared wrapper cells also choose wrapper cell clocks based on the I/O logic associated with each port.

If you must use dedicated wrapper cells, then configure them to use the system clock from the I/O logic instead of a dedicated
wrapper clock:

dc_shell> set_wrapper_configuration -class core_wrapper \


-use_system_clock_for_dedicated_wrp_cells enable

If you do not resolve this issue, the core's wrapper chains will not function properly when the core is placed in outward-facing mode
during top-level testing. However, you can still perform core-level debugging in TetraMAX ATPG by enabling the PLL bypass mode (with
the run_drc –patternexec wrp_of_occ_bypass command).
Workaround

Product L1
TestMAX DFT (/s/detail/01t1U000003IXzUQAW)

Additional Product(s)
TestMAX ATPG (80003968)

Article Number
000018057

Last Published Date


12/11/2019, 12:51 PM

Article Record Type


How To

URL Name
Why-Do-I-Get-an-S1-DRC-Violation-in-wrp-of-Mode-When-Using-an-OCC-Pipeline-Clock-1576092525338

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