COMPUTER SYSTEM ARCHITECTURE

[FOR LIMITED CIRCULATION]

Editorial Board

Dr. Charu Gupta

Ms. Aishwarya Anand Arora
Content Writers

Dr. Reema Thareja, Ms. Asha Yadav

Academic Coordinator

Deekshant Awasthi

© Department of Distance and Continuing Education

E-mail: [email protected]
[email protected]

Published by:
Department of Distance and Continuing Education
Campus of Open Learning, School of Open Learning,
University of Delhi, Delhi-110007

Printed by:
School of Open Learning, University of Delhi
 COMPUTER SYSTEM ARCHITECTURE

External Reviewer
Dr. Seema Thakur
Disclaimer Assistant Professor
Shaheed Rajguru College of Applied Sciences for Women,
University of Delhi

Corrections/Modifications/Suggestions proposed by Statutory Body, DU/

Stakeholder/s in the Self Learning Material (SLM) will be incorporated in
the next edition. However, these corrections/modifications/suggestions will be
uploaded on the website https://sol.du.ac.in. Any feedback or suggestions may
be sent at the email- [email protected]

Printed at: Taxmann Publications Pvt. Ltd., 21/35, West Punjabi Bagh,
New Delhi - 110026 (600 Copies, 2024)

Department of Distance & Continuing Education, Campus of Open Learning,

School of Open Learning, University of Delhi
 Contents

PAGE

Lesson 1: Digital Logic Circuits 1–31

Lesson 2: Digital Components 32–49

Lesson 3: Data Representation 50–74

Lesson 4: Basic Computer Organization and Design 75–95

Lesson 5: Addressing Modes 96–109

Lesson 6: Input Output Organization 110–129

Glossary 131–133

PAGE i
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture_Content.indd 1 10-09-2024 17:05:43

Computer System Architecture_Content.indd 2 10-09-2024 17:05:43
 L E S S O N

1
Digital Logic Circuits
Asha Yadav
Assistant Professor
Department of Computer Science
School of Open Learning
University of Delhi
Email-Id: [email protected]

STRUCTURE
1.1 Learning Objectives
1.2 Introduction
1.3 Basic Components of a Digital Computer
1.4 Hardware and Software
1.5 Binary Information
1.6 Logic Gates
1.7 Boolean Algebra
1.8 Representation of Boolean Expression
1.9 K-Map (Karnaugh MaP)
1.10 Combinational Circuit
1.11 Sequential Circuit
1.12 Flip-flops
1.13 Summary
1.14 Answers to In-Text Questions
1.15 Self-Assessment Questions
1.16 References
1.17 Suggested Readings

PAGE 1
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 1 12-09-2024 17:25:28

 COMPUTER SYSTEM ARCHITECTURE

Notes
1.1 Learning Objectives
After reading this lesson you will be able to:
‹ ‹Applythe functions of logic gates such as AND, OR, NOT, XOR,
and NAND in digital circuits.
‹ ‹Evaluateand construct Boolean expressions, truth tables, and apply
Boolean laws to simplify digital circuits.
‹ ‹Optimize logic expressions using methods like Karnaugh maps to
enhance circuit efficiency.
‹ ‹Explain the operation of various flip-flops (SR, D, JK, T) and their
applications in sequential circuits.
‹ ‹Design combinational circuits by applying logic gates and Boolean
algebra.

1.2 Introduction
Since you are already familiar with the concept of compiler and inter-
preter in your previous semester, in this course you will learn about
computer system architecture. Let’s first understand the definition of
computer system architecture: “Computer architecture is concerned
with the structure and behaviour of the computer as seen by the user.
It includes the information formats, the instruction set and techniques
for addressing memory. The architectural design of a computer is con-
cerned with the specifications of the various functional modules, such as
processors and memories, and structuring them together into a computer
system.” (Ref 1)
Hence, computer system architecture can be thought of as the blueprint
of a computer. Imagine you’re building a house—just like you need
a plan that shows where all the rooms, doors, and windows go simi-
larly a computer needs a plan that shows how its different parts work
together. When you study this course, you gain a deep understanding of
how computers work at a fundamental level, that is how they process
instructions, manage data, and communicate between various components.
In this course we’re interested in understanding how the computer is
organized and how it behaves when you use it. This includes things

2 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 2 12-09-2024 17:25:28

 Digital Logic Circuits

like how data is stored and processed, what kind of instructions the Notes
computer can understand, and how it keeps track of where everything
is stored in memory. When we talk about the architectural design of
a computer, we’re really talking about how we put all the important
pieces—like the processor, which does the calculations, and the memory,
where data is stored—together to create a system that works smoothly
and efficiently. This lesson will help you to gain a basic idea of digital
computers, introducing you the concept of logic gates and its function.
As we go along, we learn about Boolean algebra, a powerful tool that
helps us make these circuits more efficient by simplifying and analys-
ing them. So, digital logic isn’t just about learning how circuits work;
it’s also about developing a strong analytical mind and learning how
to solve problems.

1.2.1 Digital Computers

A digital computer is a machine that processes information using num-
bers (binary numbers 0 and 1). Think of it like a very fast calculator
that can do much more than just simple arithmetic. Everything a digital
computer does—whether it’s running a program, playing a video, or
displaying text—is done by operating on these binary numbers. It takes
input, processes it according to instructions (which are also in binary
form), and then produces output. Internally, the computer is made up
of many tiny components like transistors and logic gates, which work
together to perform all these operations. These components are orga-
nized into various parts like the processor (which does the thinking)
and memory (which stores information). So, in simple terms, a digital
computer is a highly organized system that processes data using binary
numbers to perform a wide range of tasks, from basic calculations to
complex problem-solving.

1.2.2 History
The early 20th century saw several significant turning points in the
development of digital computers Table 1.1 given below discusses some
of the important developments of each major era:

PAGE 3
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 3 12-09-2024 17:25:28

 COMPUTER SYSTEM ARCHITECTURE

Notes Table 1.1: History of Digital Computers

Era Developments
Mechanical era The development of contemporary computers
was facilitated by early computing devices such
as the mechanical calculator and abacus.
Electromechanical era Relays and vacuum tubes were used in devices
like the Colossus and the Zuse Z3.
Electronic era Totally electronic digital computers first appeared
in 1945 with the release of the ENIAC.
Transistor era Smaller, more effective computers were made
possible by the 1950s replacement of vacuum
tubes with transistors.
Integrated Circuit era The invention of integrated circuits in the
1960s made microprocessors possible, which
in turn allowed for the development of personal
computers.
Modern era Developments in semiconductor technology, the
widespread use of the internet, and the emergence
of artificial intelligence have all contributed to
the continuous expansion of the capabilities of
digital computers.

1.3 Basic Components of a Digital Computer

A digital computer typically consists of several key components:
‹ ‹Central Processing Unit (CPU): Often referred to as the brain of
the computer, the CPU performs arithmetic and logic operations,
controls data flow, and executes instructions from programs.
‹ ‹Memory Unit: This is where data and instructions are stored temporarily
(RAM) or permanently (ROM). Modern computers also use various
types of non-volatile storage, such as solid-state drives (SSDs).
‹ ‹Input Unit: Devices like keyboards, mouse, and scanners allow
users to input data into the computer.
‹ ‹Output Unit: Monitors, printers, and speakers are used to output
data in a form which human can understand.
4 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 4 12-09-2024 17:25:28

 Digital Logic Circuits

‹ ‹Storage Unit: Hard drives, SSDs, and external storage media are Notes
used for long term data storage.

Figure 1.1: Digital Computer (Block Diagram)

Figure 1.1 shows the various components of a digital computer and their
interaction amongst each other.

1.4 Hardware and Software

This section will help you understand the characteristic and interaction
between hardware and software, which is fundamental towards under-
standing how digital computers operate. These two components form
the backbone of any computing system, each playing a separate but
complementary role.

PAGE 5
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 5 12-09-2024 17:25:29

 COMPUTER SYSTEM ARCHITECTURE

Notes Hardware: It refers to the physical components of a computer system that

you can touch and see. These components are responsible for executing
tasks, storing data, and providing interfaces for user interaction. Key
hardware components include:
‹ ‹Central Processing Unit (CPU): The CPU, often called the brain
of the computer, performs calculations and executes instructions.
It consists of:
� Arithmetic Logic Unit (ALU): Executes arithmetic and logical
operations.
� Control Unit (CU): Directs the operation of the processor,
telling the ALU, memory, and input/output devices how to
respond to the instructions received.
� Registers: Small, fast storage locations within the CPU that
hold data temporarily during processing.
‹ ‹Memory Unit: The component where data and instructions are
stored. It is divided into:
� Primary Memory: Random Access Memory (RAM) is a volatile
memory that temporarily stores data and instructions that the
CPU needs while performing tasks.
� Secondary Memory: Non-volatile storage used for long term
data retention, such as hard drives, SSDs, and external storage
devices.
� ROM (Read Only Memory): Non-volatile memory that
contains essential instructions for booting up the computer
and performing basic operations.
‹ ‹InputDevices: These devices allow users to input data into the
computer, for example keyboard, mouse and scanner.
‹ ‹Output Devices: Output devices display or produce the results of
computer processes, like monitor, printer and speakers.
‹ ‹Motherboard: The motherboard is the main circuit board that
connects all the hardware components. It includes sockets for the
CPU, RAM, and expansion cards, as well as connections for input
and output devices.

6 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 6 12-09-2024 17:25:29

 Digital Logic Circuits

‹ ‹Storage Devices: These devices store data permanently. Common Notes

storage devices include Hard Disk Drives (HDDs) and Solid-State
Drives (SSDs).
Software: Software refers to the intangible components of a computer
system—the programs and applications that run on the hardware. Software
can be broadly categorized into two types: system software and appli-
cation software.
‹ ‹System Software: System software manages the hardware and
creates an environment for application software to run. Key types
of system software include Operating System (OS) and Utility
Programs.
‹ ‹Application Software: Software programs that interact with users
to perform specific task and activities like software for presentation,
text processing and database.

Interaction Between Hardware and Software

The interaction between hardware and software is a cornerstone of
computer operation, users have access to application software that sends
instructions to the OS. The OS interprets these instructions and sends
commands to the hardware then hardware executes the commands,
performing tasks like computation, data storage, or rendering graphics.
The results are sent back through the OS to the application software,
providing output to the user.
For example, when a user types a document in a word processor key-
board (input device) sends keystrokes to the CPU, OS processes these
inputs and updates the document and updated document is displayed on
the monitor (output device).

1.5 Binary Information

Binary information is the most basic form of data that a digital computer
understands. It’s like the computer’s native language, and it consists only
of two symbols: 0 and 1. Imagine flipping a light switch—it’s either on
(which we can think of as a 1) or off (which we can think of as a 0).
Similarly, binary information uses these two states (0, 1) to represent all

PAGE 7
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 7 12-09-2024 17:25:29

 COMPUTER SYSTEM ARCHITECTURE

Notes kinds of data. These binary digits, also known as bits, are the building
blocks of all digital system operations and data storage. They are the
smallest unit of data in computing.
For example, when you type a letter on your keyboard, the computer
translates that letter into a specific combination of 0s and 1s. These com-
binations might represent anything from numbers and letters to instructions
for the computer on what to do next. The reason we use binary is because
it’s simple and reliable. The computer’s internal circuits, made up of mil-
lions of tiny switches, can easily distinguish between two states—on or
off, 0 or 1—allowing them to process and store information efficiently.
So, binary information is essentially the fundamental way that computers
encode, process, and communicate all the data they handle.
In nutshell binary information in digital computers is represented using
0 and 1. Binary signals, corresponding to these states, are electrical
voltages or currents where specific levels represent 0 or 1, enabling
the encoding, processing, and transmission of data within and between
computer components.

1.6 Logic Gates

Binary logic involves binary variables and operations that hold logical
significance. It is utilized in algebraic or tabular forms for the manipu-
lation and processing of binary information. This manipulation is carried
out by components known as logic gates. Logic gates are switches within
computers that change their state from on to off based on user input. The
essential components of computers are logic gates, which turn on when
a given condition is met and turn off when it is not. By determining
whether the incoming data satisfies a certain criterion, they provide an
output of true (ON) or false (OFF). Remember that true is equivalent to
on or 1, and false is equivalent to off or 0.
The basic components of digital circuits are digital logic gates. They
carry out the fundamental logical operations required for digital com-
putation. The most common digital logic gates are explained in detail
below Table 1.2.

8 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 8 12-09-2024 17:25:29

 Digital Logic Circuits

Table 1.2: Logic Gates Notes

PAGE 9
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 9 12-09-2024 17:25:29

 COMPUTER SYSTEM ARCHITECTURE

Notes

Note that NAND and NOR gates are also called universal gate because
they can be used to create any digital circuit.

1.7 Boolean Algebra

This section explains Boolean algebra, which is a way of working with
logical statements that are either true or false, represented by 0 and 1.
Developed by George Boole in 1847, it’s the backbone of computer sci-
ence and digital logic. In Boolean algebra, you deal with variables that
can only be 0 or 1, and you use logical operators like AND, OR, and
NOT to combine, simplify, and change these statements. It’s basically a
set of rules that helps you understand how different logical connections
work. You’ll find it super useful in programming, designing digital cir-
cuits, and any kind of logical thinking in math. It’s like the language of
computers, and learning it gives you a solid foundation for understanding
how computers think and process information.

1.7.1 Boolean Function

Boolean Function is a mathematical formula that turns a set of binary
inputs into a single binary output. This output shows how the inputs are
related logically. In Boolean algebra or equations, a variable can exclusively
take one of two values: FALSE (0) or TRUE (1). Expressions that can
be evaluated as either TRUE or FALSE are termed Boolean expressions
10 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 10 12-09-2024 17:25:29

 Digital Logic Circuits

or truth functions, and the outcomes TRUE or FALSE are referred to Notes
as truth values. Variables capable of holding truth values are known as
logical variables or binary valued variables. A decision resulting in either
TRUE or FALSE is called a Binary decision.
Logic operations like AND, OR, and NOT are often used to describe
Boolean functions, along with their symbols. They are very important in
digital logic design because they show how digital circuits work and are
used for jobs like logic synthesis, optimisation, and analysis. There are
different ways to show boolean functions, such as truth tables, Boolean
expressions, logic gates, and Karnaugh maps. Each gives a different view
of the function’s behaviour and features.
Example: F(A, B, C) = A + Bʹ + C defines a boolean function that takes
3 inputs A, B, C and evaluates the output as (A) OR (NOT (B)) OR C.

1.7.2 Truth Table

Truth table is a tabular representation of the possible input combinations
and their corresponding output for a Boolean function. It is structured
such that every row represents a distinct combination of input values,
while the columns comprise the input variables and the output variable,
respectively. The values presented in the table are Boolean in nature; that
is they are in 0 and 1 form (or T and F form). Truth tables are commonly
used in digital logic design to describe the behavior of logical functions
and circuits. The Boolean function given in example above can be rep-
resented as truth table given in Table 1.3.

Table 1.3: Truth Table of F(A, B, C) = A + Bʹ + C

Input Output
A B C F

0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
PAGE 11
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 11 12-09-2024 17:25:29

 COMPUTER SYSTEM ARCHITECTURE

Notes
1.7.3 Logic circuit
Logic circuit is a graphical representation of a digital circuit having logic
gates and their interconnections. We have already studied the graphical
representation of various logical operators as gate in section 1.6. The
Logic circuit for Table 1.3 is shown in Figure 1.2.

Figure 1.2: Logic Diagram

The purpose of Boolean algebra for digital circuits is multifaceted. It
provides a formal language for expressing logical functions, enables sys-
tematic circuit design and optimization, facilitates rigorous analysis and
verification, and ultimately contributes to the development of efficient,
reliable, simplified and cost-effective digital systems.

1.7.4 Boolean Laws

Here we’re going to dive into Boolean laws, which are the basic rules that
help us work with logic expressions in digital systems. Just like in regular
algebra where we use rules to simplify equations, boolean laws allow us to
simplify logical expressions, which are made up of variables that can either
be true (1) or false (0). Some Boolean laws are given in Table 1.4 below.
Table 1.4: Boolean Laws

12 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 12 12-09-2024 17:25:30

 Digital Logic Circuits

These laws—like the Commutative, Associative, and Distributive Laws— Notes

are essential for reducing the complexity of logic circuits, making the
logic circuits more efficient and easier to understand. So, let’s start by
looking at how these laws apply and why they’re so important in digital
logic design.

Boolean expression simplification using Boolean laws

While simplifying a Boolean expression we can use the laws given in
Table 1.4 and follow the below mentioned operator precedence:
Parenthesis >> NOT >> AND >> OR
Example: Simplify the expression below:

Note the • symbol can also be dropped from the expression i.e. no symbol
between variables also indicates AND operation like A • B = AB

IN-TEXT QUESTION
1. Simplify the following Boolean expressions:
(a) Y = BC + BCʹ + BA
(b) Y = A + AʹB + AʹBʹC + AʹBʹCʹD + AʹBʹCʹDʹE

1.8 Representation of Boolean Expression

The term “Boolean expression” refers to the logical statement that contains
Boolean variables and logical operators that can evaluate to either true
(1) or false (0). Boolean expressions may be expressed in two distinct
forms: the first is the Sum of Products (SOP) form, and the second is the
Product of Sums (POS) form. To understand SOP and POS lets introduce
you to the concept of minterm which is very essential for this section.

PAGE 13
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 13 12-09-2024 17:25:30

 COMPUTER SYSTEM ARCHITECTURE

Notes A minterm is nothing else but a combination of variables in a truth table,

i.e. a truth table with 2 variable will have 4 (22) minterms. Now lets get
back to Boolean expression forms:
Sum of Products (SOP): SOP form of Boolean expressions is the one
that adds up the products of two or more input variables (that give 1 as
output). Each minterm corresponds to a row in the truth table where the
function output is true (1). Let’s understand this in simple terms, suppose
you have a logical problem where you want to know when a certain
condition is true. To solve this, you list out all the specific scenarios
(combinations of variables) where the condition is true. Each of these
scenarios is called a product, where you AND together the variables in
either their true or complemented form. The SOP form then combines
these products using OR operations, so it shows all the different ways
the condition can be true. It’s like saying, “The condition is true if this
happens OR that happens.” The SOP form helps us clearly see all the
situations where our logic circuit gives a true output.
‹ ‹Minterm (SOP) Representation: Each minterm is represented
as ABCD where A, B, C, D are the variables, and the minterm
represents a specific combination of these variables. Consider truth
table given below:

A B C Y
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 1

The canonical (or standardized) SOP form of Boolean expression derived

from truth table for Y is

14 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 14 12-09-2024 17:25:30

 Digital Logic Circuits

It can be minimized (using boolean laws mentioned previously in Table 1.4) Notes
to give a simpler expression (minimal SOP form) as:

Points to Remember
1. Both the Canonical SOP form and the minimal SOP form can be
interconverted efficiently by employing a truth table method.
2. Every individual term within the SOP form, recognized as minterms,
contributes distinctly to the expression.
Product of Sum (POS): The Boolean expressions that produces the prod-
uct of sum for two or more input variables (that give 0 as output). Each
“Sum” term in the POS form is known as a “maxterm” and each maxterm
corresponds to a row in the truth table where the function output is false
(0). Further the POS combines these maxterm (sum terms) by product.
Consider truth table given below:
A B C Y
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 1
The canonical POS form of Boolean expression derived from truth table
for Y is
Y = (A + B + C)(A + Bʹ + Cʹ)(Aʹ + Bʹ + C)
PAGE 15
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 15 12-09-2024 17:25:30

 COMPUTER SYSTEM ARCHITECTURE

Notes It can be minimized as:

Y = (A + B + C)(A + Bʹ + Cʹ)(Aʹ + Bʹ + C)
Y = (A + (B + C)(Bʹ + C))(Aʹ + Bʹ + C)
Switching between Canonical POS form and its minimal version, and
vice versa, can be done using a truth table.

1.9 K-Map (Karnaugh MaP)

We have already studied the process of simplifying Boolean expressions
using Boolean algebraic rules, but this is not always unique, and in most
cases, the resulting expression is not in its minimal form. Thus, K-map
technique will be employed to achieve uniqueness and obtain the final
minimal form. This section provides an overview of K-maps, explaining
the grouping of variables and simplification procedure.

Key points
� The number of cells in a Karnaugh map (K-map) corresponds to
the total number of possible combinations of input variables.
‹ ‹This total number of possible combinations is calculated using the
formula: 2n, where n represents the number of input variables in
the Boolean expression.
‹ ‹Each cell in the K-map represents a unique combination of input
values, with the number of cells equalling the number of possible
cases.
‹ ‹For example, if there are 3 input variables, there will be 23 i.e. 8
cells in the K-map, where each variable can independently take on
one of two binary values (0 or 1).

Steps of map simplification

1. Determine the Number of Cells: Select the number of cells based
on the number of input variables. For n input variables, there will
be 2n cells in the Karnaugh map (K-map).
2. Identify SOP or POS Form:
� Identify whether the given problem is in Sum of Products (SOP)
or Product of Sums (POS) form.

16 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 16 12-09-2024 17:25:30

 Digital Logic Circuits

� For SOP form, mark the cells corresponding to minterms with Notes
‘1’, and fill the rest with ‘0’.
� For POS form, mark the cells corresponding to maxterms with
‘0’, and fill the rest with ‘1’.
� In POS form, take the complement of the output variable to
obtain the resultant expression.
3. Group Terms:
Group the terms (either 0’s or 1’s) in rectangular shapes, with the
total number of terms being 2, 4, 8, (2n) etc., covering as many
elements as possible in one group. Groups can overlap each other,
opposite and corner grouping is allowed, also there can be no
diagonal groups (Remember to make a group as large as possible).
4. (a) Find Product Terms for SOP: From the groups formed, identify
the product terms for SOP form, product terms in SOP form
represent the product (AND) of input variables.
(b) F
 ind Sum Terms for POS: From the groups formed identify
the sum terms for POS form, sum terms in POS form represent
the sum (OR) of input variables.
The maps of two, three and four variable functions is given below:

Figure 1.3: k-maps (Ref 1)

k-maps help facilitating the reduction of logic circuits and expressions to

their minimal forms. Below is a k-map simplification example.
Minimize the F(A, B, C, D) = Σ(0, 1, 2, 5, 7, 8, 9, 10, 13, 15)
The k-map of the above function is a 4 variable k-map given below

PAGE 17
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 17 12-09-2024 17:25:30

 COMPUTER SYSTEM ARCHITECTURE

Notes

Now,

Thus, minimized boolean expression is-

F(A, B, C, D) = BD + C′D + B′D′
Don’t Care Conditions
The “Don’t care” condition says that we can use the blank cells of a
K-map to make a group of the variables. To make a group of cells, we
can use the “don’t care” cells as either 0 or 1, and if required, we can
also ignore that cell. We mainly use the “don’t care” cell to make a large
group of cells. The cross (×) symbol is used to represent the “don’t care”
cell in K-map.
Rules for Karnaugh Maps with Don’t Care Conditions
1. After forming the K-Map, fill 1’s at the specified positions corresponding
to the given minterms. Fill X at the positions where don’t care
combinations are present.
2. Now, Encircle the groups in the K-Map. One thing to be kept in
mind is, now we can treat Don’t Care conditions (X) as 1s if these
help in forming the largest groups. No such group can be encircled
whose all the elements are X.
3. If still there are 1s left which doesn’t get encircled in any of the
groups, then these isolated 1s are encircled individually.
4. Now, recheck all the encircled groups, and remove any redundancy
if present.
5. Write the Boolean expression for each encircled group.
6. The final minimal expression can be obtained by circling each
Boolean expressions that were obtained from each group.
18 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 18 12-09-2024 17:25:30

 Digital Logic Circuits

Minimise the following function in SOP minimal form using K-Maps: Notes
F(A, B, C, D) = Σ(1, 2, 6, 7, 8, 13, 14, 15) + d(0, 3, 5, 12)
The SOP K-map for the given expression is:

1.10 Combinational Circuit

A combinational circuit is a kind of digital circuit that only uses the
present inputs to generate output. It doesn’t have any memory or feedback
built in, so the output is only affected by the current input. Logic gates
are used to make combinational circuits. The output is determined by
the logical function on the input data. Different kinds of digital systems
use these circuits to do calculations, handle data, and make decisions.

Figure 1.4: Combinational Circuit

Example of Combinational Circuit

An adder is a combinational digital circuit that performs addition of numbers.
Adders are classified into two types: Half Adder and Full Adder. Both the
adders along with circuit diagram are discussed in subsequent subsection.
PAGE 19
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 19 12-09-2024 17:25:30

 COMPUTER SYSTEM ARCHITECTURE

Notes
1.10.1 Half Adder
The half adder adds two binary digits and produces two outputs as sum
and carry. It consists of one XOR logic gate producing “SUM” and one
AND gate producing “CARRY” as outputs.
Logical Expression for half adder is: S = A ⊕ B; C = A*B.

A S (Sum)
Half Adder
B C (Carry)

Figure 1.5: Half Adder (Block Diagram)

The circuit diagram and truth table of half adder is shown below it has
two inputs A, B and produces sum and carry as output.

Figure 1.6: Half Adder (Circuit diagram and truth table)

Limitation: The main problem with the Half Adder circuit is that it can
only add two values and doesn’t care about carry. Thus, Full Adder was
developed.

1.10.2 Full Adder

A full adder is a combinational logic circuit that performs the addition
of three binary digits. It is an essential component in digital electronics,
particularly in arithmetic operations within processors and other com-
puting devices.

20 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 20 12-09-2024 17:25:30

 Digital Logic Circuits

The full adder has three inputs: Notes

1. A - The first digit.
2. B - The second digit.
3. Cin - The carry input, which is a digit carried over from the addition
of less significant bits (bits from right).
The full adder produces two outputs:
1. S (Sum) - This is the result of the addition of the three input bits,
excluding any carry out.
2. Cout (Carry out) - This is the carry output, representing any overflow
from the addition, which can be passed to the next more significant
bit in a multi-bit addition.
The operation of the full adder can be depicted by the following equations:
‹ ‹Sum (S) = A ⊕ B ⊕ Cin, where ⊕ denotes the XOR (exclusive
OR) operation.
‹ ‹Carry out (Cout) = (A AND B) OR (Cin AND (A ⊕ B)), where
AND and OR are the standard logical operations.

A S (Sum)
Full Adder
B Cout (Carry)

Cin
Figure 1.7: Full Adder (Block Diagram)

A full adder circuit can be constructed using two half adders and an OR
gate. In this configuration, the first half adder adds the inputs A and B,
generating a partial sum. The second half adder then adds this partial sum
to the carry input Cin, producing the final sum output, S. If either half
adder generates a carry, the overall carry output, Cout, will be produced
by taking the OR of the carry outputs from both half adders.
A full adder, which uses the previous carry as an input, is ideal for
adding multi-digit binary numbers. To add such numbers, multiple full
adders are connected in a series, or cascade. The number of full adders
required in this cascade is equal to the number of binary digits (bits) in
the numbers being added.
PAGE 21
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 21 12-09-2024 17:25:30

 COMPUTER SYSTEM ARCHITECTURE

Notes

Figure 1.8: Full Adder (Circuit diagram and truth table)

Uses
‹ ‹They are fundamental in constructing various digital devices.
‹ ‹These circuits are used to create complex arithmetic and logic
circuits, such as Arithmetic Logic Units (ALUs).
‹ ‹Primarily designed for adding binary numbers, they also serve in
other applications including:
‹ ‹Binary-Coded Decimal (BCD) operations
‹ ‹Address decoding
‹ ‹Table index calculation

1.11 Sequential Circuit

Combinational circuit does not use any memory. Hence the previous state
of input does not have any effect on the present state of the circuit. But
sequential circuit has memory so output can vary based on input. This
type of circuit uses current input, previous output, clock and a memory
element.
Sequential circuits are an integral part of digital electronics, designed to
store and process information over time. Unlike combinational circuits,
which rely solely on the current input to produce an output, sequential
circuits maintain state information, allowing them to remember past inputs
and produce outputs based on both current and past inputs. One common
example of a sequential circuit is a Finite State Machine (FSM), which
consists of a set of states, transitions between these states, and outputs
associated with each state. FSMs are widely used in various applications,
including control systems, digital signal processing, and communication

22 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 22 12-09-2024 17:25:31

 Digital Logic Circuits

protocols. For instance, consider a traffic light controller. It operates as Notes

a finite state machine, with states representing different traffic light con-
figurations (e.g., green light for “go,” yellow light for “prepare to stop,”
and red light for “stop”). The controller transitions between these states
based on inputs such as vehicle presence and pedestrian signals, ensuring
safe and efficient traffic flow. Using memory elements like flip-flops
and feedback loops, sequential circuits enable complex behaviour and
decision-making capabilities in digital systems. The most common type
of sequential circuit is a synchronous sequential circuit that provides a
clock input so that the output bits are stored at discrete interval of times
The block diagram of sequential circuit is represented in the figure below:

Figure 1.9: Sequential Circuit

1.12 Flip-flops
Flip-flops are a type of sequential circuit and are not just standalone
components; they’re actually derived from logic gates. Once a specific
input value is provided, flip-flops retain and execute it, provided the
logic gates are configured accurately. Flip-flops can be used to create
memory by applying Boolean logic. In fact, flip-flops can be viewed as
the foundational concept behind Random Access Memory (RAM). They
store 1 bit information. There are four types of flip-flops that are used
commonly:
‹ ‹S-R Flip-flop
‹ ‹D Flip-flop
PAGE 23
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 23 12-09-2024 17:25:31

 COMPUTER SYSTEM ARCHITECTURE

Notes ‹ ‹J-K Flip-flop

‹ ‹T Flip-flop

S-R Flip-flop
The basic Set -Reset flip-flop, is a type of flip-flop circuit that stores
one bit of data. It has two inputs, S (set) and R (reset), and two outputs,
Q and the complement of Q.

Figure 1.10: S-R Flip-flop (Ref 1)

The behaviour of an SR flip-flop is defined below:

‹ ‹When S = 1 and R = 0, the flip-flop sets to the state Q = 1.
‹ ‹When S = 0 and R = 1, the flip-flop resets to the state Q = 0.
‹ ‹When both S and R are 0, the flip-flop maintains its previous state.
‹ ‹When both S and R are 1, the behaviour is undefined and results
in a “forbidden” state, which can lead to unpredictable behaviour
in practical implementations.
The SR flip-flop is widely used in digital circuits for various applica-
tions, such as memory storage, data synchronization, and control circuits.
However, due to its susceptibility to the forbidden state, more advanced
flip-flop types like D flip-flops and JK flip-flops are often preferred in
modern digital designs.

D Flip-flop
A D flip-flop or delay flip-flop is a type of flip-flop circuit used in
digital electronics to store and transfer data. It has a single data input
(D), a clock input (CLK), and two outputs: the normal output (Q) and
its complement. The D flip-flop operates as follows:

24 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 24 12-09-2024 17:25:31

 Digital Logic Circuits

1. Data Input (D): The data input determines the state the flip-flop Notes
will store when the clock signal transitions. When the clock signal
changes, the value at the data input is transferred to the output.
2. Clock Input (CLK): The clock input controls when the data input
is sampled and transferred to the output. The flip-flop changes its
state only on the rising or falling edge (depending on the specific
implementation) of the clock signal.
� When the clock signal transitions (typically from low to high or
high to low, depending on the specific flip-flop implementation),
the value present at the data input (D) is transferred to the
output (Q).
� Between clock transitions, the output state remains stable and
holds the previously sampled value.
D flip-flops are widely used in digital systems for various purposes,
including data storage, synchronization, and control. They are particu-
larly useful for storing data that needs to be synchronized with a clock
signal, making them essential components in sequential logic circuits like
counters, shift registers, and memory elements.

Figure 1.11: D Flip-flop (Ref 1)

JK Flip-flop
A JK flip-flop is a type of sequential logic circuit used in digital elec-
tronics for storing and transferring binary data. It has two data inputs,
labelled J and K, a clock input (CLK), and two outputs: the normal output
(Q) and its complement.
The JK flip-flop has four possible operating modes, which are determined
by the combinations of inputs J and K:

PAGE 25
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 25 12-09-2024 17:25:31

 COMPUTER SYSTEM ARCHITECTURE

Notes 1. Set Mode: When J = 1 and K = 0, the flip-flop sets to the state
where Q = 1 , regardless of the previous state.
2. Reset Mode: When J = 0 and K = 1, the flip-flop resets to the
state where Q = 0 , regardless of the previous state.
3. Toggle Mode: When both J and K are set to 1 (J = 1 and K = 1),
the flip-flop toggles its output. If the previous state was Q = 1, the
next state will be Q = 0, and vice versa.
4. No Change Mode: When both J and K are set to 0 (J = 0 and
K = 0), the flip-flop maintains its current state, regardless of the
clock input.
The operation of a JK flip-flop is synchronized with a clock signal (CLK).
The flip-flop changes its state (according to the operating mode) only on
the rising or falling edge of the clock signal, depending on the specific
implementation.
JK flip-flops are widely used in digital systems for various applications,
including frequency dividers, counters, shift registers, and memory ele-
ments. They offer more flexibility compared to other types of flip-flops,
such as the D and SR flip-flops, due to their ability to operate in multiple
modes and toggle functionality.

Figure 1.12: JK Flip-flop (Ref 1)

T flip-flop
A T flip-flop, also known as a toggle flip-flop, is a type of sequential
logic circuit used in digital electronics to toggle its output state based
on the transitions of its inputs. It has a single input (T), a clock input
(CLK), and two outputs: the normal output (Q) and its complement.

26 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 26 12-09-2024 17:25:31

 Digital Logic Circuits

The behaviour of a T flip-flop is quite straightforward: Notes

1. Toggle Functionality: The T flip-flop toggles its output state (Q)
whenever the clock input (CLK) transitions from one state to another
(e.g., rising edge, falling edge).
2. Input Transition: When the clock input transitions and the input T
is high (1), the flip-flop changes its output state to the complement
of its current state. If Q was 0, it becomes 1, and if Q was 1, it
becomes 0. If T is low (0), the output state remains unchanged.
In summary, the T flip-flop toggles its output state whenever the clock
input transitions, and the input T is high. When T is low, the output state
remains the same.
T flip-flops find applications in digital systems where toggling functionality
is required, such as in counters, frequency dividers, and sequential logic
circuits where alternating states are needed. They are particularly useful
for generating square waves and controlling the timing of digital signals.

Figure 1.13: T Flip-flop (Ref 1)

Edge Triggered Flip-flop

An edge-triggered flip-flop is a form of sequential logic circuit that alters
its state (output) exclusively during specific edges (transitions) of a clock
signal. Contrary to level-triggered flip-flops, edge-triggered flip-flops are
sensitive to the change in the clock signal from one state to another, such
as the rising or falling edge.
There exist two prevalent varieties of edge-triggered flip-flops:
1. The positive edge-triggered flip-flop, also referred to as the rising
edge-triggered flip-flop, only changes its output state when the clock
signal experiences a rising edge. When the clock signal transitions
PAGE 27
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 27 12-09-2024 17:25:31

 COMPUTER SYSTEM ARCHITECTURE

Notes from low to high, the output updates from the current state to the
new state.
2. The negative edge-triggered flip-flop, also referred to as the falling
edge-triggered flip-flop, alters its state or output exclusively when
the clock signal experiences a falling edge. Therefore, the output
undergoes a change from its current state to a new state when the
clock signal transitions from a high voltage level to a low voltage
level.

Figure 1.14: Edge Triggered Flip-flop (Ref 1)

Edge-triggered flip-flops are extensively employed in digital systems to

ensure synchronisation and regulate timing. By selectively initiating the
state transition exclusively at points of the clock signal, they guarantee
that the output alterations happen with utmost accuracy at the required
moments, thereby circumventing any potential problems such as violations
of setup and hold time. They play a crucial role in constructing depend-
able and effective sequential logic circuits, such as counters, registers,
and memory elements.

Master-Slave Flip-flop
A master-slave flip-flop is a sequential logic circuit that consists of two
interconnected flip-flops, namely a master flip-flop and a slave flip-flop.
The master flip-flop is triggered by the leading edge (either positive or

28 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 28 12-09-2024 17:25:31

 Digital Logic Circuits

negative) of the clock signal, whereas the slave flip-flop is triggered by Notes
the trailing edge of the clock signal. This configuration guarantees that the
outputs of the flip-flop transition between states only at precise moments,
thereby preventing undesired fluctuations and ensuring dependable func-
tionality. The master flip-flop acquires the input data and retains it until
the subsequent clock transition, while the slave flip-flop seizes the output
of the master flip-flop and presents it as the ultimate output. Master-slave
flip-flops are frequently employed in digital systems that require precise
timing and dependable functionality, such as microprocessors, memory
units, and communication systems.

IN-TEXT QUESTIONS
2. What type of signal does a digital system use?
3. How many bits are in a byte?
4. What is the smallest unit of data in a digital system?
5. What is the output of an AND gate when all inputs are 1?
6. What type of circuit has outputs depending only on the current
inputs?
7. What type of circuit includes memory elements?
8. What element is used to store a single bit of data?
9. Which Boolean operation outputs true if at least one input is
true?
10. What mathematical tool is used to simplify Boolean expressions?

1.13 Summary
This chapter lays the groundwork for understanding complex digital
systems by introducing the essential concepts of digital computer, Bool-
ean algebra, and logic gates. It establishes the basic principles that are
crucial for designing and analyzing digital circuits. This chapter explains
combinational circuits, sequential circuits, flip-flops and K-map. Various
types of combinational circuit half adder and full adder are also discussed
in the chapter.

PAGE 29
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 29 12-09-2024 17:25:31

 COMPUTER SYSTEM ARCHITECTURE

Notes
1.14 Answers to In-Text Questions

1. (a)

(b)

2. Digital
3. 8
4. Bit
5. 1
6. Combinational circuit
7. Sequential circuit
8. Flip-flop
9. OR
10. Algebra

1.15 Self-Assessment Questions

1. What are the two types of signals used in digital systems?
2. Define Boolean algebra and its significance in digital logic design.
3. What are the basic Boolean operations.
4. Describe the significance of the truth table in digital logic.
5. What is a logic gate, and what are the types of basic logic gates.
6. Differentiate between SOP and POS.

30 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 30 12-09-2024 17:25:31

 Digital Logic Circuits

Notes
1.16 References
u Computer System Architecture by M. Morris Mano, Third edition,
1993, Prentice Hall of India.
u Computer System Architecture by M. Morris Mano, Third edition,
1993, Pearson Education.

1.17 Suggested Readings

u Sima, D., & Kacsuk, P. (1997). Advanced computer architectures.
Addison-Wesley Longman Publishing Co., Inc.
u Null, L. (2023). Essentials of Computer Organization and Architecture.
Jones & Bartlett Learning.
u Hennessy, J. L., & Patterson, D. A. (2017). Computer architecture:
a quantitative approach. Morgan Kaufmann.

PAGE 31
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 31 12-09-2024 17:25:31

 L E S S O N

2
Digital Components
Asha Yadav
Assistant Professor
Department of Computer Science
School of Open Learning
University of Delhi
Email-Id: [email protected]

STRUCTURE
2.1 Learning Objectives
2.2 Introduction to Digital Components
2.3 Arithmetic Microoperations
2.4 Decoders
2.5 Encoder
2.6 Multiplexer
2.7 Memory Units
2.8 Summary
2.9 Answers to In-Text Questions
2.10 Self-Assessment Questions
2.11 References
2.12 Suggested Readings

2.1 Learning Objectives

After reading the chapter, you will be able to understand and apply the following concepts:
‹ ‹Functionality
and design of decoders.
‹ ‹Decoder expansion techniques.

‹ ‹Comprehension and utilization of multiplexers.

‹ ‹Memory units in digital systems.

32 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 32 12-09-2024 17:25:31

 Digital Components

Notes
2.2 Introduction to Digital Components
Computer systems are made up of a lot of different digital components
that work together to process, store, and send data very quickly and
correctly. The abilities of these systems are greatly affected by each of
these components; from the Central Processing Unit (CPU)’s basic arith-
metic operations to the complex data manipulation done by memory units,
decoders, and multiplexers. Logic gates, microprocessors, and memory
devices like RAM and ROM all work together to make sure that data
processing goes smoothly and quickly.
As technology improves, it becomes more and more important to under-
stand and use these digital components correctly. Advanced components
like microcontrollers, FPGAs, and Digital Signal Processors (DSPs)
improve the functionality of modern devices by performing specific tasks
in different contexts. A/D and D/A converters make it possible for analog
and digital signals to talk to each other. Interface controllers control how
different parts of a system talk to each other. These systems are more
complicated and powerful because they need sensors and actuators to
change physical parameters into digital signals and back again.

2.3 Arithmetic Microoperations

Micro-operations refer to the fundamental operations that a computer executes
on the data stored in its registers. They serve as the essential components
of complex instructions carried out by the CPU. Each micro-operation
carries out a basic task, such as moving data from one register to another,
executing arithmetic or logic operations on data, or altering the contents
of a register. Figure 2.1 shows various categories of micro-operations.

Figure 2.1: Types of Microoperations

PAGE 33
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 33 12-09-2024 17:25:32

 COMPUTER SYSTEM ARCHITECTURE

Notes The basic circuits for arithmetic operations will be discussed in this sec-
tion like add, subtract and increment. Some of the arithmetic operations
and their symbolic representation is provided below in Table 2.1 (where
R represents register)

Table 2.1: Microoperations

Operation Symbol Description
Addition R3  R1  R 2 Add content of R1, R2 and transfer to R3
Subtraction R3  R1  R 2 Sub-content of R2 from R1 and transfer to R3
Compliment R 2  R 2 One’s Compliment of R2
Negate R 2  R 2  1 Two’s Compliment of R2
Increment R1  R1  1 Add 1 to R1
Decrement R1  R1  1 Subtract 1 from R1
Now we discuss the combinational circuits that are used to carry these
operations:
Note: We have already discussed half adder, full adder in Lesson 1.

2.3.1 Binary Adder

A binary adder is a digital circuit that implements the arithmetic sum of
two binary numbers, which can be of any length. The generation process
involves the sequential connection of full-adder circuits. The output is
propagated from one full-adder to the input carry of the next full-adder.
The block diagram showing the interconnections of four full-adder cir-
cuits, which are utilised to facilitate a 4-bit binary adder (an n-bit will
require n full adders) is given in Figure 2.2.

Figure 2.2: Binary Adder

34 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 34 12-09-2024 17:25:34

 Digital Components

The bits of binary number A are added to bits of binary number B, sub- Notes
script numbers are given from right to left, with subscript 0 representing
the least significant bit. The carries are interconnected in a sequential
manner through the utilisation of full adders. The binary adder receives
the input carry signal C0 and produces the output carry signal C4. The
output signals of the full adders generate the required sum bits. The
output of each full-adder is connected to the input carry of the next
higher-order full-adder. The n data bits for the A inputs are sourced
from a single register, specifically R1, while the n data bits for the B
inputs are sourced from another register, specifically R2. The sum can
be transferred to a third register R3 or one of the source registers (R 1
or R2), thereby restoring its previous content.

2.3.2 Binary Adder Subtractor

This section will explain working and implementation of binary adder
subtractor using full adder, to understand the working of the circuit you
need to first know the concept of 1’s and 2’s compliment of a binary
number (though it has been taken in detail in lesson 3).
1’s compliment of a binary number is the value obtained by inverting
all the bits of the given binary number for example 1’s compliment of
11001 is 00110. 2’s compliment can be obtained by adding 1 to the 1’s
compliment of the number (from LSB). For example 2’s compliment of
11001 is 00111.
The binary number subtraction can be obtained by adding the 2’s com-
plement of the addend bits to the augend bits. The 2’s complement can
be obtained by adding 1 to 1’s compliment of the number. The 1’s com-
plement can be achieved by using inverters, and one can be added to the
sum by the input carry. An exclusive-OR gate can be used to combine the
addition and subtraction operations into a single circuit, by incorporating
it with each full adder. The Figure 2.3 illustrates a circuit that performs
addition and subtraction operations using 4 bits.

PAGE 35
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 35 12-09-2024 17:25:34

 COMPUTER SYSTEM ARCHITECTURE

Notes

Figure 2.3: 4-bit Binary Adder Subtractor

The mode input M regulates the operation. When M = 0 the circuit

is an adder and when M = 1 the circuit turns into a subtractor. Each
XOR gate receives input M and one of the inputs of B. When M = 0,
we have B  0  B . The full adders receive the value of B, the input
carry is 0, and the circuit executes add operation on A and B. When
M = 1, we have B  1  B and C0 = 1. The B inputs are all comple-
mented and a 1 is inserted by the input carry. The circuit operates
addition of A with the 2’s complement of B (i.e. subtraction). For
unsigned numbers, this provides A − B � if A ≥ B or the 2’s complement
of ( B − A ) if A < B . For signed numbers, the result is A − B supported
that there is no overflow.

2.3.3 Binary Incrementer

The binary incrementer adds 1 to the existing binary value stored in
the register. This is achieved by using combination of half adders,
to implement n-bit binary incrementer we require “n” half adders.
Thus, the storage capacity of the register is denoted by the number
‘n’ for any n-bit binary incrementer. The value of this register will
be increased by 1.

36 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 36 12-09-2024 17:25:35

 Digital Components

Notes

Figure 2.4: 4-bit Incrementer

A 4-bit incrementer is shown in Figure 2.4, it is a digital circuit that

can add 1 to a 4-bit binary number (increment operation). It functions
by employing four half adders, each of which corresponds to a single
bit of the binary number. The LSB initiates the process, sum S0 and the
carry C1 are generated by adding 1 to first bit A0, where S0 = A0 ⊕ 1
and C1 = A0 AND 1. This carry is subsequently propagated to the subse-
quent bit, A1. The second bit is incremented by adding the carry C1 and
A1from the previous addition, resulting in a new sum S1 and a carry C2.
This process continues through the third bit A2 and fourth bit A3, with
each bit addition involving the sum and carry being passed to the next
higher bit. The incremented 4-bit number S3S2S1S0 is the final output.
The design guarantees that the incrementing operation is both efficient
and straightforward, adding one to the binary number with minimal delay.

2.4 Decoders
As we already know an n bit binary number can represent 2n different
values, a decoder is a combinational circuit that can convert a n-bit binary
code to a maximum of 2n unique output combinations. Thus, decoding
is the process by which binary input code is transformed into a desired
output. Decoders are responsible for decrypting or extracting the real data

PAGE 37
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 37 12-09-2024 17:25:35

 COMPUTER SYSTEM ARCHITECTURE

Notes from the code that has been received. Encoder (that we will study later
in this lesson) and decoder are essential components of modern digital
systems such as calculators, mobile phones, fax machines, computers,
and other digital devices. Encoders are used at the input side to encode
information, while decoders are used at the output side to decode the
information. There are numerous applications, such as data de-multiplexing,
memory address decoding, seven segment display decoding, and binary
function generation.
The decoders below are called n to m line decoders, where m ≤ 2n. Their
goal is to use n variables to make 2n or fewer binary combinations. One
that takes in n input signals and sends out m output signals is called a
n × m decoder.

3 to 8 Decoder
A 3 × 8 decoder is a digital circuit that accepts three input lines and
generates eight output lines. A 3 × 8 decoder is shown in figure below:
‹ ‹Input Lines: The decoder is equipped with three input lines,
designated as x, y and z. These input lines correspond to a binary
code, where each line can be either 0 or 1. The combination of
inputs determines which output line will be activated.
‹ ‹Output Lines: The decoder is equipped with eight output lines F0
to F7. Each output line represents a distinct binary combination of
the input lines. For instance, when the input lines are set to 000
(x = 0, y = 0, z = 0), the output line F0 will be active. If the input
lines are 001 (with x = 0, y = 0, z = 1), the output line F1 will
be enabled, and so on.
‹ ‹A 3 × 8 decoder offers a handy method for converting a three-bit
binary code into one of eight potential output states. This makes
it a versatile and indispensable element in the design of digital
circuits.

38 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 38 12-09-2024 17:25:35

 Digital Components

Notes

Figure 2.5: 3 to 8 Decoder

Enable Input
An enable input in a decoder is a signal that controls whether the decoder
will work or not. The decoder works when the enable input 1 and it
turns off when enable is 0. Below are two states of decoder based on
enable input.
Active State: The decoder looks at its input lines when the enable input is
active. It turns on one of its many output lines based on the binary code
on the input lines. In a 3-to-8 decoder with 3 input lines, for example,
one of the 8 outputs will be turned on depending on how the 3 input
lines are combined.
Inactive State: If enable input is not active, the decoder does not respond
to the signals sent to it and all output lines are set to an inactive state.
The enable input is very important in situations where more than one
decoder is needed because it lets you choose which decoder to use at any
given time. For Example, in a memory system, the enable input can be
used to choose which memory chip is accessed. This way, read or write
commands will only work on the chosen memory. The Figure 2.2 shows
updated truth table and decoder logic circuit.

PAGE 39
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 39 12-09-2024 17:25:35

 COMPUTER SYSTEM ARCHITECTURE

Notes

Figure 2.6: 3 × 8 Decoder (with Enable input)

NAND gate decoder

Decoder can be constructed with NAND gate instead of AND gate. Such
decoder turns binary input signals into a certain output by using NAND
gates. There are two input lines and four output lines in a 2 × 4 decoder.
There are many possible combinations of input signals, and each output
line shows one of them. However, the outputs are active-low, which
means that the chosen output is 0. The primary benefits of using NAND
gates to construct decoders are their universality, cost-effectiveness, and
simplicity in digital circuit design.

Figure 2.7: 2 × 4 Decoder (with NAND Gate)

40 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 40 12-09-2024 17:25:36

 Digital Components

Notes
2.4.1 Decoder Expansion
Decoder expansion is a technique used to create larger decoders from
smaller ones to handle a greater number of input lines than a single
smaller decoder can manage. This approach is particularly useful when
a digital system requires more output lines than what is provided by the
available decoder i.e. the scenario wherein you need a bigger decoder
but only small size decoder is available. The basic idea is to use multi-
ple smaller decoders in combination, controlled by additional inputs, to
expand the number of possible outputs. This is often achieved by using
the higher-order bits to enable one of several smaller decoders.
Expanding a 2-to-4 decoder to create a 3-to-8 decoder involves using
additional logic to combine multiple 2-to-4 decoders in a way that can
handle three input lines and produce eight unique outputs. By using
the higher-order bit A2 to control the enable inputs of two 2-to-4
decoders, you can effectively create a 3-to-8 decoder. This expanded
decoder can handle three input lines and produce eight unique outputs,
thus increasing the decoding capacity without the need for a single,
larger decoder chip.
Figure 2.5 below illustrates how decoders with enable inputs can be
connected to create a larger decoder. In this example, two 2-to-4 line
decoders are combined to form a 3-to-8 line decoder:
‹ ‹The two least significant bits (A1 and A0) are connected to both
decoders.
‹ ‹The most significant bit (A2) is connected to the enable input of
one decoder.
‹ ‹The complement of the most significant bit (A2) is connected to
the enable input of the other decoder.
‹ ‹When A2 is 0, the upper decoder is enabled while the lower decoder
is disabled, producing outputs corresponding to minterms D 0
through D3.
‹ ‹When A 2 is 1, the upper decoder is disabled while the lower
decoder is enabled, producing outputs corresponding to minterms
D4 through D7.

PAGE 41
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 41 12-09-2024 17:25:36

 COMPUTER SYSTEM ARCHITECTURE

Notes

Figure 2.8: 3 × 8 Decoder Using 2 × 4 Decoder (Ref 1)

2.5 Encoder
An encoder is a digital circuit that takes in a signal, usually in the form
of binary data, and turns it into an output signal that has been coded. In
a way, it does the opposite of what a decoder does. Digital communi-
cation systems, data transmission, and different kinds of digital sensors
all use encoders all the time. Most encoders have 2n or less input lines
and n output lines. The number of input lines shows how many ways the
input can be put in. The number of output lines shows how the output
was encoded.
Below is example of a 8-to-3 encoder, which means it has 8 input lines
and 3 output lines. This is an octal to binary encoder, as you can see
each row has one specific octal number set , the 3 bit output depicts
the binary value of that octal number. The truth table for this encoder
would look like this:

42 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 42 12-09-2024 17:25:36

 Digital Components

Notes

Figure 2.9: 8 to 3 Encoder

2.6 Multiplexer
A multiplexer, abbreviated as “mux,” is a combinational digital circuit.
It can select one of several input signals and direct it to a single output
line. It is frequently employed in digital systems for the purpose of data
routing, signal switching, and selection.
‹ ‹Inputs: A multiplexer is equipped with multiple data input lines
and control input lines that determine the data input that is selected.
‹ ‹Selection Lines: The control inputs, which are frequently referred
to as select lines or address lines, are responsible for determining
which input line is directed to the output. The multiplexer’s capacity
to handle a certain number of input lines is contingent upon the
number of select lines.
‹ ‹Output: The output line is then directed to the selected input.
The symbol “MUX” is frequently used to represent a multiplexer, which
is followed by the number of input lines and the number of select lines.
For example, “4 × 1 MUX” represents a multiplexer with 4 input lines
and 1 select line.
The relationship between the input signals, the select lines, and the
output is defined by the truth table of a multiplexer. For instance, for
a 4 × 2 multiplexer with two select lines, the truth table is shown in
Figure 2.10.

PAGE 43
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 43 12-09-2024 17:25:36

 COMPUTER SYSTEM ARCHITECTURE

Notes

Figure 2.10: 4 × 1 Multiplexer

IN-TEXT QUESTIONS
1. Which device converts 2n inputs into an n-bit code?
2. What device converts binary information into a maximum of
2n outputs?
3. What device selects one input from multiple inputs based on
select lines?

2.7 Memory Units

The storage unit’s capacity to store and retain data is referred to as the
memory unit. Bytes are used to quantify the storage capacity. Bit (Binary
Digit) denotes the passive or active state of a component within an elec-
tric circuit, symbolizing either a logical 0 or 1. A nibble is a collection
of four bits. A byte is composed of eight bits. It is the smallest unit that
can be used to represent a character or data item. A word in computer
programming is a fixed number of bits that are treated as a single unit.
Word remains constant for each individual machine, even though it varies
across computers. The word-size or word length of a computer word can

44 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 44 12-09-2024 17:25:36

 Digital Components

vary from 8 bits to 96 bits. There are various types of memories in a Notes
computer as shown in Figure 2.11.

Figure 2.11: Classification of Memory

RAM (Random Access Memory): RAM is a type of volatile memory
that enables the simultaneous reading and writing of data. It is frequently
employed as the primary memory in digital devices and computers. In
RAM, data and program instructions that are being used by the CPU are
stored. It enables the Central Processing Unit (CPU) to rapidly read and
write data by providing rapid access to data. RAM is volatile, meaning
that its contents are lost when power is removed from the system. Thus
it needs continuous power for retaining data. SRAM (Static RAM) and
DRAM (Dynamic RAM) are two distinct types of RAM, each with its
own unique characteristics in terms of power consumption, cost, and
speed. Below is the block diagram of RAM.

Figure 2.12: RAM (Block Diagram)

PAGE 45
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 45 12-09-2024 17:25:36

 COMPUTER SYSTEM ARCHITECTURE

Notes The memory unit is organized into 2k words, with each word consisting
of n bits. The address lines are used to select one of these 2k words.
Data input and output lines are used for writing and reading n bits to
and from the memory unit, respectively. The above figure has following
components:
Address Lines (k address lines): These lines are used to select a specific
memory location. The number of address lines determines the addressable
memory space. With k address lines, the memory can address 2k unique
locations (words). For example 3 address lines will have 23 = 8 unique
memory addresses.
Data Input Lines (n data input lines): These lines are used to input
data into the memory. The number of data input lines corresponds to the
number of bits in each word that the memory unit can store.
Data Output Lines (n data output lines): These lines are used to output
data from the memory. The number of data output lines is the same as
the number of data input lines, allowing the same number of bits to be
read from the memory.
Control Lines: Read Line control signal tells the memory unit to read
data from the selected memory location and send it out via the data out-
put lines. Write Line control signal tells the memory unit to write data
present on the data input lines to the selected memory location.
Read Operation: When the read control line is activated, the memory
unit retrieves the data from the addressed location and places it on the
data output lines.
Write Operation: When the write control line is activated, the data
present on the data input lines is written to the addressed location.
ROM (Read-Only Memory): ROM is a type of non-volatile memory that
stores data and instructions that are permanently written in the memory
(during manufacturing). It is used to store firmware and essential system
instructions that do not change over time. It retains its contents even
when power is removed from the system, making it ideal for storing
critical system software and firmware. Unlike RAM, ROM is typically
read-only, meaning that its contents cannot be easily modified or updated
after manufacturing. There are various types of ROM, including Mask
ROM, which is programmed during manufacturing, and Programmable
ROM (PROM), which can be programmed by the user after manufacturing.
46 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 46 12-09-2024 17:25:36

 Digital Components

Notes

Figure 2.13: Block Diagram of ROM

PROM (Programmable Read-Only Memory): PROM is a type of

non-volatile memory that can be programmed by the user after manufac-
turing. It allows for the storage of data and instructions that do not change
frequently. It retains its programmed contents just like ROM. However,
unlike ROM, PROM can be programmed or written to by the user using
specialized programming equipment. PROM is typically programmed only
once, after which its contents become permanent and cannot be changed.
PROM is used in various applications where permanent but infrequently
changing data or instructions are required, such as firmware updates and
boot code storage.
EPROM (Erasable Programmable Read-Only Memory): EPROM is
a type of non-volatile memory that can be both programmed and erased
multiple times using ultraviolet light. It also retains its programmed
contents even when power is removed. However, it can be erased and
reprogrammed multiple times using ultraviolet light exposure to remove
the stored data. EPROM chips typically have a transparent window on
top through which ultraviolet light can penetrate to erase the stored data.
EPROM is used in applications where occasional updates or reprogram-
ming of firmware or data are required, such as in embedded systems,
microcontrollers, and early generations of BIOS chips.
EEPROM (Electrically Erasable Programmable Read-Only Memory):
EEPROM is a type of ROM that allows users to modify its contents by
applying a voltage higher than the normal level, which erases and repro-
grams the memory. EEPROMs have the advantage over EPROM chips
in that they can be modified while still inside the computer, without the
need for removal. The lifetime of an EEPROM is a crucial factor in its
design, as it can be reprogrammed multiple times while the computer is
operational. Flash memory is a distinct type of EEPROM that is commonly
used in personal computers to erase and reprogram data by adjusting
the voltage. The data stored in the Dynamic Random Access Memory

PAGE 47
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 47 12-09-2024 17:25:36

 COMPUTER SYSTEM ARCHITECTURE

Notes (DRAM) will be erased when the power supply is disconnected, whereas
the data stored in the Electrically Erasable Programmable Read-Only
Memory (EEPROM) will remain intact even when the power is turned
off. Furthermore, EEPROM has the capability to delete previously stored
data and then rewrite it.
In nutshell RAM provides volatile storage for actively used data, while
ROM offer non-volatile storage for firmware, system instructions, and
infrequently changing data. Each type of memory serves specific purposes
and has distinct characteristics regarding programmability, volatility, and
data retention.

IN-TEXT QUESTIONS
4. What type of memory retains data even when power is turned
off?
5. What type of memory is volatile and used for temporary storage?

2.8 Summary
This chapter provides a thorough insight of various digital components
that are essential to understand computer system architecture. The chapter
explains the designing and concept of circuits like binary adder, binary
subtractor, binary incrementer. It also focuses on working of decoder,
encoder and multiplexer, along with their usage in real life. The chapter
ends with a detailed discussion of memory units. This chapter will help
the student to gain a deeper understanding these components.

2.9 Answers to In-Text Questions

1. Encoder
2. Decoder
3. Multiplexer
4. ROM
5. RAM

48 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 48 12-09-2024 17:25:36

 Digital Components

Notes
2.10 Self-Assessment Questions
1. What is the function of a multiplexer (MUX)?
2. Explain the working of a 4-to-1 multiplexer with a truth table.
3. What is a decoder, and how is it used in digital circuits?
4. What is the function of an encoder in digital systems?
5. Describe the role of a decoder in digital circuits.
6. What is the difference between RAM and ROM?
7. Explain the use of ROM in digital systems.
8. How does volatile memory differ from non-volatile memory?

2.11 References
u Computer System Architecture by M. Morris Mano, Third edition,
1993, Prentice Hall of India.
u Computer System Architecture by M. Morris Mano, Third edition,
1993, Pearson Education.

2.12 Suggested Readings

u Sima, D., & Kacsuk, P. (1997). Advanced computer architectures.
Addison-Wesley Longman Publishing Co., Inc.
u Null, L. (2023). Essentials of Computer Organization and Architecture.
Jones & Bartlett Learning.
u Hennessy, J. L., & Patterson, D. A. (2017). Computer architecture:
a quantitative approach. Morgan Kaufmann.

PAGE 49
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 49 12-09-2024 17:25:36

 L E S S O N

3
Data Representation
Asha Yadav
Assistant Professor
Department of Computer Science
School of Open Learning
University of Delhi
Email-Id: [email protected]

STRUCTURE
3.1 Learning Objectives
3.2 Data Representation
3.3 Number Systems
3.4 Conversion of Radix ‘r’
3.5 Binary Coded Decimal
3.6 Compliments
3.7 Fixed Point Representation
3.8 Integer (Sign and Magnitude) Representation
3.9 Addition and Subtraction of Signed and Unsigned Numbers
3.10 Overflow Detection
3.11 Summary
3.12 Answers to In-Text Questions
3.13 Self-Assessment Questions
3.14 References
3.15 Suggested Readings

3.1 Learning Objectives

After studying this chapter, you will be able to:
‹ ‹Represent data in various formats like binary, octal, hexadecimal.
‹ ‹Convert different number systems, such as binary, decimal, and hexadecimal.
‹ ‹Understand the concepts of fixed-point representation for representing real numbers
in binary format.
‹ ‹Perform addition and subtraction of signed and unsigned integers.
50 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 50 12-09-2024 17:25:36

 Data Representation

Notes
3.2 Data Representation
Data representation is a critical aspect of computer systems architecture,
as it refers to the representation of various types of data (like text, images,
audio, and video) in a manner that enables computers to store, perform
operation and interpret them. Computers employ binary numbers, or bits,
which are strings of 0s and 1s to store data internally, also formats and
encoding methods are employed to display various types of data.

3.3 Number Systems

The number system is a fundamental concept that forms the basis for
representing, storing, and manipulating data in computer systems. Com-
puters employ various number systems for the purpose of processing and
storing data. The common number systems are:
Decimal (Base 10): Utilises the numerical symbols 0-9. This is the con-
ventional system for representing numbers in a way that can be easily
understood by humans.
Binary (Base 2): It is a numerical system that exclusively uses the digits
0 and 1. This is the fundamental system for computers as they function
based on binary states, which are represented by “on (1)” and “off (0)”.
Octal (Base 8): It is a numerical system that uses digits from 0 to 7.
Octal numbers are occasionally employed as a concise representation of
binary numbers, as each octal digit corresponds to three binary digits.
Hexadecimal (Base 16): It utilises the digits 0-9 and the letters A-F.
Hexadecimal is frequently employed in programming and computer engi-
neering due to its ability to represent four binary digits with a single
hexadecimal digit.
The study of number systems is valuable for computing students since the
computer sector utilizes many other number systems rather than well-known
decimal system. For representation of number system every numerical
value can be expressed by arranging symbols in ordered positions. For
example, in the decimal number system, each position to the left of the
decimal point represents a different power of ten, starting with the units
(ones) position and progressing to tens, hundreds, thousands, and so on.
In other words, each location corresponds to a distinct exponent of the
PAGE 51
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 51 12-09-2024 17:25:36

 COMPUTER SYSTEM ARCHITECTURE

Notes base 10. For instance, the decimal number 2234 (or (2234)10) can be
expanded in the following manner:

3.3.1 Binary Numbers

The ideas of positional number systems that we applied to the decimal
number system can also be applied to the binary number system. Nev-
ertheless, the binary number system has a base 2, meaning that each
location in a binary number corresponds to an increasing power of 2.
The binary number’s positions are weighted in a sequential manner from
right to left, with weights of 1, 2, 4, 8, 16, 32, 64, and so on. Below are
some of the initial successive exponents of 2:

Binary to Decimal Conversion

Converting a binary number to decimal requires multiplication each digit
of the binary number by 2 raised to the power of its position (starting
from the rightmost digit with position 0), and then sum up these values.
1. Write down the binary number you want to convert to decimal.
2. Starting from the rightmost digit, assign positions to each digit. The
rightmost digit has a position of 0, the next digit to the left has a
position of 1, and so on.
3. Multiply each digit of the binary number by 2 raised to the power
of its position (like first position will be multiplied by 20 = 1).
4. Sum up all the resulting numbers from step 3.

52 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 52 12-09-2024 17:25:36

 Data Representation

For example: Notes

Binary to Octal Conversion

Converting from binary to octal involves grouping the binary digits into
sets of three, and then converting each group into its octal equivalent.
1. Start from the rightmost digit of the binary number and group the
digits into sets of three. If the leftmost group has less than three
digits, you can pad it with zeros on left.
2. Once you’ve grouped the digits, convert each group into its octal
equivalent. You can use the following conversion table:
Binary (3-bit) Octal
000 0
001 1
010 2
011 3
100 4
101 5
110 6
111 7

PAGE 53
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 53 12-09-2024 17:25:37

 COMPUTER SYSTEM ARCHITECTURE

Notes 3. W
 rite down the octal digits obtained from each group in order from
left to right to get the final octal number.
For example covert (101101110)2 to octal
1. Group the binary digits:
‹ ‹101 101 110
2. Convert each group to octal:
‹ ‹101 (binary) = 5 (octal)
‹ ‹101 (binary) = 5 (octal)
‹ ‹110 (binary) = 6 (octal)
3. Combine the octal digits:
‹ ‹Octal number: 556
So, the octal equivalent of the binary number 101101110 is 556.

Binary to Hexadecimal Conversion

Converting binary to hexadecimal involves grouping the binary digits
into sets of four, and then converting each group into its hexadecimal
equivalent.
1. Start from the rightmost digit of the binary number and group the
digits into sets of four. If the leftmost group has less than four
digits, you can pad it with zeros on left.
2. Once you’ve grouped the digits, convert each group into its
hexadecimal equivalent. You can use the following conversion table:

Binary (4-bit) Hexadecimal

0000 0
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7
1000 8

54 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 54 12-09-2024 17:25:37

 Data Representation

Binary (4-bit) Hexadecimal Notes

1001 9
1010 A
1011 B
1100 C
1101 D
1110 E
1111 F

3. Write down the hexadecimal digits obtained from each group in

order from left to right to get the final hexadecimal number.
For example convert (101101110)2 to hexadecimal
1. Group the binary digits:
‹ ‹0010 1101 1100
2. Convert each group to hexadecimal:
‹ ‹0010 (binary) = 2 (hexadecimal)
‹ ‹1101 (binary) = D (hexadecimal)
‹ ‹1100 (binary) = C (hexadecimal)
3. Combine the hexadecimal digits:
‹ ‹Hexadecimal number: 2DC
So, the hexadecimal equivalent of the binary number 101101110 is 2DC.

3.3.2 Decimal Numbers

Decimal numbers are numerical values represented in the base-10 numeral
system, which is the commonly used technique for expressing both whole
and fractional numbers in everyday calculations and mathematics. The
decimal system employs 10 symbols from 0-9 to represent numbers. The
position of each digit in a decimal integer represents its place value,
which is an exponent of 10. The digit on the far right indicates the units,
the digit to its left represents the tens, the following digit represents the
hundreds, and so on.

PAGE 55
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 55 12-09-2024 17:25:37

 COMPUTER SYSTEM ARCHITECTURE

Notes Decimal Conversions

Converting a decimal number to binary, octal, or hexadecimal involves
dividing the number by the base (2 for binary, 8 for octal, 16 for
hexadecimal) and noting the remainders at each step until the quotient
becomes zero. Then, the remainders are read in reverse order to get the
converted number.
Decimal to Binary
1. Divide the decimal number by 2.
2. Note the remainder (either 0 or 1).
3. Repeat steps 1 and 2 with the quotient obtained from the division
until the quotient becomes zero.
4. Write down the remainders obtained in reverse order to get the
binary equivalent.

Reading remainders from bottom to top: 10111011

Decimal to Octal
1. Divide the decimal number by 8.
2. Note the remainder.
3. Repeat steps 1 and 2 with the quotient obtained from the division
until the quotient becomes zero.
4. Write down the remainders obtained in reverse order to get the
octal equivalent.

56 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 56 12-09-2024 17:25:37

 Data Representation

Notes

Reading remainders from bottom to top: 273

Decimal to Hexadecimal
1. Divide the decimal number by 16.
2. Note the remainder. If the remainder is 10, write A; if it’s 11, write
B; and so on up to F for 15.
3. Repeat steps 1 and 2 with the quotient obtained from the division
until the quotient becomes zero.
4. Write down the remainders obtained in reverse order to get the
hexadecimal equivalent.

Converting remainder 11 to hexadecimal gives ‘B’.

Reading remainders from bottom to top: BB

3.3.3 Octal Number System

The idea of positional number systems that we used for the decimal and
binary number systems can also be applied to the octal number system.
The octal number system has a base of eight, meaning that each point
in an octal number reflects a power of eight that increases sequentially.
The positions of the octal number are weighted in a sequential manner
from right to left, with weights of 1, 8, 64, 512, and so on. Below is a
list of the initial successive exponents of 8:

80 = 1 81 = 8 82 = 64 83 = 512 84 = 4096 85 = 32768

PAGE 57
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 57 12-09-2024 17:25:37

 COMPUTER SYSTEM ARCHITECTURE

Notes Octal to Binary

1. Convert each octal digit to its 3-bit binary equivalent referring table
given in section 3.3.1.
2. Combine the binary equivalents obtained for each digit to get the
binary number.
� 3 8 = 0112
� 48 = 1002
� 58 = 1012
So, 3458 = 0111001012

Octal to Decimal
1. Multiply each digit of the octal number by 8n where n, is the
position of the digit (starting from 0 for the rightmost digit).
2. Add up the results from step 1 to get the decimal equivalent.
� 3 × 82 = 3 × 64 = 192
� 4 × 81 = 4 × 8 = 32
� 5 × 80 = 5 × 1 = 5
Adding result together: 192 + 32 + 5 = 229
So, 3458 = 22910

Octal to Hexadecimal
1. Convert the octal number to binary.
2. Group the binary digits into sets of four.
3. Convert each group of binary digits to its hexadecimal equivalent
using table given in section 3.3.1.

Example:
Convert (725)8 to Hexadecimal
(725)8 = (111010101)2
Grouping into sets of four: 0001 1101 0101
(Add leading zeros to make a complete set of four bits 0001 1101 0101)

58 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 58 12-09-2024 17:25:37

 Data Representation

4. Each set of four binary digits can be converted to one hexadecimal Notes
digit.
‹ ‹0001→1

‹ ‹1101→D

‹ ‹0101→5

Hence (725)8→(1D5)16

3.3.4 Hexadecimal Number

Hexadecimal (often abbreviated as “hex”) is a base-16 numeric system.
Hexadecimal, in contrast to the decimal system, employs sixteen unique
symbols to represent values, as opposed to the ten symbols (0-9) used
in the decimal system. The following are the symbols:
0 1 2 3 4 5 6 7 8 9AB C D E F
Where:
A represents 10
B represents 11
C represents 12
D represents 13
E represents 14
F represents 15
Hexadecimal notation follows a positional system where each digit’s
place corresponds to a power of 16, like how the decimal system works
with powers of 10.

Hexadecimal to Binary Conversion

To convert a hexadecimal number to binary, you can simply convert each
hexadecimal digit to its 4-bit binary equivalent.
1. Write down the hexadecimal number.
2. Replace each hexadecimal digit with its 4-bit binary equivalent.
3. Combine the binary equivalents obtained for each digit to get the
binary representation.

PAGE 59
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 59 12-09-2024 17:25:37

 COMPUTER SYSTEM ARCHITECTURE

Notes Example:
convert (3F8)16
‹ ‹3 -> 0011
‹ ‹F -> 1111
‹ ‹8 -> 1000
⇒ (3F8)16 -> (0011 1111 1000)2

Hexadecimal to Decimal Conversion

To convert a hexadecimal number to decimal, multiply each digit by its
corresponding power of 16, starting from the rightmost digit.
1. Write down the hexadecimal number.
2. Assign each digit a position value, starting from 0 for the rightmost
digit.
3. Multiply each digit by 16n where n is its position value.
4. Add up the results to get the decimal equivalent.
Example:
Convert (2B)16 to decimal
‹ ‹2 × 161 = 2 × 16 = 32
‹ ‹B × 160 = 11 × 1 = 11
Add up the results: 32 + 11 = 43, so the hexadecimal number 2B is
equivalent to the decimal number 43.

Hexadecimal to Octal Conversion

To convert a hexadecimal number to octal, you can first convert it to
binary and then convert the binary number to octal.
1. Convert the hexadecimal number to binary.
2. Group the binary digits into sets of three, starting from the right.
3. Convert each group of three binary digits to its octal equivalent.
4. Combine the octal equivalents obtained for each group to get the
octal representation.

60 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 60 12-09-2024 17:25:37

 Data Representation

Example: Notes
1. Convert (A5)16 to octal
Step 1:
� A -> 1010
� 5 -> 0101
⇒ (A5)16 -> 10100101
Step 2:
010 100 101 (Group in 3)
Writing binary equivalent
⇒ (A5)16 = (245)8

3.4 Conversion of Radix ‘r’

To convert a number from decimal to another base (radix r), or vice
versa, you can use the following methods:
Decimal to Radix r Conversion:
To convert a decimal number to a different base r (where r is the base),
you repeatedly divide the decimal number by r and note the remainders
at each step until the quotient becomes zero. Then, the remainders are
read in reverse order to get the converted number.
Decimal to Base-5 Conversion:
1. Divide 29 by 5: 29 ÷ 5 = 5 with remainder 4. (Quotient: 5,
Remainder: 4)
2. Divide 5 by 5: 5 ÷ 5 = 1 with remainder 0. (Quotient: 1,
Remainder: 0)
3. Divide 1 by 5: 1 ÷ 5 = 0 with remainder 1. (Quotient: 0,
Remainder: 1)
Reading the remainders from bottom to top: 104, so decimal 29 is equal
to base-5 104.
Radix r to Decimal Conversion:
To convert a number from another base r to decimal, you multiply each
digit of the number by r raised to the power of its position (starting from
0 for the rightmost digit), and then sum up these values.
PAGE 61
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 61 12-09-2024 17:25:37

 COMPUTER SYSTEM ARCHITECTURE

Notes Base-5 to Decimal Conversion:

Let’s convert base-5 number 104 back to decimal:
1 × 52 + 0 × 51 + 4 × 50 = 1 × 25 + 0 × 5 + 4 × 1 = 25 + 0 + 4 = 29
So, base-5 number 104 is equal to decimal 29.

IN-TEXT QUESTIONS
1. Convert the decimal number 25 to binary.
2. Convert the binary number 11010 to decimal.
3. Convert the octal number 157 to decimal.
4. Convert the hexadecimal number 3F to decimal.

3.5 Binary Coded Decimal

Binary Coded Decimal (BCD) is a binary encoding scheme used to rep-
resent decimal numbers. In BCD, each decimal digit (0-9) is represented
by its corresponding 4-bit binary code. The main feature of BCD is that
each digit is encoded independently of the others, allowing for precise
decimal representation and arithmetic operations. BCD allows for arith-
metic operations (addition, subtraction, multiplication, and division) to
be performed directly on decimal numbers without conversion to binary.
Arithmetic operations in BCD follow rules like those used for decimal
arithmetic. Each decimal digit (0-9) is represented by its 4-bit binary
equivalent.
For example:
‹ ‹0 is represented as 0000 in BCD.
‹ ‹1 is represented as 0001 in BCD.
‹ ‹2 is represented as 0010 in BCD.
For multidigit representation:
‹ ‹45 is represented as 0100 0101 in BCD.
‹ ‹123 is represented as 0001 0010 0011 in BCD.
‹ ‹789 is represented as 0111 1000 1001 in BCD.

62 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 62 12-09-2024 17:25:37

 Data Representation

Let’s represent the decimal number 357 in BCD: Notes

1. Convert each decimal digit to its 4-bit binary equivalent:
‹ ‹3 -> 0011
‹ ‹5 -> 0101
‹ ‹7 -> 0111
2. Combine the binary equivalents:
‹ ‹BCD for 357: 0011 0101 0111
So, the decimal number 357 is represented as 001101010111 in BCD.

Alphanumeric Representation
Alphanumeric representation is the use of a combination of letters and
numbers to represent data. This system comprises:
‹ ‹Alphabetic characters refer to both uppercase (A-Z) and lowercase
(a-z) letters.
‹ ‹Numeric characters refer to the digits 0-9.
‹ ‹Non-alphanumeric characters: Examples of symbols include @, #,
$, %, &, *, and so on.
Alphanumeric characters are essential for the storage and manipulation
of textual data in computer systems. Names, addresses, and other textual
data are encoded using alphanumeric characters. Human-Computer Inter-
action (HCI) involves the use of text-based interfaces that allow users to
interact with computer systems by providing and receiving information
in a format that is easily understandable to humans. Computer systems
utilise representation methods to store and process information. Alpha-
numeric characters are encoded using different encoding schemes. The
most prevalent ones are:
ASCII stands for American Standard Code for Information Interchange,
in this each character is represented by a distinct binary code consisting
of either 7 or 8 bits. Standard ASCII employs a 7-bit encoding scheme,
enabling the representation of 128 distinct characters. Extended ASCII
employs 8 bits, enabling the representation of 256 distinct characters.
Unicode is a standardised character encoding system that assigns a unique
number to each character in various writing systems. It is an extensive

PAGE 63
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 63 12-09-2024 17:25:37

 COMPUTER SYSTEM ARCHITECTURE

Notes encoding scheme that accommodates a wide array of characters from

diverse languages and symbol sets. Employs variable-length encoding,
such as UTF-8 or UTF-16 (where UTF is Unicode Transformation Format),
to depict characters.

3.6 Compliments
Complements are used in computers to make operations like subtraction
easier and for the logical manipulations. Radix r stands for the base of
the number system. There are two kinds of complements for each radix-r
system:
‹ ‹(r-1)’s complement
‹ ‹r’s complement

(r−1)’s Complement
The (r-1) complement of a number is a method used to represent negative
numbers in a specific radix (base) system. It is beneficial for carrying out
arithmetic computations, particularly subtraction. The (r-1) complement
of a number N in each radix r is obtained by subtracting each digit of
N from (r-1).
Binary System (Base 2): For a binary number (base 2), the r−1’s com-
plement is known as the 1’s complement.
Number: 1010
Radix: 2
(r-1) Complement Calculation:
For base 2, r – 1 = 1.
‹ ‹Subtract each digit from 1:
‹ ‹1 – 1 = 0
‹ ‹1 – 0 = 1
‹ ‹1 – 1 = 0
‹ ‹1 – 0 = 1
(1’s complement of 1010): 0101
It can be obtained by inverting each digit as well (i.e., 0 → 1, 1 → 0).

64 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 64 12-09-2024 17:25:37

 Data Representation

Decimal System (Base 10): For a decimal number (base 10), the r−1’s Notes
complement is known as the 9’s complement.
Number: 256
Radix: 10
(r-1) Complement Calculation:
For base 10, r – 1 = 9.
‹ ‹Subtract each digit from 9:
‹ ‹9 – 2 = 7
‹ ‹9 – 5 = 4
‹ ‹9 – 6 = 3
(9’s complement of 256): 743
r’s Complement: The r’s complement of a number N, given a radix r,
is obtained by calculating the (r-1) complement and then adding 1 to
the least significant digit. Example of binary and decimal calculation is
given below:
Binary
Number: 1010
Radix: 2
(r-1) Complement Calculation:
For base 2, r – 1 = 1.
� Subtract each digit from 1:
‹ ‹1 – 1 = 0
‹ ‹1 – 0 = 1
‹ ‹1 – 1 = 0
‹ ‹1 – 0 = 1
(1’s complement of 1010): 0101
Add 1 to the Least Significant Digit:
‹ ‹0101 + 1 = 0110
(2’s complement of 1010): 0110

PAGE 65
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 65 12-09-2024 17:25:37

 COMPUTER SYSTEM ARCHITECTURE

Notes Decimal
For base 10, r – 1 = 9.
� Subtract each digit from 9:
‹ ‹9 – 2 = 7
‹ ‹9 – 5 = 4
‹ ‹9 – 6 = 3
(9’s complement of 256): 743
Add 1 to the Least Significant Digit:
‹ ‹743 + 1 = 744
(10’s complement of 256): 744
Unsigned number subtraction
Subtracting unsigned numbers involves the direct subtraction of one non-neg-
ative number from another. However, in computer systems, this process can
be streamlined by using complement systems, such as the r’s complement,
to simplify the operation, particularly when working with binary numbers.
This method involves taking the complement of the subtrahend and adding
it to the minuend. Subtraction using complement is explained below:
Subtraction using r’s Compliment
Example 1: subtract 0011 (3 in decimal) from 1010 (10 in decimal).
Steps:
1. Find the 2’s complement of the subtrahend (as explained above).
0011 -> 1101
2. Add the complement to the minuend.
(1010 + 1101) -> 10111
3. If there’s an overflow, discard it.
Discard 1 from leftmost (overflow)
Answer: 0111 i.e. 7
Example 2: subtract 256 from 734
Steps:
1. Find the 10’s complement of the subtrahend.
256 -> 744

66 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 66 12-09-2024 17:25:37

 Data Representation

2. Add the complement to the minuend. Notes

(734 + 744) -> 1478
3. If there’s an overflow, discard it.
Discard 1 from leftmost (overflow)
Answer: 478
Subtraction using (r-1)’s Compliment
Example 1: subtract 0011 (3 in decimal) from 1010 (10 in decimal).
Steps:
1. Find the 1’s complement of the subtrahend.
0011 -> 1100
2. Add the complement to the minuend.
(1010 + 1100) -> 10110
3. If there is a carry, add it back to the result.
0110 + 1 -> 0111
Answer: 0111 i.e. 7
Example 2: 734 − 256
Steps:
1. Find the 9’s complement of the subtrahend.
256 -> 743
2. Add the complement to the minuend.
(734 + 743) -> 1477
3. If there is a carry, add it back to the result.
477 + 1 -> 478
Answer: 478

3.7 Fixed Point Representation

Fixed-point representation in computer architecture refers to a method of
representing and performing arithmetic operations on numerical values
with a fixed number of digits after (and sometimes before) the decimal
point. Here are the key aspects of fixed-point representation:

PAGE 67
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 67 12-09-2024 17:25:37

 COMPUTER SYSTEM ARCHITECTURE

Notes

Format:
In fixed-point representation, a specific number of bits are allocated for
the integer part and the fractional part of a number. For example, in an
8-bit fixed-point format with 4 bits allocated for the integer part and 4
bits for the fractional part, the format might look like: IIII. FFFF.

Figure 3.1: Format of Fixed-point Arithmetic

Range and Precision:

The range and precision of fixed-point numbers depend on the number
of bits allocated to the integer and fractional parts. A larger number of
bits for the fractional part increases precision but reduces the range of
representable values, and vice versa.

68 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 68 12-09-2024 17:25:37

 Data Representation

Applications: Notes
Fixed-point representation is often used in applications where hardware
efficiency is crucial, such as in embedded systems and digital signal
processing (DSP). It allows for efficient implementation of arithmetic
operations using simpler hardware and less computational resources
compared to floating-point representation.
Advantages:
Fixed-point representation offers deterministic behavior in arithmetic
operations, predictable performance, and reduced hardware complexity
compared to floating-point arithmetic, making it suitable for real-time
systems and applications where precision within a specific range is suf-
ficient.
Challenges:
The main challenge with fixed-point representation is selecting an
appropriate format (number of integer and fractional bits) that balances
between range and precision for a given application. Improper selection
can lead to overflow (values exceeding the representable range) or loss
of precision.
The magnitude of the signed binary numbers can be described using three
methods are as follows:

3.8 Integer (Sign and Magnitude) Representation

An integer can have positive or negative value, we represent positive
integer having 0 in the sign bit and rest of the bit represent the magni-
tude of the number. For example, +15 is represented as 01111 where 0
is sign bit and 1111 is the magnitude.
The representation of a negative integer is a little more tricky, in case of
negative integers the sign bit is 1 and the magnitude can be represented as
signed magnitude representation or signed 1’s compliment representation
or signed 2’s compliment representation let’s have a detailed understanding
of all of these with the help of example.
Let’s take two integers +15 and −15 and depict its representation

PAGE 69
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 69 12-09-2024 17:25:37

 COMPUTER SYSTEM ARCHITECTURE

Notes

Figure 3.2: Integers Signed Magnitude Representation

Hence as depicted in the Figure 3.2 above +15 has only one representa-
tion but −15 can have 3 representations

3.9 Addition and Subtraction of Signed and Unsigned

Numbers
Signed or unsigned numbers may be added. When we add two numbers,
like 8 and 5, the result is 13. This means that when we combine two
single-digit numbers, the outcome could also include a two-digit number.
This is true for binary system as well. The binary addition thumb rule is:

Examples (a–e) of unsigned binary addition are given in figure below:

70 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 70 12-09-2024 17:25:38

 Data Representation

Notes

The signed magnitude representation is helpful while doing ordinary

arithmetic operations but in case of computer arithmetic signed 2’s com-
pliment is used as it is easier to do calculations using 2’s compliment.

Addition
The rule for adding two integers using signed 2’s compliment repre-
sentation only requires only addition and compliment. For addition we
need to add two numbers (in their signed 2’s compliment representation)
including sign bit and in case we have a carry we need to discard it as
shown below in example (taken from Ref 1).

In above example the negative results are in 2’s compliment representation

to interpret their value we need to convert it back like (−7) represented
as 11111001 above in 2’s compliment form. Hence taking 2’s compliment
of 11111001 will give 00000111 which is +7 the difference. Similarly,
11101101(−19) comes out to be 00010011(+19). This conversion is required
to provide clear interpretation of the result (remember this conversion
gives magnitude in a better way sign of the number is still negative).
Subtraction
As we already know that subtraction can be converted to addition if
the sign of subtrahend is changed. Hence, subtraction can be done by
computing the 2’s compliment of subtrahend and adding it to minuend

PAGE 71
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 71 12-09-2024 17:25:38

 COMPUTER SYSTEM ARCHITECTURE

Notes (including the sign bit in both cases), the carry generated out of sign
bit is discarded.
Example: Subtract (1010)2 from (1111)2 using 2’s complement method.
2’s complement of (1010)2
(1010)2 is (0110)2
Add (0110)2 to (1111)2

Answer: 0101

IN-TEXT QUESTIONS
5. Add the binary numbers 1011 and 1101.
6. Find the 2’s complement of the binary number 01101.
7. Subtract the binary number 101 from 110 using 2’s complement.
8. Convert the decimal number 255 to hexadecimal.
9. Convert the hexadecimal number 2A to binary.
10. Represent the decimal number −45 in sign-magnitude form using
8 bits.

3.10 Overflow Detection

Simply expressed, overflow occurs when a result is obtained that is greater
than the maximum number that can be represented. Put differently, an
overflow is the outcome of adding two numbers with sign bits ‘0’ to get
a value with a sign bit ‘1’. For example: An 8 bit word can maximum
represent +127 decimal, 01111111 in binary. If we add, 120 + 10 -> 130;
120 -> 0111 1000
10 -> 0000 1010
---------------
1000 0010 -> in sign magnitude form, MSB (Most significant bit) ‘1’
means negative number while we expect +130
Since Max is +127, an overflow situation exists.
72 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 72 12-09-2024 17:25:38

 Data Representation

In an overflow case, an error has occurred and the programmer or user Notes
has to be informed that this has happened. The CPU hardware recognizes
this circumstance and sets the “OVERFLOW” status bit. If the user is
interested, they can examine the OVERFLOW status bit to identify this
problem and take the appropriate action regarding the data handling.

3.11 Summary
This chapter gives the insight of binary, octal, hexadecimal, decimal number,
conversion from one number system to another representation of complement,
signed representation of positive and negative number. It also explains the
subtraction of unsigned numbers, arithmetic addition and overflow concepts.

3.12 Answers to In-Text Questions

1. 25 (decimal) = 11001 (binary)
2. 11010 (binary) = 26 (decimal)
3. 157 (octal) = 182 + 581 + 7*80 = 111 (decimal).
4. 3F (hexadecimal) = 3161 + 15160 = 63 (decimal)
5. 1011 + 1101 = 11000.
6. 01101 → Invert bits: 10010 → Add 1: 10011.
7. 110 (binary) − 101 (binary):
‹ ‹Find 2’s complement of 101: 010 + 1 = 011.
‹ ‹Add to 110: 110 + 011 = 1001 (ignoring the overflow, result
is 001).
8. 255 (decimal) = FF (hexadecimal).
9. 2A (hexadecimal) = 0010 1010 (binary).
10. −45 (decimal) in 8-bit sign-magnitude: 1101 1010.

3.13 Self-Assessment Questions

1. What is a number system? Why do we need it.
2. What is r’s and (r-1)’s complement method? What is usage of
complement method.

PAGE 73
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 73 12-09-2024 17:25:38

 COMPUTER SYSTEM ARCHITECTURE

Notes 3. Convert the following binary numbers to decimal: 101110; 1110101;

and 110110100.
4. Convert the following decimal numbers to the bases indicated.
(a) 7562 to octal
(b) 1938 to hexadecimal
(c) 175 to binary
5. What is overflow and how it is detected?

3.14 References
u Computer System Architecture by M. Morris Mano, Third edition,
1993, Prentice Hall of India.
u Computer System Architecture by M. Morris Mano, Third edition,
1993, Pearson Education.

3.15 Suggested Readings

u John P Hayes “Computer Architecture and organization” McGraw
Hill.
u Dezso Sima,Terence Fountain and Peter Kacsuk “Advanced Computer
Architecture” Pearson Education.
u H&P3: Hennessy, J. L., and D. A. Patterson. Computer Architecture:
A Quantitative Approach, 3rd ed. San Mateo, CA: Morgan Kaufman,
2002. ISBN: 1558605967.

74 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 74 12-09-2024 17:25:38

 L E S S O N

4
Basic Computer
Organization and Design
Dr. Reema Thareja
Assistant Professor
Department of Computer Science
School of Open Learning
University of Delhi
Email-Id: [email protected]

STRUCTURE
4.1 Learning Objectives
4.2 Introduction
4.3 Key Terminology
4.4 Structure of an Instruction Code
4.5 Stored Program Organization
4.6 Addressing Modes
4.7 Computer Registers
4.8 The Common Bus
4.9 Computer Instructions
4.10 Instruction-Set Completeness
4.11 Instruction Cycle
4.12 Type of Instruction and Addressing
4.13 Input Output and Interrupt
4.14 Interrupt Cycle
4.15 Summary
4.16 Answers to In-Text Questions
4.17 Self-Assessment Questions
4.18 References
4.19 Suggested Readings

PAGE 75
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 75 12-09-2024 17:25:38

 COMPUTER SYSTEM ARCHITECTURE

Notes
4.1 Learning Objectives
After reading this chapter, you will understand the following concepts:
‹ ‹Difference between computer organization and its architecture.
‹ ‹Stored program organization.
‹ ‹Computer Instructions.
‹ ‹Interrupt Processing.

4.2 Introduction
The organization of a computer is defined by its internal registers, tim-
ing and control structure, and the set of instructions that it uses. It also
specifies the sequence of micro-operations it performs on data stored
in registers. But before going further let us understand the difference
between Computer Architecture and Computer Organization.

Computer Architecture VS Computer Organization

Computer Architecture Computer Organization

Computer Architecture caters to how Computer Organization looks into
hardware components are connected the structure and behaviour of a
to each other to form a computer computer system as visible to the
system. end-user.
Computer Architecture helps us to Computer Organization helps us
list the functionalities of a system. to understand how every unit
in the system is arranged and
interconnected.
While designing a computer system, Computer organization is done as
its architecture is considered first. per the architecture of the system.
Computer Architecture considers Computer Organization works with
high-level design issues. low-level design issues.
While studying a computer ’s Organization deals with physical
architecture, its instruction sets, components like Circuit design,
Addressing modes, Data types and Signals, Adders and Peripherals.
Cache optimization are considered.

76 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 76 12-09-2024 17:25:38

 Basic Computer Organization and Design

Notes
4.3 Key Terminology
Before delving into the details of Computer System Architecture, we need
to first understand the following terms.
Program: A program is a set of instructions that specify the operations,
operands and the sequence in which data has to be processed. They are
written using programming languages like C++, C, Python, etc. However,
a computer cannot execute programs directly because it understands
instructions written in binary language only (in the form of 0s and 1s).
Therefore, a computer first converts the high-level codes into binary
machine-executable codes and then performs the user-specified task.
Instruction Codes: An instruction code is a collection of bits that instruct
the computer to perform a particular task.
Operation Code (or Opcode): The Operation code of an instruction is
a collection of bits that specifies the operation that must be performed.
Operation can be addition, subtraction, shift, complement, etc. For exam-
ple, in the instruction ADD 457, ADD is the opcode.
Operand: An instruction also specifies the data or the operands on which
the operation will be performed. The operand may be a CPU registers
and/or a memory addresses.
IN-TEXT QUESTIONS
1. ________ is a set of instructions that specify the operations,
operands and the sequence in which data has to be processed.
2. Data on which the operation will be performed is also known
as ________.
3. ________ specifies the operation that needs to be performed.

4.4 Structure of an Instruction Code

In general, each instruction code is 16-bits long and consists of three parts.
The mode field defines how the location of the operand can be found
by the computer.
The operation code field or opcode specifies the operation to be per-
formed. The number of bits required for this field depends on the total
operations available on the computer.
PAGE 77
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 77 12-09-2024 17:25:38

 COMPUTER SYSTEM ARCHITECTURE

Notes The address field contains the operand’s address. It can either be a
memory location or a CPU register. The address field of the instruction
specifies whether the operand is direct, indirect or immediate.

4.5 Stored Program Organization

The operands are specified by indicating the registers and/or memory
locations in which they are stored. k bits are used to specify one of
the 2k registers (or memory locations) in which the data is present. The
simplest design is to have one processor register (called the accumulator)
and two fields in the instruction- one for the opcode and the other for
the operand as shown in Figure 4.1.

Figure 4.1: Program Instruction in Memory

4.6 Addressing Modes

We can specify one of the following operands in an instruction:
Direct operand is an operand that is either stored in the register or in
the memory location specified.
Indirect operand is an operand whose address is stored in the register
or in the memory location specified.
Immediate operand is an operand whose value is directly specified in
the instruction.
The difference between a direct and indirect instruction can be visualized
in Figure 4.2.
78 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 78 12-09-2024 17:25:38

 Basic Computer Organization and Design

Notes

Figure 4.2: Program Instruction in Memory

4.7 Computer Registers

Computer instructions are stored in consecutive memory locations and
are executed sequentially. Program Counter is a register which stores
the address of the next instruction to be executed. However, besides
this information, the computer also needs registers to store the data or
the address at which a memory operand is present in the memory. Then
registers are required to hold the input, output and temporary values.
Since our reference memory model has 4096 locations, it needs 12 bits
to store address. Any register that stores data will be of 16 bits. Given
below is a list of registers available along with their size and functionality.
Register Number Register Name Function
Symbol of Bits
DR 16 Data register Holds memory operand
AR 12 Address register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction register Holds instruction code
PC 12 Program counter Holds address of instruction
TR 16 Temporary register Holds temporary data
INPR 8 Input register Holds input character
OUTR 8 Output register Holds output character
PAGE 79
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 79 12-09-2024 17:25:38

 COMPUTER SYSTEM ARCHITECTURE

Notes IN-TEXT QUESTIONS

4. k bits can be used to specify in which of the ________ registers.
5. ________ operand is an operand whose address is stored in the
register or in the memory location specified.

4.8 The Common Bus

To avoid excessive wiring, memory and computer registers are connected
using a common bus as shown in Figure 4.3. The main job of this common
bus is to transfer data between registers and memory. The specific output
that is selected for the bus is determined by section variables S2S1S0. The
register whose LD (Load) is enabled will receive the data from the bus.
Values stored in the registers can be incremented by setting the INR control
input and can be cleared by setting the CLR control input. Note that the
Accumulator’s input must come via the Adder & Logic Circuit. This allows the
Accumulator and Data Register to swap data simultaneously. The address of
any memory location being accessed must be loaded in the Address Register.

Figure 4.3: Common Bus

4.9 Computer Instructions

The basic computer has three instruction code formats. Each instruction
format is of 16 bits.
Memory-reference format: In this format, opcode is followed by a 12-bit
memory address and preceded by a bit which indicates whether direct or
indirect addressing is being used.
80 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 80 12-09-2024 17:25:38

 Basic Computer Organization and Design

Register-reference format: This format starts with 0111 and is then fol- Notes
lowed by a 12 bit register instruction code.
Input-output format: This format starts with 1111 and is followed by a
12 bit input-output instruction code. Refer Figure 4.4 to understand how
the instruction format differs for each type of instruction.

Figure 4.4: Instruction Format

4.10 Instruction-Set Completeness

A computer instruction set is said to be complete if the computer includes
a sufficient number of instructions in the following categories:
Arithmetic, logical and shift instructions. In this category, computer
provides instructions for adding, subtracting, complementing and incre-
menting the accumulator. Instructions for performing AND, OR, XOR,
logical and arithmetic shifts are also supported.
Instructions for moving data from registers to memory and memory to
registers are provided. In this category, we have instructions like LDA,
STA, unconditional branches (BUN), subprogram calls (BSA) and con-
ditional branches (ISZ).
Instructions for Program-control and status-checking come under this
category. All Input and output instructions fall under this category. More-
over, instructions to generate and handle interrupts are also supported by
the computer.

PAGE 81
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 81 12-09-2024 17:25:38

 COMPUTER SYSTEM ARCHITECTURE

Notes Figure 4.5 lists basic memory-reference instructions.

Figure 4.5: Memory-Reference Instructions

Basic register reference instructions are listed in Figure 4.6.

Figure 4.6: Memory-Reference Instructions

Basic Input and Output Instructions are as given in Figure 4.7.

Figure 4.7: Input-Output Instructions

82 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 82 12-09-2024 17:25:39

 Basic Computer Organization and Design

Notes
4.11 Instruction Cycle
The instructions of a program are carried out by a process called the
instruction cycle (Figure 4.8). This cycle consists of these phases that are,
‹ ‹Fetch an instruction from memory
‹ ‹Decode the instruction
‹ ‹Read the effective address from memory if the operand has an
indirect address.
‹ ‹Execute the instruction.
The instruction cycle repeats until the halt instruction is executed.

Figure 4.8: The Instruction Cycle

Fetch and Decode

Initially, the Program Counter (PC) stores the address of the instruction
about to be executed and the Sequence Counter (SC) is cleared to 0.
With each clock pulses the SC is incremented and the timing signals go
through the sequence T0, T1, T2, etc.
So, initially, AR is loaded with the PC’s address at T0. Therefore, we
can write, T0: AR <- PC.
Subsequently, as we fetch the instruction to be executed, we must incre-
ment the program counter so that it points to the next instruction. At T1,
we therefore, write, T1: IR <- M[AR], PC <- PC + 1
At T2, we need to decode the instruction to understand which operation
has to be performed and 4 also prepare to fetch the operand. To determine

PAGE 83
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 83 12-09-2024 17:25:39

 COMPUTER SYSTEM ARCHITECTURE

Notes whether it is an indirect operand or not, we also need to check the indi-
rect field of the instruction code. So, we can write,
T2: D0, … D7 <- Decode IR(12-14), AR <- IR (0-11), I <- IR(15)

4.12 Type of Instruction and Addressing

During time T3, the control unit determines if this is a memory-reference,
register-reference or input/output instruction. Recall that register-reference
and input/output have 111 in the decoder bits. The two instructions can be
distinguished using the I (indirect) bit, which is 0 for register reference
and 1 for I/O instructions.
A memory-reference instruction can also be categorized using the I bit.
If I = 0, it is a direct memory addressing instruction and an indirect
addressing instruction if I bit is 1. For example, if D7 is 1, then, refer
the flowchart to analyse how one of the four paths is chosen. The four
separate paths are: D7 ’IT3: AR <- M[AR]
D7 ’I’T3: Nothing
D7 I’T3: Execute a register-reference instruction
D7 IT3: Execute an input-output instruction
Figure 4.9 demonstrates the flowchart of the entire instruction cycle
involved in executing a memory-reference instruction.

Figure 4.9: Flowchart for Executing Instructions

84 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 84 12-09-2024 17:25:39

 Basic Computer Organization and Design

Figure 4.10 gives execution of register reference instructions. Notes

Figure 4.10: Execution of register-reference instructions

Figure 4.11 gives execution of register reference instructions.

Figure 4.11: Memory Reference Instructions

Memory-Reference Instructions
All memory-reference instructions are executed at T 4 irrespective of
whether it is a direct or indirect memory addressing instruction. Instruc-
tions like AND, ADD and LDA are performed in two steps because AC
can only be access data via DR. The control signals for these operations
can be given as,

PAGE 85
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 85 12-09-2024 17:25:39

 COMPUTER SYSTEM ARCHITECTURE

Notes Instruction Operation

AND D0T4 : DR <- M[AR]
D0T5 : AC <- AC A DR, SC <- 0
ADD D0T4 : DR <- M[AR]
D0T5 : AC <- AC + DR, E <- Cout, SC <- 0
LDA D2T4 : DR <- M[AR]
D0T5 : AC <- DR, SC <- 0

STA stores the contents of the AC, which can be applied directly to the
bus. The instruction is specified as, D3T4: M[AR] <- AC, SC <- 0
Branch Unconditionally (BUN) transfers control unconditionally to the
effective address. It is specified as,
D4T4: PC <- AR, SC <- 0.
Branch and Save Return Address (BSA) is used to branch to a sub-
program (or a function). As you know, this requires saving the return
address. Usually, the computer saves the return address at the operand’s
effective address and the subprogram starts one location after this address
in memory:
D5T4: M[AR] <- PC, AR <- AR + 1
D5T5: PC <- AR, SC <- 0

Figure 4.12: Example of BSA Instruction Execution

86 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 86 12-09-2024 17:25:39

 Basic Computer Organization and Design

ISZ skips the next instruction if the operand stored at the given effec- Notes
tive address is 0. This requires that the PC incremented, which cannot
be done directly:
D6T4: DR <- M[AR]
D6T5: DR <- DR + 1
D6T6: M[AR] <- DR, if (DR = 0) then (PC <- PC + 1), SC <- 0

IN-TEXT QUESTIONS
6. ________ stores the address of the instruction about to be executed.
7. All memory-reference instructions are executed at ________.
8. ________ skips the next instruction if the operand stored at the
effective address is 0.

4.13 Input Output and Interrupt

A computer can serve no useful purpose unless it communicates with
the external environment. The terminal sends and receives 8 bit serial
information. The information from the keyboard is saved in INPR (that
is, the input register). Correspondingly, the information for the printer
is stored in the OUTR which is the output register. INR and OUTR
communicate with a communication interface serially and with the AC
in parallel. This is clear from the Figure 4.13.

Figure 4.13: Input-Output Process

PAGE 87
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 87 12-09-2024 17:25:39

 COMPUTER SYSTEM ARCHITECTURE

Notes The 1-bit input flag, FGI is a control flip-flop which is automatically
set to 1 when information is available to be read by the input device.
It is again automatically cleared (set to 0) when the information is read
by the computer.
The OUTR (or the output register) works in the same fashion but in
the opposite direction. Initially, the output flag, FGO is set to 1. The
computer checks the value of FGO. If FGO = 1, the information from
AC is moved to or transferred to OUTR and FGO is cleared to 0. The
output device reads the information, prints it and again set the flag to 1.
The computer will not further load any character into OUTR until FGO
is 0. As long as FGO is cleared, it indicates that the output device is in
the process of printing the character.
Some basic I/O operations are specified in Figure 4.14. Note that here,
p = D7IT3.

Figure 4.14: Input/Output Instructions

4.14 Interrupt Cycle

The interrupt cycle is nothing but the hardware implementation of a
branch and save return address instruction. The return address, that is,
the address stored in the program counter is saved at memory location 0.
Control then places, address 1 into program counter and sets the Interrupt
Enable Flag (IEN) to zero, IEN<- 0 and R <- 0 so that no more interrupts
can be generated until the interrupt request from the flag is received.
Look at the Figure 4.15 below to understand how it works.
88 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 88 12-09-2024 17:25:39

 Basic Computer Organization and Design

Notes

Figure 4.15: Demonstration of the Interrupt Cycle

The way the interrupt is handled by the computer can be explained using
a flow chart (Figure 4.16). An interrupt flip flop R is used. When R = 0;
computer executes an instruction cycle. While executing the instruction
cycle, IEN is checked by the control.
‹ ‹If IEN = 0, then it indicates that the programmer has disabled the
interrupt. So control executes another instruction cycle.
‹ ‹If IEN = 1; the control checks the flag bits-FGI and FGO. If
both of them are 0, then both INPR and OUTR are not ready for
transfer information. In this scenario, control continues with the
next instruction cycle.
‹ ‹If any of the two flags (FGI or FGO) is set to1 while IEN = 1
then R is set to 1.
After executing an instruction, the control checks the value of R. if
R = 1, then an interrupt cycle is initiated. Note that R can be set to 1 if
IEN = 1 and either the FGI or FGO are equal to 1. This can happen with
any clock transition except when timing signals T0, T1, T2 are active.
Therefore, the condition that sets R to 1 can be written as, T0ʹT1ʹT2ʹ
(IEN) (FGI + FGO): R ← 1.

PAGE 89
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 89 12-09-2024 17:25:39

 COMPUTER SYSTEM ARCHITECTURE

Notes Here, symbol + between FGI and FGO designate a logic OR operation.
This is ANDed with IEN and T0ʹT1ʹT2ʹ.

Figure 4.16: Flowchart for Interrupt Cycle

IN-TEXT QUESTIONS
9. When R = 0; computer goes through an ________ cycle.
10. If either flag (FGI or FGO) is set to 1 while IEN = 1 then
flip-flop ________ is set to 1 to initiate an interrupt cycle.

Case Study 1: A computer uses a memory unit with 256K words of 32

bits each. A binary instruction code is stored in one word of memory. The
instruction has four parts: an indirect bit, an operation code, a register
code part to specify one of 64 registers, and an address part.
(a) How many bits are there in the operation code, the register code
part, and the address part?
(b) Draw the instruction word format and indicate the number of bits
in each part.
(c) How many bits are there in the data and address inputs of the
memory?
90 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 90 12-09-2024 17:25:40

 Basic Computer Organization and Design

Notes

Case Study 2: The content of AC in the basic computer is hexadecimal

A937 and the initial value of E is 1. Determine the contents of AC, E,
PC, AR, and IR in hexadecimal after the execution of the CLA instruction.
Repeat 11 more times, starting from each one of the register-reference
instructions. The initial value of PC is hexadecimal 021.

Case Study 3: An instruction at address 021 in the basic computer has

I 0, an operation code of the AND instruction, and an address part equal
to 083 (all numbers are in hexadecimal). The memory word at address
083 contains the operand B8F2 and the content of AC is A937. Go over
the instruction cycle and determine the contents of the following regis-
ters at the end of the execute phase: PC, AR, DR, AC, and IR. Repeat
the problem six more times starting with an operation code of another
memory-reference instruction.
PAGE 91
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 91 12-09-2024 17:25:40

 COMPUTER SYSTEM ARCHITECTURE

Notes

Case Study 4: Show the contents in hexadecimal of registers PC, AR,

DR, IR, and SC of the basic computer when an ISZ indirect instruction
is fetched from memory and executed. The initial content of PC is 7FF.
The content of memory at address 7FF is EA9F. The content of memory
at address A9F is 0C35. The content of memory at address C35 is FFFF.
Give the answer in a table with five columns, one for each register and
a row for each timing signal. Show the contents of the registers after the
positive transition of each clock pulse.

Case Study 5: The content of PC in the basic computer is 3AF (all

numbers are in hexadecimal). The content of AC is 7EC3. The content
of memory at address 3AF is 932E. The content of memory at address
32E is 09AC. The content of memory at address 9AC is 8B9F.
(a) What is the instruction that will be fetched and executed next?
(b) Show the binary operation that will be performed in the AC when
the instruction is executed.
(c) Show the contents in hexadecimal of registers PC, AR, DR, IR, and SC

92 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 92 12-09-2024 17:25:40

 Basic Computer Organization and Design

Notes

4.15 Summary
‹ ‹Computer architecture is defined as those aspects of a system
that are visible to the user, such as data bits, instruction sets, and
addressing strategies, and that directly affect how a program is
executed logically.
‹ ‹Computer organization deals with how a system should be structured,
how its operational units and their linkages meet the architectural
standards, how the abstract model is realized, and how to execute
the system.
‹ ‹The operands are specified by indicating the registers and/or
memory locations in which they are stored. k bits can be used
to specify in which of the 2 k registers (or memory locations)
data is present.
‹ ‹Computer instructions are stored in consecutive memory locations
and are performed sequentially.
‹ ‹The instructions of a program are performed by a process called the
instruction cycle. The phases in this cycle are – Fetch-Decode-Execute.
‹ ‹All memory-reference instructions are executed at T4 irrespective
of whether it is a direct or indirect memory addressing instruction.
‹ ‹Once the execution phase is over, the control checks the value of
R. if R = 1, then an interrupt cycle is initiated.

PAGE 93
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 93 12-09-2024 17:25:40

 COMPUTER SYSTEM ARCHITECTURE

Notes
4.16 Answers to In-Text Questions
1. Program
2. Operand
3. Opcode
4. 2k
5. Indirect
6. Program Counter
7. T4
8. ISZ
9. Instruction
10. R

4.17 Self-Assessment Questions

1. Given, a computer having 64 registers, 256K words memory having
32 bits in each, an instruction code of 1 word of memory, draw
the instruction format if the instruction has 4 fields – an indirect
bit, operation code, register code and an address.
2. Explain why the following instructions cannot be executed during
a single clock pulse.
(a) IR <- M[PC]
(b) AC <- AC + TR
(c) DR <- DR + AC
3. If AC = A937 H, PC = 21H and E = 1, calculate the values of AC,
PC, E, AR and IR after the execution of every register reference
instruction. (For each instruction, assume the same initial values).
4. If PC = 21 H, I = 0, opcode specifies AND operation, address part
of instruction is 083 H, AC = A937H and the value at location 083
in memory is B8F2H. Calculate the values of AC, PC, E, AR and
IR after the execution of every memory reference instruction. (For
each instruction, assume the same initial values).

94 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 94 12-09-2024 17:25:40

 Basic Computer Organization and Design

5. If PC = 7FFH, content at 7FFH is EA9FH, content at A9FH is Notes

0C35H and content at C35H is FFFFH then show how the values
of AC, PC, E, AR and IR will change during execution of the
instruction.
6. If PC = 3AFH, AC = 7EC3H, content of 3AFH is 932EH, content
of 32EH is 09ACH and the content of 9ACH is 8B9FH, then which
instruction will be fetched, calculate the values of AC, PC, E, AR,
IR and E after the instruction is executed.

4.18 References
u Computer System Architecture by M. Morris Mano, Third edition,
1993, Prentice Hall of India.
u Computer System Architecture by M. Morris Mano, Third edition,
1993, Pearson Education.

4.19 Suggested Readings

u H&P3: Hennessy, J. L., and D. A. Patterson. Computer Architecture:
A Quantitative Approach, 3rd ed. San Mateo, CA: Morgan Kaufman,
2002. ISBN: 1558605967.
u H&P2: Hennessy, J. L., and D. A. Patterson. Computer Architecture:
A Quantitative Approach, 2nd ed. San Mateo, CA: Morgan Kaufman,
1995. ISBN: 1558603727.
u P&H: Patterson, D. A., and J. L. Hennessy. Computer Organization
and Design: The Hardware/Software Interface, 3rd ed. San Mateo,
CA: Morgan Kaufman, 2004. ISBN: 1558606041.

PAGE 95
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 95 12-09-2024 17:25:40

 L E S S O N

5
Addressing Modes
Dr. Reema Thareja
Assistant Professor
Department of Computer Science
School of Open Learning
University of Delhi
Email-Id: [email protected]

STRUCTURE
5.1 Learning Objectives
5.2 Introduction
5.3 Addressing Mode
5.4 Implied Mode
5.5 Immediate Addressing Mode
5.6 Register Mode
5.7 Register Indirect Mode
5.8 Auto Increment or Auto Decrement Addressing Mode
5.9 Direct Addressing Mode
5.10 Indirect Addressing Mode
5.11 Relative Address Mode
5.12 Indexed Addressing Mode
5.13 Base Register Addressing Mode
5.14 Numerical Example
5.15 Applications of Addressing Modes
5.16 Summary
5.17 Answers to In-Text Questions
5.18 Self-Assessment Questions
5.19 References
5.20 Suggested Readings

96 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 96 12-09-2024 17:25:40

 Addressing Modes

Notes
5.1 Learning Objectives
After reading the chapter, you will be able to understand the following
concepts:
‹ ‹Effective Address.
‹ ‹Computing effective address in case of different addressing modes.
‹ ‹Applications of addressing modes.

5.2 Introduction
These days, programmers write programs using high-level languages (like
C, C++, R, Python, Java, etc), as it is convenient for them to define
variables and specify operations. However, since computers understand
only binary language, these programs are compiled to generate the actual
machine code. A machine code includes low-level instructions.
In the previous chapter, we have seen that a machine instruction contains
an operation field, an address field, and a mode field. While the operation
field (opcode) indicates the operation to be performed (for example, addition,
subtraction, multiplication, etc), the mode field indicates how the memory
address of the operand (data on which the operation will be performed) is
determined. Computers can use the address field and the mode field to com-
pute the effective address of the operand in multiple ways. These different
ways are termed as addressing modes. But, before starting our discussion
on addressing modes, let us first recall the instruction cycle of a computer.
‹ ‹Fetch the instruction from the memory
‹ ‹Decode the instruction
‹ ‹Execute the instruction
Now, to fetch the instruction, we need to find the effective address and
the effective address (address of the operand or data specified in an
instruction). This address is calculated using an addressing mode. So let
us see in detail, what an addressing mode is.

5.3 Addressing Mode

The addressing mode states the rule for specifying the address part of the
instruction before the operand is actually used. It not only gives flexibility
PAGE 97
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 97 12-09-2024 17:25:40

 COMPUTER SYSTEM ARCHITECTURE

Notes to program but also reduces the number of bits in the address part of the
instructions. The mode field indicates how to locate the operand and the
address part specifies either a memory address or a processor register.
The effective address of the operand may be stated using different address-
ing modes. Some of them are explained in the next section.

5.4 Implied Mode

In this mode, the operand is implied by the instruction itself. Hence, the
name. For example, the instruction, CMA – Complement Accumulator is an
implied-mode instruction because just by reading the name of the instruction,
it is clear that the operand is present in the accumulator register. The struc-
ture of an implied mode instruction can be given as shown in Figure 5.1,

Figure 5.1: Structure of an Implied Mode Instruction

Advantage: No memory reference is required.

Disadvantage: Limited operand.

5.5 Immediate Addressing Mode

In this mode, the operand is a part of the instruction. The operand imme-
diately follows the opcode field of the instruction. Therefore, an immediate
instruction has an operand field rather than an address field. The operand
field has the operand on which the operation will be performed. For exam-
ple, the instruction MOV AC, 10 is an immediate instruction because the
operand (value to be moved in Ac), is directly available in the instruction.
Thus, such instructions are used to initialize register to a constant value.
The format of immediate addressing mode instruction is given in Figure 5.2.

Figure 5.2: Format of Immediate Addressing Mode Instruction

Advantage: Memory reference is not required.

Disadvantage: Limited operand.
98 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 98 12-09-2024 17:25:40

 Addressing Modes

IN-TEXT QUESTIONS Notes

1. ________ specifies how to interpret the address field of the

instruction before the operand is actually used.
2. In ________ mode, the instruction consists of both the opcode
and the operand.
3. Add 10 is an example of ________ mode.

5.6 Register Mode

In this mode, the instruction has a CPU register. This register stores the
operand. An example of register mode instruction is:
ADD AC, R
This instruction will add the operand in register R to the value available
in the accumulator. We can understand this mode pictorially by seeing
the Figure 5.3.

Figure 5.3: Format of Register Mode Instruction

Advantage: Memory reference is not required.

Disadvantage: Limited CPU registers.

5.7 Register Indirect Mode

In this mode, the instruction has a CPU register. Contents of this register
specify the address of the operand in the memory. That is, the register
does not have the operand but the address of the operand. For example,
the instruction, ADD AC, [R] is a register indirect instruction because
the value stored at memory location (whose address is in the register)
will be added to the contents of the accumulator. Look at the Figure 5.4
to visualize this concept.
PAGE 99
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 99 12-09-2024 17:25:40

 COMPUTER SYSTEM ARCHITECTURE

Notes

Figure 5.4: Register Indirect Mode Instruction Format

Advantage: Large address space because the contents of register can

specify any memory location.
Disadvantage: Extra memory reference is required.

5.8 Auto Increment or Auto Decrement Addressing Mode

This addressing mode is same as register indirect mode except that the
register is either incremented or decremented before or after its value is
used to access the memory.
Auto increment or auto decrement addressing mode is very helpful when
the address stored in the registers refers to an array or a table of data
in memory. In such a case, the next address can be easily and quickly
generated by incrementing or decrementing the value stored in the register
after accessing every value stored in the table.
Since, it is similar to register indirect addressing mode, the address
part of the instruction is used by the control unit in the CPU to get the
operands from memory.

5.9 Direct Addressing Mode

In this mode, the effective address is the address specified in the address
part of the instruction. This means that the operand is stored at the mem-
ory location whose address is given in the address part of the instruction.
For example, ADD AC, [4000H] instruction is a direct addressing mode
instruction, as the operand is stored at address 4000H in the memory.
We can either specify the address of the operand or specify a memory
variable. Since memory variables are nothing but memory locations storing
values. So, ADD AC, COUNT is also an example of direct addressing

100 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 100 12-09-2024 17:25:40

 Addressing Modes

instruction. The instruction will add the value stored at address (location) Notes
named COUNT with the value present in the accumulator.
In such instruction the effective address (EA) is equal to the address part of
the instruction. We can understand this addressing mode using the Figure 5.5.

Figure 5.5: Format of Direct Addressing Mode Instruction

Advantage: Simple to use.
Disadvantage: limited address field.

5.10 Indirect Addressing Mode

In this mode, the address field of the instruction specifies an address
where the effective address is stored in memory. The operand is stored
at the effective address in the main memory. So, here, the control unit
fetches the instruction from the memory and uses its address part to get
the effective address. Pictorially, this addressing mode can be seen as
given in the Figure 5.6.

Figure 5.6: Format of Indirect addressing mode Instruction

Here, effective address, EA is the address stored at the address part of
the instruction.
Advantage: Flexibility.
Disadvantage: Complexity.

PAGE 101
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 101 12-09-2024 17:25:40

 COMPUTER SYSTEM ARCHITECTURE

Notes
5.11 Relative Address Mode
In this mode, the effective address is calculated by adding the value
stored in the address part of the instruction with the value stored in
the program counter (PC). For example, if the address field has value
850, and the program counter contains 20, then the operand is stored at
memory address, 850 + 20 = 870. Look at the Figure 5.7 to visualize
relative addressing mode.

Figure 5.7: Format of Relative Address Mode Instruction

Here, Effective Address (EA) = PC + A

And A, the address part of the instruction is a signed number (either
a +ve or a –ve number).
Advantage: Flexibility.
Disadvantage: Complexity.

IN-TEXT QUESTIONS
4. In ________ addressing mode, value stored in the register is the
address of the operand in the memory.
5. In ________ addressing mode, EA is the address stored at the
address part of the instruction.
6. In relative addressing mode, the effective address is calculated
by adding the value in the address part of the instruction with
the value stored in the ________.

102 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 102 12-09-2024 17:25:40

 Addressing Modes

Notes
5.12 Indexed Addressing Mode
In this mode, the effective address is obtained by adding the contents of
an index register (referred as XR) to the address part of the instruction.
This can be written as, Effective Address (EA) = XR + A
This addressing mode is useful when we have an array. In such a case,
the address field of the instruction has the starting address of the array.
The distance between the starting address and the operand is given by
the index, i. This index is stored in the index register. All values of the
array are thus stored in consecutive memory locations. Every value is
stored relative to the address of the first element in the array.

5.13 Base Register Addressing Mode

In this mode, the effective address is calculated by adding the value in
base register (BR) to the vaue stored in the address part of the instruc-
tion. This is like indexed addressing mode but the only difference here
is that, in base register addressing mode, as the name implies, we will
add the value in the base register rather than that of the index register.
The base register addressing mode is used in computers to relocate pro-
grams in memory i.e. to move programs and data from one segment of
the memory to another.
Here, Effective Address (EA) = BR + A

5.14 Numerical Example

Consider a scenario in which the two-word instruction Load To AC is
stored at address 200 and 201. The address part of the instruction has
value 500.
The first word of the instruction has the operation code and mode, and
the second word has the address. Assuming that PC = 200, Processor
Register Rl = 400, and Index Register XR = 100. Now compute the
effective address and the value loaded into AC for the addressing modes
discussed above.

PAGE 103
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 103 12-09-2024 17:25:40

 COMPUTER SYSTEM ARCHITECTURE

Notes

Solution:
‹ ‹Direct Addressing Mode: In this mode, the effective address is
specified as the address part of the instruction. Here, it is 500.
Since EA = 500, the operand to be loaded into AC is 800, that is
the value stored at address 500.
‹ ‹Immediate Addressing Mode: In this mode, the second word of the
instruction is taken as the operand rather than an address. Therefore,
according to the given instruction, 500 is the value that will be
loaded into AC. Since, address of value 500 is 201, the effective
address here is 201.
‹ ‹Indirect Addressing Mode: In this case, the effective address can
be obtained from the address part of the instruction. Since, address

104 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 104 12-09-2024 17:25:41

 Addressing Modes

500 is given in the instruction, EA = 800, the value stored at 500. Notes
Now that EA = 800, the operand or the value to be loaded into
AC is 300.
‹ ‹Relative Mode: In this addressing mode, the effective address is
calculated as the sum of PC and address part of the instruction.
Therefore, in this case, EA = 500 + 202 = 702. Correspondingly, the
operand is 325. Thus, after the execution of this instruction AC will
have the value 325. Note that initially, PC was 200, after fetching
the current instruction, PC becomes 202 as it is the address of the
next instruction. Load To AC is a two word instruction consuming
addresses 200 and 201.
‹ ‹Index Addressing Mode: In this mode, the effective address is
calculated as the sum of index register and the address part of the
instruction. Therefore, EA = XR + 500 = 100 + 500 = 600 and the
operand is 900, that is, the value stored at address 600.
‹ ‹Register Mode: In the register mode, the operand is in the register.
Since, the register R1 has value 400, this is the operand and will
be loaded into AC. Note that there will be no effective address in
this case.
‹ ‹Register Indirect Mode: In this mode, the effective address is given
in the register. In this case, register, R1 has 400, so the effective
address is 400 and the operand is the value stored at 400, which
is 700 in this case. Therefore, 700 will be loaded into AC.
‹ ‹Auto-increment Mode: It is same as the register indirect mode
except that Rl is incremented after the execution of the instruction.
Therefore, RI = 401.
‹ ‹Auto-decrement Mode: It is same as the register indirect mode
except that it decrements Rl before executing the instruction. So,
in this case, the effective address is 399 and the operand loaded
into AC is 450.
The table given below summarizes the effective address and the operand
loaded into AC for all the addressing modes discussed above.

PAGE 105
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 105 12-09-2024 17:25:41

 COMPUTER SYSTEM ARCHITECTURE

Notes

5.15 Applications of Addressing Modes

The applications of various addressing modes are as follows:
‹ ‹Immediate addressing mode is used to initialize a register with
some constant value. For example, MOV AC, 10.
‹ ‹Register addressing mode and direct addressing mode are best
to implement variables and access static data. For example, MOV
AC, COUNT.
‹ ‹Register indirect addressing mode and indirect addressing modes
are usually used to access an array or to implement pointers.
‹ ‹Relative addressing mode is used to relocate programs at run time
and to change the execution order of instruction.
‹ ‹Index addressing mode is also used to implement arrays.
‹ ‹Base register addressing mode is used to write codes that are
either re-locatable or handles recursion.
‹ ‹Auto-increment/decrement addressing mode is used to implement
loops and stacks.

IN-TEXT QUESTIONS
7. In ______ addressing mode, the effective address is calculated by
adding the value of XR to the address part of the instruction.
8. The _________ addressing mode is used in computers to relocate
programs in memory.
106 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 106 12-09-2024 17:25:41

 Addressing Modes

Notes
5.16 Summary
‹ ‹Programmers write programs using high-level languages which are
then compiled to generate the actual machine code. A machine code
includes low-level instructions.
‹ ‹The addressing mode indicates the rules for calculating the address
field of the instruction before the operand is actually used.
‹ ‹In implied mode the operand is implied by the instruction itself.
‹ ‹In immediate mode, the operand is a part of the instruction.
‹ ‹In register mode, the instruction specifies a CPU register
‹ ‹In register indirect mode, the instruction specifies a CPU register.
Contents of this register specify the address of the operand in the
memory.
‹ ‹In auto increment or decrement addressing mode is same as register
indirect mode except that the register is incremented or decremented
before or after its value is used to access memory.
‹ ‹In direct addressing mode, the effective address is equal to the
address part of the instruction.
‹ ‹In indirect addressing mode, the address field of the instruction
specifies an address where the effective address is stored in memory.
‹ ‹In relative addressing mode, the effective address is calculated by
adding the value of the address part of the instruction with the
value stored in the Program Counter (PC).
‹ ‹In indexed addressing mode, the effective address is obtained by
adding the contents of an index register (referred as XR) to the
address part of the instruction.
‹ ‹In base register addressing mode, the effective address is calculated
by adding the value of the Base Register (BR) to the address part
of the instruction

5.17 Answers to In-Text Questions

1. The addressing mode
2. Immediate addressing mode

PAGE 107
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 107 12-09-2024 17:25:41

 COMPUTER SYSTEM ARCHITECTURE

Notes
3. Immediate addressing mode
4. Register indirect
5. Indirect
6. Program Counter (PC)
7. Indexed
8. Base register

5.18 Self-Assessment Questions

1. The memory unit of a computer has 256K words of 32 bits each.
The instruction format specifies information about four fields-
operation code, addressing mode, register and a memory address.
If the system supports 7 addressing modes and 60 registers, give
the instruction format.
2. A two-word instruction is stored in memory at address W. The
address field of the instruction is given as Y. the operand used
during the execution of the instruction is stored at an address Z.
An index register contains the value X. State how Z is calculated
from the other addresses if the addressing mode of the instruction
is – direct, indirect, relative, indexed.
3. A relative mode branch type of instruction is stored in memory at
address 750. The branch is made to address 500. What should be
the value of relative address field of the instruction?
4. How many times is the memory referenced in case the operand is
specified using an indirect addressing mode instruction? What will
be the answer if it a branch instruction?
5. What must be content of the address field of an indirect addressing
mode instruction to make it same as register indirect mode instruction?
6. Consider a scenario in which an instruction is stored at location
300 with address field at 301. The value of the address field is 400.
CPU register R1 contains value 200. Calculate the effective address
with the following addressing modes-direct, immediate, relative,
register indirect, indexed register with R1 as the index register.

108 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 108 12-09-2024 17:25:41

 Addressing Modes

Notes
5.19 References
u Computer System Architecture by M. Morris Mano, Third edition,
1993, Prentice Hall of India.
u Computer System Architecture by M. Morris Mano, Third edition,
1993, Pearson Education.

5.20 Suggested Readings

u John P Hayes “Computer Architecture and organization” McGraw
Hill.
u Dezso Sima,Terence Fountain and Peter Kacsuk “Advanced Computer
Architecture” Pearson Education.
u Kai Hwang “Advanced Computer Architecture” TMH.
u Linda Null, Julia Lobur-The Essentials of Computer Organization
and Architecture, 2014, 4th Edition.
u H&P3: Hennessy, J. L., and D. A. Patterson. Computer Architecture:
A Quantitative Approach, 3rd ed. San Mateo, CA: Morgan Kaufman,
2002. ISBN: 1558605967.
u H&P2: Hennessy, J. L., and D. A. Patterson. Computer Architecture:
A Quantitative Approach, 2nd ed. San Mateo, CA: Morgan Kaufman,
1995. ISBN: 1558603727.
u P&H: Patterson, D. A., and J. L. Hennessy. Computer Organization
and Design: The Hardware/Software Interface, 3rd ed. San Mateo,
CA: Morgan Kaufman, 2004. ISBN: 1558606041.

PAGE 109
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 109 12-09-2024 17:25:41

 L E S S O N

6
Input Output Organization
Dr. Reema Thareja
Assistant Professor
Department of Computer Science
School of Open Learning
University of Delhi
Email-Id: [email protected]

STRUCTURE
6.1 Learning Objectives
6.2 Introduction
6.3 Peripheral Devices
6.4 ASCII (American Standard Code for Information Interchange)
6.5 Input-Output Interface
6.6 I/O BUS and Interface Module
6.7 I/O Bus Versus Memory Bus
6.8 Isolated I/O Bus Versus Memory Mapped I/O Bus
6.9 Mode of Transfer
6.10 Programmed I/O
6.11 Interrupt Driven I/O
6.12 Direct Memory Access (DMA)
6.13 Summary
6.14 Answers to In-Text Questions
6.15 Self-Assessment Questions
6.16 References
6.17 Suggested Readings

110 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 110 12-09-2024 17:25:41

 Input Output Organization

Notes
6.1 Learning Objectives
After studying this chapter, you will be able to:
‹ ‹Define peripheral devices.
‹ ‹Explain Input/Output (I/O) interfaces.
‹ ‹List the data transfer schemes.
‹ ‹Explain the concept of program control.
‹ ‹Describe interrupts.
‹ ‹Explain the concept of DMA transfer.
‹ ‹Define I/O Processors.

6.2 Introduction
We know that computer organization refers to operational units and their
interconnections that conform to the architecture specifications. A computer
is a complex system that consists of a large number of components. A com-
puter is of no use if it does not communicate with the external environment.
A user provides instructions to the computer through input devices, and
the input data from the user after processing is stored in the memory. The
results of processing are displayed to the user through an output device.
Though peripheral devices are not essential for the computer to perform
its basic tasks, they do add to user’s experience. So, we can say that,
peripheral devices are not a part of the core computer system architecture.
The term, peripheral, more loosely refers to a device that is external to
the computer case. In this section we will look into some of the periph-
eral devices that are commonly used by users these days.

6.3 Peripheral Devices

A computer uses peripheral devices to send and receive input/output from
the user of the system. These devices can be categorized into three basic
categories- Input Devices, Output Devices and Storage Devices.
Input Devices: The input device converts input data and instructions into
binary code that can be understood by a digital computer. Some commonly
used input devices are given in Figure 6.1.
PAGE 111
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 111 12-09-2024 17:25:41

 COMPUTER SYSTEM ARCHITECTURE

Notes

Figure 6.1: Commonly Used Input Devices

Output Devices: An output device translates the digitized signals into a
form that can be read and interpreted by the user. Some commonly used
input devices are given in Figure 6.2.
Monitors are output devices as they display an electoral visual
display for the computers.
Printers are output devices as they produce text and pictures made
on the computer or laptop.
Speakers are output devices as they play sound produced from
the computer or laptop.
Headphones are similar to speakers, meaning that they both play
sound produced by electrical equipment, there- fore headphones
are output devices.
A plotter is an output device as it sends pictures and drawing
from a computer to it and produces those drawings in ink.
Projectors are output devices as they display what is on a compute
or electrical device on a much larger scale.

Figure 6.2: Commonly Used Output Devices

112 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 112 12-09-2024 17:25:41

 Input Output Organization

Storage Devices: Storage devices are used to store Notes

data in the system which will be later used for
access or further processing. In the past, magnetic
tapes were used for data storage. The data could be
read and written only in sequential order. Tapes were
the cheapest medium for storage in those days as they could store a large
number of binary digits on every inch of the tape. But these days storage
devices listed in the figure given below are commonly used for data storage
and retrieval. The main storage device used in our computers is the hard
disk. The hard disk stores information on one or more circular disks that
are continuously spinning. These rotating disks are coated with a magnetic
material and are stacked with spaces between them. Information is recorded
on the surface of the magnetic disks by magnetic heads as tiny magnetic
spots. Other commonly used storage devices are shown in Figure 6.3.

Figure 6.3: Commonly Used Storage Devices

6.4 ASCII (American Standard Code for Information

Interchange)
ASCII codes are alphanumeric characters. Input/output devices that com-
municate with people and the computer transfer alphanumeric Information
to and from the device and the computer.
PAGE 113
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 113 12-09-2024 17:25:41

 COMPUTER SYSTEM ARCHITECTURE

Notes ASCII codes uses 7 bits to code 128 different characters. Out of these
128 characters, 94 are printable and 34 are non-printing characters used
for various control functions. Among 94 printable characters, 26 are
uppercase letters, 26 are lowercase letters, 10 are digits and 32 are spe-
cial characters.
The 34 control characters are used for routing and arranging the printed
text in a prescribed format. These characters are divided into three cat-
egories:
Format Effectors: These control characters control the layout of printing.
Examples of format effectors include BS- Back Space, HT- Horizontal
Tab, CR- Carriage Return.
Information Separators: These characters separate data into paragraphs
and pages. Examples include RS- Record Separator and FS- File Separator
Communication Control Characters: They are basically used for trans-
mission of text between remote terminals. Examples include STX-Start
of text, ETX-End of text.

6.5 Input-Output Interface

I/O Interface helps to transfer information to and from the internal storage
and the external I/O devices. Peripheral devices connected to a computer
have special communication links to interface with the CPU. Such a link
resolves differences between the central computer and each peripheral
device. Some of these prominent differences include,
1. While peripherals are electro-mechanical and electromagnetic devices,
CPU and memory are electronic devices.
2. Peripheral devices transfer data at a much slower rate as compared
to CPU, so the two must be synchronized.
3. Formats of data and codes used by peripheral devices are different
from those used in the CPU and memory.
4. The operating modes vary from one peripheral to another. To resolve
these differences to allow smooth working of the devices, computer
systems have Interface Units between the CPU and the peripheral
devices. These units supervise and synchronize all input and out
transfers.

114 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 114 12-09-2024 17:25:41

 Input Output Organization

Notes
6.6 I/O BUS and Interface Module
Refer figure given below which shows that the I/O interface module
provides a link between the processor and peripherals. The I/O Bus, on
the other hand, has data, address and control lines. The I/O bus from the
processor is connected to the interface of all the peripherals devices. To
communicate with a particular device, the processor puts the address on
the address lines. Each interface decodes and interprets the address as
well as the control signals received from the I/O bus.
The I/O bus also synchronizes the data flow and supervises data exchange
between peripheral and the processor. Each peripheral device connected
to the CPU has its own controller. For example, the printer controller
controls the paper motion, the print timing.

Figure 6.4: I/O BUS and Interface Module

From Figure 6.4, it is clear that when the interface finds its own address on
the address lines, it activates the path between the bus and the device that
it controls. Rest of the devices are disabled by their respective interfaces.
Note that the processor floats a function code in the control lines (also
known as I/O command). These commands can be one of the following
commands.
‹ ‹Control command to activate the peripheral and instruct it what to do.
‹ ‹Status command to check the status in the interface and in the
peripheral devices.
PAGE 115
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 115 12-09-2024 17:25:42

 COMPUTER SYSTEM ARCHITECTURE

Notes ‹ ‹Data Output command facilitates the interface to respond by

transferring data from the bus into one of its registers.
‹ ‹Data Input command is just the reverse of data input command.

6.7 I/O Bus Versus Memory Bus

The processor also needs to communicate with the memory unit. Like the
I/O bus, the memory bus also contains data, address and read/write control
lines. The CPU can communicate with memory and I/O in three ways.
i. Use two separate buses- one for memory and the other for I/O
ii. Use a single bus for memory and the I/O. However, separate control
lines can be used for each.
iii. Use a single bus for memory and I/O and common control lines.
IOP: When we use two separate buses (as in case i), the computer has
independent data, address and control buses for accessing memory and
I/O. Such a configuration is used in computers that have a separate Input
Output Processor (IOP) in addition to the CPU.
In this configuration, memory communicates with CPU and IOP using
memory bus. Similarly, the IOP communicates with the I/O devices using
a separate IO bus. This makes an independent path between external
devices and the memory.

6.8 Isolated I/O Bus Versus Memory Mapped I/O Bus

Many computers use a common bus to exchange data with memory or
IO. The CPU specifies whether address is for memory or for IO. If the
control lines states IO read write, then the address is for IO devices.
Similarly, if the control lines specify memory read/write, then the address
is for the memory.
Isolated I/O Bus: Memory transfer and I/O transfer are distinguished
through separate Read and Write lines as shown in Figure 6.6. When
an I/O transfer occurs, the I/O read and I/O write control signals are
enabled. Similarly, Memory read and write control lines are enabled for
a memory transfer. This configuration isolates all I/O interface addresses

116 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 116 12-09-2024 17:25:42

 Input Output Organization

from memory addresses. Moreover, for each of these, there are different Notes
input and output instructions. When CPU fetches and decodes the operation
code for an I/O instruction, it places an address for I/O interface on the
address line and either I/O Read or Write command on the control line.
Correspondingly, if the CPU fetches a memory instruction, it places
memory address on address lines and memory read/write command on
the control line.

Figure 6.5: Isolated I/O Bus

Memory Mapped I/O Bus: In this configuration, a single set of read/
write control lines are used which do not distinguish between memory and
I/O transfer. Even the memory and I/O addresses are shared as shown in
Figure 6.6. So, there is no specific input or output instructions. Therefore,
the instruction So, the same memory reference instructions can be used
for I/O transfers ∙ Considerable flexibility in handling I/O operations

Figure 6.6: Isolated I/O Bus

PAGE 117
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 117 12-09-2024 17:25:42

 COMPUTER SYSTEM ARCHITECTURE

Notes IN-TEXT QUESTIONS

1. ________ refers to operational units and their interconnections
that conform to the architecture specifications.
2. ________ device translates the digitized signals into a form that
can be read and interpreted by the user.
3. ASCII codes uses ________ bits to code 128 different characters.
4. I/O Interface helps to transfer information to and from the
________ storage and the ________ I/O devices.

6.9 Mode of Transfer

Typically, the memory unit stores binary data that is received from an
external device. The memory unit is the source of the data that is sent
from the CPU to the external device. The memory unit is always the
source and the target; the CPU only processes the data. There are various
ways in which data can be sent between the CPU and the I/O devices.
There are three possible ways to transfer data to and from the peripherals.
Programmed I/O: Programmed I/O depends on how the computer pro-
gram’s I/O instructions are written. Every data item transfer is started
by a program instruction. Usually, the data transfer is to and from CPU
and a peripheral device but data transfer to and from CPU and memory
is also possible. In programmed I/O, CPU must continuously monitor the
data transfer process.
Example of Programmed I/O: In this case, there is no direct commu-
nication between the memory unit and the I/O device. The CPU must
carry out multiple instructions to transfer data from an I/O device to
memory. These instructions include- an input instruction to move data
from the device to the CPU and a store instruction to move data from
the CPU to memory. When data transfer is enabled for programmed I/O,
the CPU remains in the program loop until the I/O unit signals that it
is ready for data transfer. Because it keeps the CPU busy unnecessarily,
this procedure takes a long time. An interrupt facility can be used to
prevent this kind of scenario.

118 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 118 12-09-2024 17:25:42

 Input Output Organization

Advantages: Notes
‹ ‹Easy to implement.
‹ ‹Less hardware support is required
‹ ‹CPU periodically checks the status bits.
Disadvantages:
‹ ‹The processor wastes a lot of time waiting for the I/O module to
transfer or receive data.
‹ ‹System’s performance is severely degraded.
Interrupt-initiated I/O: In the interrupt initiated IO, the interface is
commanded to send out an interrupt request signal whenever data is
available from IO device. This configuration extensively use interrupt
facility and certain commands to allow CPU to continue running any
other program in the interim. Meanwhile, the interface continues to
monitor the IO devices.
The IO device sends an interrupt request signal to the CPU whenever it
detects that it is ready to transfer data. On receiving the interrupt signal,
CPU temporarily suspends the program it was executing, and switches
to service the interrupting program to handle the I/O transfer. CPU then
resumes its work.
Advantages:
‹ ‹Faster and more efficient than Programmed I/O.
‹ ‹Less hardware support is required
‹ ‹CPU does not have to periodically check the status bits.
Disadvantages:
‹ ‹Comparatively difficult to implement.
‹ ‹Support required from underlying hardware and operating system
Direct Memory Access: The CPU’s speed limits the amount of data
that can move between a memory unit and a fast storage device like a
magnetic disk. Thus, we may do away with the CPU’s intervention and
enable peripherals to communicate directly with one another via memory
buses. Direct Memory Access, or DMA, is the term used to describe
this kind of data transfer method. The CPU is not in use and has no
control over the memory buses during DMA. In order to govern the

PAGE 119
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 119 12-09-2024 17:25:42

 COMPUTER SYSTEM ARCHITECTURE

Notes direct transfer between the memory unit and the I/O devices, the DMA
controller assumes control of the buses.
DMA allows devices to exchange and receive data from a computer’s
main memory, including disk drives, external memory, graphics cards,
network cards, and sound cards. It allows the CPU to continue working
on other tasks while data is exchanged between memory and the disk.

Figure 6.7: DMA vs Programmed IO

Advantages:
‹ ‹I/O interfaces provide a standard way of communicating with
external devices. This allows different devices to be connected to
the computer using the same interface.
‹ ‹I/O interfaces facilitates adding/ removing different devices from
a computer without affecting the other components. This makes it
easier to replace a faulty device.
‹ ‹Datais transferred at a high speed between I/O interfaces and the
computer.
‹ ‹I/O interfaces are compatible with a number of devices. This allows
users to choose from a variety of devices for data transfer.
Disadvantages:
‹ ‹I/O interfaces are often expensive, especially if specialized hardware
is required to connect a particular device to a computer system.
‹ ‹Some I/O interfaces are difficult to configure especially when
specialized hardware is required to set up and maintain the system.

120 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 120 12-09-2024 17:25:42

 Input Output Organization

‹ ‹Though I/O interfaces are compatible with a wide range of devices, Notes
there can still be compatibility issues.
‹ ‹There can be a security risk if devices are not properly configured.
Hackers may exploit these vulnerabilities to gain unauthorized access
to a computer system or steal data.

6.10 Programmed I/O

In Programmed I/O, each data transfer is initiated by an instruction in
the program. The data is transferred between CPU and an IO device.
A separate set of instructions are used to transfer the data to and from
CPU and memory.
Data transfer using Programmed I/O, requires constant monitoring of the
peripheral by the CPU. The CPU waits for the interface to see when a
transfer can again be made.
In Figure 6.8, we see that initially, the CPU sends the address and read/
write signals to the IO device. The peripheral device transfers several bytes
of data one at a time when they are available. As soon as a byte of data is
available, the device places it in the I/O bus and enables data valid line.
The interface stores data into its data register and enables data accepted
line. It also sets the Flag bit in the status register. A computer program
is written to check the flag bit in the status register to see if a byte has
placed in the data register by the I/O device.
If the flag bit is one, CPU reads the data from data register else the
data accepted line is disabled. The same flow can be understood using
a flowchart.

Figure 6.8: Data Transfer from I/O device to CPU

PAGE 121
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 121 12-09-2024 17:25:42

 COMPUTER SYSTEM ARCHITECTURE

Notes Examples: Reading information from a mouse or keyboard involves the

CPU constantly checking the device for keystrokes or mouse movements.
Writing data to a printer involves the CPU starting the print job, monitoring
the printer’s status bit, and sending small bursts of data.

6.11 Interrupt Driven I/O

In this technique, an interrupt is used to inform the device about the start
and end of transfer. Meanwhile, the CPU executes another program. When
the interface sees that the device is ready for data transfer, an interrupt is
sent to the CPU. On receiving the interrupt, the CPU temporarily stops the
execution of the program and branches to a service program to process
the I/O transfer. After completing the execution of the service program,
the CPU resumes with the task it was originally performing.
Unlike Programmed IO, in interrupt driven IO, CPU does not have to
repeatedly check the flag. It continues to perform its task. Only on
receiving the interrupt, CPU temporarily suspends it current task, stores
the return address from PC and branches to the address of the subroutine.
The branch address can be calculated in two ways:
Non-vectored Interrupt: When a non-vectored interrupt is generated, the
branch address is assigned to the fixed address in the memory.
Vectored Interrupt: In case of a vectored interrupt, the source that
interrupts the CPU provides the branch information. So, in this case the
branch address is not a fixed memory location. Rather, it is calculated
using the information (vector) sent to the CPU.

6.12 Direct Memory Access (DMA)

In DMA, the IO interface directly transfers data to or from memory unit
using the memory bus in the absence of CPU. This is important because,
the speed of the CPU often limits the amount of data that can be trans-
ferred between memory and a fast storage device (like, magnetic disk).
With CPU in between the memory and IO device, the IO device sends
data to CPU and CPU shares it with memory thereby slowing down the
data transfer process. Now, the peripheral device can itself manage the
memory buses directly allowing fast memory access. In the meantime,

122 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 122 12-09-2024 17:25:42

 Input Output Organization

the CPU relinquishes the control of busses and is placed in an idle state. Notes
Look at Figure 6.9 which summarizes the contrast between the three
modes of data transfer modes using a flowchart.

Figure 6.9: Three Techniques for Input of a Block of Data

DMA Block diagram

Figure 6.10 shows a basic block diagram for DMA transfer.

Figure 6.10: DMA Transfer Block Diagram

PAGE 123
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 123 12-09-2024 17:25:42

 COMPUTER SYSTEM ARCHITECTURE

Notes The Bus Request control signal requests the DMA controller to ask the
CPU to relinquish (or leave) the control buses.
As the name suggests, the Bus Grant signal activated by the CPU informs
the DMA controller that CPU has relinquished the control of buses and
thus, DMA can take control of the control buses to directly transfer data
between memory and peripheral device. Once the control is taken, DMA
can transfer data either by cycle stealing or doing a burst transfer. Both
the techniques are explained below.
‹ ‹Burst Transfer: In this type of transfer, DMA will return the bus
control to the CPU after transferring the specified number of bytes
of data. A register is used as a byte count. After transferring every
byte, the value of the byte count register is decremented. Once the
value of byte count register becomes zero, the DMA Controller will
release the control of the buses so that CPU can take their control
and perform its operations. Note that while DMA transfer was being
done, the CPU was halted. Now that the data transfer is complete,
CPU can resume its operations.
‹ ‹Cyclic Stealing: In this method, the DMA controller transfers one
word at a time. After transferring a word, it returns the control
of the buses to the CPU. The advantage of this method is that
it delays CPU operations only for one memory cycle. Hence the
name. In this technique, DMA steals one memory cycle from CPU
to transfer data.
DMA Controller
A DMA (Direct Memory Access) controller as shown in Figure 6.11 is a
peripheral device in a computer system that allows data to be transferred
between peripheral devices and memory without involving the CPU. When
a peripheral device needs to transfer data to or from memory, it sends a
request to the DMA controller. If multiple devices are requesting DMA
access, the DMA controller determines the priority of the controller and
gives it access as per its priority.
Once granted access, the DMA controller takes control of the system bus
and transfers data directly between the peripheral device and memory,
bypassing the CPU. DMA controllers are particularly useful for high-speed

124 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 124 12-09-2024 17:25:42

 Input Output Organization

data transfer operations because they offload the CPU from managing Notes
the data transfer, allowing it to focus on other tasks. As discussed, DMA
controllers can operate in different modes, including:
Single Transfer Mode: One-time data transfer between a peripheral
device and memory.
Block Transfer Mode: Multiple blocks of data are transferred between
the peripheral device and memory.
Burst Transfer Mode: Multiple data words are transferred in rapid suc-
cession without releasing the bus between transfers.
DMA controllers have multiple channels to facilitate multiple data trans-
fers simultaneously. Each channel typically has its own set of registers
and control logic. Some DMA controllers also include buffer memory
to temporarily store data during transfers. This ensures smooth transfer
between the peripheral device and memory.

Figure 6.11: Block Diagram of DMA Controller

The process of DMA data transfer operation is illustrated in Figure 6.12.

PAGE 125
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 125 12-09-2024 17:25:42

 COMPUTER SYSTEM ARCHITECTURE

Notes

Figure 6.12
Advantages of DMA Controller
‹ ‹It speeds up data transfer.
‹ ‹CPU need not intervene in data transfer process, releasing CPU for
other important tasks.
‹ ‹Data transfer is completed in fewer clock cycles.
‹ ‹DMA distributes workload very appropriately.
Disadvantages of DMA Controller
‹ ‹DMA is expensive because of additional operations.
‹ ‹DMA suffers from Cache-Coherence Problems.
‹ ‹Complexity of the system increases because of DMA.
IN-TEXT QUESTIONS
5. In the ________, the interface is commanded to send out an
interrupt request signal whenever data is available from IO
device
6. The CPU is not in use and has no control over the memory
buses during ________ operation.
7. The ________ signal requests the DMA controller to ask the
CPU to relinquish the control buses.
126 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 126 12-09-2024 17:25:42

 Input Output Organization

8. Multiple blocks of data are transferred between the peripheral Notes

device and memory in the ________ mode.
9. DMA controllers have multiple ________ to facilitate multiple
data transfers simultaneously.

6.13 Summary
‹ ‹An output device translates the digitized signals into a form that
can be read and interpreted by the user.
‹ ‹ASCII codes uses 7 bits to code 128 different characters.
‹ ‹I/O Interface helps to transfer information to and from the internal
storage and the external I/O devices.
‹ ‹Programmed I/O depends on how the computer program’s I/O
instructions are written.
‹ ‹In the interrupt initiated IO, the interface is commanded to send out
an interrupt request signal whenever data is available from IO device
‹ ‹The CPU is not in use and has no control over the memory buses
during DMA. In order to govern the direct transfer between the
memory unit and the I/O devices, the DMA controller assumes
control of the buses.

6.14 Answers to In-Text Questions

1. Computer organization
2. Output
3. 7
4. Internal, external
5. interrupt initiated IO
6. Direct Memory Access
7. Bus Request control
8. Block Transfer Mode
9. Channels

PAGE 127
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 127 12-09-2024 17:25:42

 COMPUTER SYSTEM ARCHITECTURE

Notes
6.15 Self-Assessment Questions
1. Explain any three peripheral devices.
2. What do you understand by /O BUS and Interface Module
3. How does Input - Output Interface work?
4. Differentiate between:
(a) I/O Bus and Memory Bus
(b) Isolated I/O Bus and Memory Mapped I/O Bus
5. Explain the mode of data transfer in Programmed I/O technique.
6. How is Interrupt-initiated I/O better than Programmed I/O?
7. Write a short note on DMA.

6.16 References
u Computer System Architecture by M. Morris Mano, Third edition,
1993, Prentice Hall of India.
u Computer System Architecture by M. Morris Mano, Third edition,
1993, Pearson Education.

6.17 Suggested Readings

u John P Hayes “Computer Architecture and organization” McGraw
Hill.
u Dezso Sima,Terence Fountain and Peter Kacsuk “Advanced Computer
Architecture” Pearson Education.
u Kai Hwang “Advanced Computer Architecture” TMH.
u Linda Null, Julia Lobur-The Essentials of Computer Organization
and Architecture, 2014, 4th Edition.
u H&P3: Hennessy, J. L., and D. A. Patterson. Computer Architecture:
A Quantitative Approach, 3rd ed. San Mateo, CA: Morgan Kaufman,
2002. ISBN: 1558605967.

128 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 128 12-09-2024 17:25:43

 Input Output Organization

u H&P2: Hennessy, J. L., and D. A. Patterson. Computer Architecture: Notes

A Quantitative Approach, 2nd ed. San Mateo, CA: Morgan Kaufman,
1995. ISBN: 1558603727.
u P&H: Patterson, D. A., and J. L. Hennessy. Computer Organization
and Design: The Hardware/Software Interface, 3rd ed. San Mateo,
CA: Morgan Kaufman, 2004. ISBN: 1558606041.

PAGE 129
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 129 12-09-2024 17:25:43

Computer System Architecture.indd 130 12-09-2024 17:25:43
 Glossary

Addressing Mode: Computers can use the address field and the mode field of the instruc-
tion to compute the effective address of the operand in multiple ways. These different
ways are termed as addressing modes.
Base (or Radix): The number of unique digits, including zero, used to represent numbers
in a positional numeral system. Examples include base-10 (decimal), base-2 (binary), base-8
(octal), and base-16 (hexadecimal).
Binary-Coded Decimal (BCD): A binary-encoded representation of integer values that
uses a 4-bit binary number to represent each digit of a decimal number.
Binary Number System (Base-2): A numeral system that uses only two digits, 0 and 1.
It is the foundational number system for digital electronics and computing.
Block Transfer Mode: Multiple blocks of data are transferred between the peripheral
device and memory.
Boolean Algebra: Boolean algebra is introduced as a mathematical framework for analyz-
ing and designing digital circuits. It operates with binary variables and logical operations.
Burst Transfer: In this type of transfer, DMA will return the bus control to the CPU after
transferring the specified number of bytes of data.
Burst Transfer Mode: Multiple data words are transferred in rapid succession without
releasing the bus between transfers.
Combinational Circuits: Output depends solely on current inputs; used in arithmetic
operations and data routing.
Computer Organization: It refers to operational units and their interconnections that
conform to the architecture specifications.
Cyclic Stealing: In this method, the DMA controller transfers one word at a time. After
transferring a word, it returns the control of the buses to the CPU.
Decimal Number System (Base-10): The most used number system, which uses ten digits
from 0 to 9.
Decoders: A device that converts binary information from the n coded inputs to a max-
imum of 2n unique outputs.

PAGE 131
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 131 12-09-2024 17:25:43

 COMPUTER SYSTEM ARCHITECTURE

Notes Digit: A symbol used to represent numbers in each number system. For
example, in the decimal system, digits are 0 through 9.
Digital vs. Analog Systems: Digital systems use discrete values (usually
binary) to represent information, while analog systems use continuous
values. Advantages of digital systems include noise immunity, ease of
design, and accuracy.
Direct Memory Access Controller: A peripheral device in a computer
system that allows data to be transferred between peripheral devices and
memory without involving the CPU.
Direct Operand: Is an operand that is stored in the register or in the
memory location specified.
Effective Address: The location or the memory address of the operand
of the instruction.
Encoders: A device that converts information from 2 n inputs into an
n-bit code.
Flip-Flops: Basic memory elements used to store a single bit; fundamen-
tal in constructing more complex memory and sequential logic circuits.
Hexadecimal Number System (Base-16): A numeral system that uses
sixteen symbols: 0-9 and A-F, where A represents 10, B represents 11,
up to F which represents 15.
Immediate Operand: Is an operand whose value is directly specified
in the instruction.
Indirect Operand: Is an operand whose address is either stored in the
register or in the memory location specified.
Instruction Codes: An instruction code is a group of bits that instruct
the computer to perform a specific task.
K-map: Karnaugh Maps are a powerful tool for simplifying Boolean
expressions in digital logic design. They provide a visual method for
minimizing logic functions, making it easier to design efficient digital
circuits.
Logic Gates: Logic gates are the building blocks of digital circuits. Basic
gates include AND, OR, NOT, NAND, NOR, XOR, and XNOR.
Multiplexers (MUX): Selects one of several input signals and forwards
the selected input to a single output line.

132 PAGE
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 132 12-09-2024 17:25:43

 Glossary

Octal Number System (Base-8): A numeral system that uses eight digits, Notes
from 0 to 7.
Operand: An instruction also specifies the data or the operands on which
the operation will be performed. The operand may be a CPU registers
and/or a memory addresses.
Operation Code: It is a group of bits that specifies the operation that
needs to be performed. Operation can be addition, subtraction, shift,
complement, etc.
Overflow: A condition where a calculation exceeds the maximum limit
of the number system used. For instance, in an 8-bit system, any value
above 255 causes an overflow.
Program: A program is a set of instructions that specify the operations,
operands and the sequence in which data has to be processed.
Program Counter: A program counter is a special CPU register that
stores the memory address (location) of the next program instruction to
be executed.
RAM (Random Access Memory): Volatile memory used for temporary
storage while a computer is running.
ROM (Read-Only Memory): Non-volatile memory used to store firm-
ware or software that is rarely changed.
Sequential Circuits: Output depends on current inputs and past states;
used in counters, registers, and control units.
Sign-Magnitude Representation: A method of representing signed
numbers where the most significant bit (MSB) represents the sign (0 for
positive, 1 for negative) and the remaining bits represent the magnitude.
Single Transfer Mode: One-time data transfer between a peripheral
device and memory.

PAGE 133
Department of Distance & Continuing Education, Campus of Open Learning,
School of Open Learning, University of Delhi

Computer System Architecture.indd 133 12-09-2024 17:25:43

Computer System Architecture.indd 134 12-09-2024 17:25:43