Puc2024 Lecture11 RDL

The document outlines a course on Programmable Digital Circuits, covering topics such as HDL synthesis, hardware description, SoC project architecture, and register description language (RDL). It introduces RDL as a specialized language for defining register structures and behaviors, along with the PeakRDL toolchain for generating control and status register code. Additionally, it discusses various RDL component types and provides examples of generating RDL source files and documentation.

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Puc2024 Lecture11 RDL

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Programmable Digital Circuits

Dr. Eng. Piotr Kurgan

Department of Microelectronic Systems

Faculty of Electronics, Telecommunications and Informatics
Lecture Outline
• Course organization
• Repetition of HDL synthesis (Verilog & SystemVerilog)
• Hardware description (ZYBO Z7 Development Board)
• SoC project architecture
• AXI interface
• Register Description Language
• Work setup/environment
• Petalinux build & configuration
• SVUnit framework in QuestaSim
• Hardware debugging & chipscope
• Outline of laboratory projects. Implementation topics
RDL and PeakRDL
• Register Description Language (RDL) is a specialized language used to describe
registers in hardware design
• RDL allows to define structure, behavior, and access policies of registers in HW
design
• RDL is used for ensuring consistency and to eliminate risk of errors
• PeakRDL is an open-source toolchain for generating control and status register code
(CSR code)

SystemRDL reference: https://peakrdl.readthedocs.io/en/latest/index.html

RDL Component Types
• SystemRDL address map description components:
• field: lowest-level SystemRDL component. Describes behavior of bit collection
within a register. Permits assignment of multiple properties.
• reg: container definition for one or more fields. Accesible by software (SW) at
a given address.
• regfile: logical grouping of registers or additional register files. Convenient
mechanism for grouping conceptually-related registers.
• addrmap: grouping that implies physical boundary in implementation.
• signal: provides a mechanism to define additional inputs to register map.
• mem: represents an array of storage elements. Registers can be optionally
instantiated in memory to imply structure.
Baseline Project Overview
• Baseline project directory tree
RDL Baseline Example
RDL: Other Examples
Generating RDL Source Files
• Command (executed from ~/puc-lab/fpga):

• Result:
Generating RDL Source Files: Results
• Command:

• Result:
Generating RDL Source Files: Results #2
Generating RDL Source Files: Results #3
Generating RDL Source Files: Results
• HTML Documentation
• Command: peakrdl html ./src/registers.rdl ./src/html/
Generating RDL Source Files: Results #2
• HTML Documentation
Working With Registers
• Petalinux on Zynq-7000 (USB Serial Port COM)
System Overview

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Puc2024 Lecture11 RDL

Uploaded by

Puc2024 Lecture11 RDL

Uploaded by

Programmable Digital Circuits

Dr. Eng. Piotr Kurgan

Department of Microelectronic Systems

SystemRDL reference: https://peakrdl.readthedocs.io/en/latest/index.html

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