FREQUENTLY ASKED I2C

INTERVIEW QUESTIONS YOU

SHOULD KNOW !!

INTERVIEW QUESTIONS
PROJECT IMPLEMENTATION

Prasanthi Chanda
1. How would you implement clock stretching in an
I2C slave controller in Verilog?
Clock stretching involves the slave holding the SCL line low when it needs
more time to process data.
Use a signal in the slave's FSM to pull SCL low.
KEY CONCEPT: The SCL signal is driven low by the slave's control logic until it is
ready to continue communication.
IMPLEMENTATION EXAMPLE:
always @(posedge clk or posedge reset) begin
if (reset) scl_out <= 1; // Default state
else if (need_more_time) scl_out <= 0; // Hold SCL low
else scl_out <= 1; // Release SCL
end

2. Write a Verilog module for generating START and

STOP conditions in I2C.
module i2c_start_stop(clk, reset,start,stop,sda,scl);
input clk, reset, start, stop;
output reg sda;
output reg scl;

always @(posedge clk or posedge reset) begin

if (reset) begin
sda <= 1; // Default idle state
scl <= 1;
end else if (start) begin
sda <= 0; // START: SDA goes low while SCL is high
end else if (stop) begin
sda <= 1; // STOP: SDA goes high while SCL is high
end
end
endmodule
3. How would you handle bus arbitration in an I2C
controller in hardware?
ARBITRATION LOGIC:
Monitor SDA while driving SCL.
If the master detects a mismatch between the driven SDA and observed
SDA, it loses arbitration and stops transmission.
IMPLEMENTATION EXAMPLE:
always @(posedge clk) begin
if (sda_drive != sda_read) begin
arbitration_lost <= 1;
end else begin
arbitration_lost <= 0;
end
end

4. Write a Verilog module for handling an ACK signal in

an I2C slave.
module i2c_ack(clk, reset, sda_in, ack);
input clk, reset, sda_in;
output reg ack;

always @(posedge clk or posedge reset) begin

if (reset) begin
ack <= 0;
end else if (sda_in == 0) begin
ack <= 1; // ACK received
end else begin
ack <= 0; // No ACK
end
end
endmodule
5. How do you handle multi-master contention in an
I2C bus in VLSI design?
Multi-master contention is resolved by the arbitration mechanism defined
in the I2C protocol:
Each master monitors the SDA line while driving it.
If a master writes a 1 but observes a 0, it loses arbitration and halts
transmission.
DESIGN STEPS IN VERILOG:
Add logic to monitor the SDA line and include an arbitration flag to
indicate whether the master has lost control.
IMPLEMENTATION EXAMPLE:
always @(posedge clk) begin
if (sda_drive == 1 && sda_read == 0) begin
arbitration_lost <= 1; // Master lost arbitration
end else begin
arbitration_lost <= 0;
end
end

6. How would you design an I2C timing analyzer in a

VLSI testbench?
Measure the timing parameters such as tSU (setup time), tHD (hold time),
and tLOW (SCL low time).
Use assertions to check if the timing matches I2C specifications.
IMPLEMENTATION EXAMPLE:
initial begin
$monitor("tSU=%d, tHD=%d, tLOW=%d", tSU, tHD, tLOW);
end
// Check setup time
always @(posedge scl) begin
assert((sda_change_time - scl_rise_time) > tSU_spec)
else $error("Setup time violation");
end
7. How would you implement a clock stretching feature
in an I2C slave controller using Verilog?
In clock stretching, the slave pulls the SCL line low until it is ready to
continue.
The SCL signal is held low by the slave's control logic when the busy flag
is active.
IMPLEMENTATION EXAMPLE:
module i2c_clock_stretch(clk, reset, busy, scl);
input clk, reset, busy;
output reg scl;
always @(posedge clk or posedge reset) begin
if (reset) scl <= 1;
else if (busy) scl <= 0; // Stretch clock
else scl <= 1; // Release clock
end
endmodule

8. How do you implement an address match

detector in an I2C slave?
Compare the received 7-bit address with the slave's assigned address.
Generate an ack signal if they match.
IMPLEMENTATION EXAMPLE:
module i2c_address_match(
input [6:0] slave_address,
input [6:0] received_address,
output reg ack
);
always @(*) begin
if (slave_address == received_address) ack = 1;
else ack = 0;
end
endmodule
9. How do you implement a START condition detector
in an I2C slave?
A START condition occurs when SDA transitions from high to low while
SCL is high.
Detect this using edge detection logic.
IMPLEMENTATION EXAMPLE:
module i2c_start_detect(clk, reset, sda, scl, start_detected);
input clk, reset, sda, scl;
output reg start_detected;

reg sda_prev;
always @(posedge clk or posedge reset) begin
if (reset) begin
sda_prev <= 1;
start_detected <= 0;
end else begin
if (scl == 1 && sda_prev == 1 && sda == 0) begin
start_detected <= 1; // START condition detected
end else begin
start_detected <= 0;
end
sda_prev <= sda;
end
end
endmodule
10. How do you implement a glitch filter for I2C
signals in hardware?
Use a shift register to filter out glitches shorter than a specific time.
Only consider SDA/SCL stable when their value is consistent over multiple
clock cycles.
IMPLEMENTATION EXAMPLE :
module glitch_filter(clk, reset, sda_in, sda_out);
input clk, reset, sda_in;
output reg sda_out;

reg [2:0] sda_shift;

always @(posedge clk or posedge reset) begin
if (reset) sda_shift <= 3'b111;
else sda_shift <= {sda_shift[1:0], sda_in};
if (sda_shift == 3'b111) sda_out <= 1; // Stable high
else if (sda_shift == 3'b000) sda_out <= 0; // Stable low
end
endmodule

11. How do you optimize an I2C controller for low-

power VLSI design?
Use clock gating to disable unused clock domains.
Use dynamic voltage scaling for power optimization.
Disable the I2C peripheral when idle using a sleep mode.
IMPLEMENTATION EXAMPLE :
module clock_gating(clk, enable, gated_clk);
input clk, enable;
output reg gated_clk;

always @(posedge clk) begin

if (enable) gated_clk <= clk;
else gated_clk <= 0;
end
endmodule
12. How would you handle clock domain crossing (CDC)
issues in an I2C controller?
Use synchronizers to safely transfer signals between asynchronous clock
domains.
EXAMPLE: Use two-stage flip-flops for metastability resolution.
IMPLEMENTATION EXAMPLE :
module cdc_sync( clk_dest, signal_src, signal_dest);
input clk_dest, signal_src;
output reg signal_dest;

reg sync1;
always @(posedge clk_dest) begin
sync1 <= signal_src;
signal_dest <= sync1;
end
endmodule

13. How do you simulate bus contention in an I2C

design?
In a testbench, simulate multiple masters attempting to drive the SDA line
simultaneously.
Verify that arbitration resolves the contention correctly.
IMPLEMENTATION EXAMPLE :
assign sda = (master1_drive) ? master1_data : 1'bz; // Master 1
assign sda = (master2_drive) ? master2_data : 1'bz; // Master 2
// Arbitration Check
always @(posedge clk) begin
if (master1_drive && master2_drive && (master1_data != master2_data))
begin
$display("Bus contention detected");
end
end
14. How would you implement an I2C slave controller
that supports multiple data rates?
Use a configurable divider to derive different clock rates for Standard
(100 kHz), Fast (400 kHz), or Fast-Plus (1 MHz) modes.
IMPLEMENTATION EXAMPLE:
module i2c_clock_divider(
input clk,
input [1:0] mode, // 00: Standard, 01: Fast, 10: Fast-Plus
output reg clk_out
);
reg [15:0] counter;
reg [15:0] threshold;

always @(*) begin

case (mode)
2'b00: threshold = 500; // 100 kHz
2'b01: threshold = 125; // 400 kHz
2'b10: threshold = 50; // 1 MHz
default: threshold = 500;
endcase
end

always @(posedge clk) begin

counter <= (counter == threshold) ? 0 : counter + 1;
clk_out <= (counter == 0) ? ~clk_out : clk_out;
end
endmodule
15. How would you design an I2C slave with error
detection and correction for data transmission in a
VLSI system?
To ensure data reliability, implement error detection using a Cyclic
Redundancy Check (CRC) or Parity Bits. Add error correction logic to
detect and correct single-bit errors.
IMPLEMENTATION STEPS:
Append a parity bit or CRC code to the data frame.
Check the received data's integrity by recalculating the CRC or parity at
the slave side.
If an error is detected, signal the master using an ACK/NACK response or
an error flag.
IMPLEMENTATION EXAMPLE:
module i2c_slave_error_detection(
input [7:0] received_data,
input [3:0] received_crc,
output reg error_detected
);
wire [3:0] calculated_crc;

// Simple CRC generator logic

assign calculated_crc = (received_data[7:4] ^ received_data[3:0]);

always @(*) begin

if (calculated_crc != received_crc) error_detected = 1;
else error_detected = 0;
end
endmodule
 PROJECT OVERVIEW
This project presents a comprehensive VLSI implementation of the
I2C Protocol. It includes the design of both master and slave
controllers, supporting essential features such as data transmission,
clock generation, error detection, and multi-master arbitration. The
implementation ensures low power consumption, error-free data
communication with CRC checks, and handling of clock stretching.
KEY COMPONENTS OF THE PROJECT:
Verilog code for I2C master and slave modules.
Testbenches for simulation and verification.
Clock generation and power management techniques.
Error detection and correction using CRC and parity.
Multi-master arbitration logic.
CONTACT INFORMATION :
For the source code, implementation details, or additional support,
please contact:
ProV Logic
Email : elearn@provlogic.com
Phone : +91 91822 80927
LinkedIn : @ProV Logic

I hope this document has provided valuable insights into the design and
functionality of I2C communication in hardware. If you have any
questions, need the source code, or wish to discuss further details, feel
free to contact me. I look forward to any feedback or collaboration
opportunities.