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LOGIC DIAGRAM:

BLOCK DIAGRAM:

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Date:10/2/25

EXPERIMENT-6
FIBONACCI SERIES
AIM: To design and verify Fibonacci Sequence Generator on FPGA

TOOLS USED:

1. Vivado Tool
2. Vivado Simulator
3. NEXYS4 DDR

THEORY:

The Fibonacci series is a sequence of numbers where each number is the sum of the two
preceding ones. It usually starts with 0 and 1. The series goes like this: 0, 1, 1, 2, 3, 5, 8, 13, 21,
34, and so on. Mathematically, it is defined by the recurrence relation: F(n) = F(n-1) + F(n-2)
with the initial conditions: F(0) = 0, F(1) = 1

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ELABORATED SCHEMATIC DESIGN:

SYNTHESIZED SCHEMATIC DESIGN:

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PROCEDURE:
1. In the open terminal, enter “source /home/install/Xilinx/Xilinx.bashrc” and press
Enter.
2. Then, enter “Vivado &” in the open terminal.
3. Click on "Create Project." A window will pop up. Click "Next," then "Next" again,
and once more "Next." Click on "Create File."
4. Enter the file name, click "Ok," and then click "Next."
5. Select the board part “xc7a100tcsg324-1,” double-click on it, and then click "Finish."
6. Click "Ok" and then "Next" in the popped window.
7. To add more source files, click on the plus symbol to add or create design sources,
then click "Next" and "Finish."
8. In the editor window, develop the code for execution.

9. Set the tb_file as the top priority, then click on "Run Simulation" -> "Run Behavioural
Simulation" to obtain the waveform.

10. Go to "File," click on "Close Simulation," and then open "IP Integrator."

11.In IP Integrator, create block design -> click "Ok." (Here, the modules are dragged and
dropped into the new module, then connected. Later, make inputs external by right-
clicking with the mouse.) After validating the design, save the design.

12.Right-click on the design module, create an HDL Wrapper, and set it as the top priority.

13.Open the elaborated design, select I/O planning, apply inputs and outputs, save the
file, and select the schematic design.

14.Click on "Run Synthesis" -> "Open Synthesized Design."

15.In the synthesis block, select Schematic, Power, and Utilization Reports.

16. Click on "Generate Bit Stream" -> "Open Hardware Manager."

17.In Hardware Manager, select "Target" -> "Program Device" -> "Program."

18.Apply different inputs to obtain different outputs on the FPGA board.

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POWER REPORT:

UTILIZATION REPORT:

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PROGRAM:

module Fibonacci (input clk, rst, output [3:0] RegA, RegB, RegC);
// Registers to store the current and previous values of the fibonacci counter
reg [3:0] RegA, RegB, RegC;
always @ (posedge clk) begin
if (rst) begin
RegA<= 4'h1; // Start RegA with the second value of fibonacci series - '1'
RegB<= 4'h0; // Start RegB with the first value of fibonacci series - '0'
RegC<= 4'h0; // Reset RegC to '0'
end
else begin
RegA<= RegB [3] ? 4'h1 :RegA + RegB; // if RegB == 8, reset
RegA RegB<= RegB[3] ? 4'h0 :RegA; // if RegB == 8, reset
RegB RegC<= RegB; // RegC is a synchronization register
end
end
endmodule

module
seg_display( input clk,
input [3:0] digit_1,

input [3:0] digit_2,

input [3:0] digit_3,

reg [17:0] count_next;

reg [17:0] count_reg=0;

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CONSTRAINTS:
set_property IOSTANDARD LVCMOS33 [get_ports clk_0]
set_property IOSTANDARD LVCMOS33 [get_ports clk_1]
set_property IOSTANDARD LVCMOS33 [get_ports rst_0]
set_property IOSTANDARD LVCMOS33 [get_ports {anode_0[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {anode_0[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {anode_0[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {anode_0[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {anode_0[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {anode_0[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {anode_0[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {anode_0[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[0]}]
set_property PACKAGE_PIN E3 [get_ports clk_0]
set_property PACKAGE_PIN J15 [get_ports clk_1]
set_property PACKAGE_PIN L16 [get_ports rst_0]
set_property PACKAGE_PIN U13 [get_ports {anode_0[7]}]
set_property PACKAGE_PIN K2 [get_ports {anode_0[6]}]
set_property PACKAGE_PIN T14 [get_ports {anode_0[5]}]
set_property PACKAGE_PIN P14 [get_ports {anode_0[4]}]
set_property PACKAGE_PIN J14 [get_ports {anode_0[3]}]
set_property PACKAGE_PIN T9 [get_ports {anode_0[2]}]
set_property PACKAGE_PIN J18 [get_ports {anode_0[1]}]
set_property PACKAGE_PIN J17 [get_ports {anode_0[0]}]
set_property PACKAGE_PIN T10 [get_ports {cathode_0[7]}]
set_property PACKAGE_PIN R10 [get_ports {cathode_0[6]}]
set_property PACKAGE_PIN K16 [get_ports {cathode_0[5]}]
set_property PACKAGE_PIN K13 [get_ports {cathode_0[4]}]
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 count_reg <=
count_next; always@(*)
count_next = count_reg + 1;

always@(*)
begin
case(count_reg[17:16])

2'b00:

begin

case(digit_1)

4'd0: cathode =
{7'b0000001,1'b1}; 4'd1: cathode
= {7'b1001111,1'b1}; 4'd2:
cathode = {7'b0010010,1'b1};
4'd3: cathode =
{7'b0000110,1'b1}; 4'd4: cathode
= {7'b1001100,1'b1}; 4'd5:
cathode = {7'b0100100,1'b1};
4'd6: cathode =
{7'b0100000,1'b1}; 4'd7: cathode
= {7'b0001111,1'b1}; 4'd8:
cathode = {7'b0000000,1'b1};
4'd9: cathode = {7'b0000100,1'b1};

endcase

anode =
8'b11111110; end
2'b01:

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begin

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set_property PACKAGE_PIN P15 [get_ports {cathode_0[3]}]
set_property PACKAGE_PIN T11 [get_ports {cathode_0[2]}]
set_property PACKAGE_PIN L18 [get_ports {cathode_0[1]}]
set_property PACKAGE_PIN H15 [get_ports {cathode_0[0]}]

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 case(digit_2)

4'd0: cathode =
{7'b0000001,1'b1}; 4'd1: cathode
= {7'b1001111,1'b1}; 4'd2:
cathode = {7'b0010010,1'b1};
4'd3: cathode =
{7'b0000110,1'b1}; 4'd4: cathode
= {7'b1001100,1'b1}; 4'd5:
cathode = {7'b0100100,1'b1};
4'd6: cathode =
{7'b0100000,1'b1}; 4'd7: cathode
= {7'b0001111,1'b1}; 4'd8:
cathode = {7'b0000000,1'b1};
4'd9: cathode =
{7'b0000100,1'b1};

endcase

anode =
8'b11111101; end
2'b10:

begin

case(digit_3)

4'd0: cathode =
{7'b0000001,1'b1}; 4'd1: cathode
= {7'b1001111,1'b1}; 4'd2:
cathode = {7'b0010010,1'b1};
4'd3: cathode =
{7'b0000110,1'b1}; 4'd4: cathode
= {7'b1001100,1'b1};
4'd5: cathode = {7'b0100100,1'b1};
4'd6: cathode = {7'b0100000,1'b1};
4'd7: cathode = {7'b0001111,1'b1};

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 4'd8: cathode = {7'b0000000,1'b1};
4'd9: cathode = {7'b0000100,1'b1};

endcase

anode = 8'b11111011;

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SIMULATION RESULT:

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 end
default:

begin

anode =
8'b11111111; end
endcase
end
endmodule

Test bench:

module Fibonacci_tb ();

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FPGA OUTPUT:

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RESULT: The Fibonacci series is designed using Verilog HDL. Simulation and FPGA
implementation is performed using Vivado tool. Functional verification of the design is
performed using a Verilog HDL test bench.

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