RISC vs CISC

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>20,000

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Architecture

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 Bus Interface Unit (BIU)

BIU fetches instructions, reads data from memory and I/O ports, writes data to
memory and I/ O ports.

Execution Unit (EU)

EU executes instructions that have already been fetched by the BIU.

BIU and EU functions separately.

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Register Organization of 8086

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8086 Microprocessor Architecture Execution Unit (EU)

EU Accumulator Register (AX)

Registers
Consists of two 8-bit registers AL and AH, which can be
combined together and used as a 16-bit register AX.

AL in this case contains the low order byte of the word,

and AH contains the high-order byte.

The I/O instructions use the AX or AL for inputting /

outputting 16 or 8 bit data to or from an I/O port.

Multiplication and Division instructions also use the AX or

AL.

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8086 Microprocessor Architecture Execution Unit (EU)

EU Base Register (BX)

Registers
Consists of two 8-bit registers BL and BH, which can be
combined together and used as a 16-bit register BX.

BL in this case contains the low-order byte of the word,

and BH contains the high-order byte.

This is the only general purpose register whose contents

can be used for addressing the 8086 memory.

All memory references utilizing this register content for

addressing use DS as the default segment register.

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8086 Microprocessor Architecture Execution Unit (EU)

EU Counter Register (CX)

Registers
Consists of two 8-bit registers CL and CH, which can be
combined together and used as a 16-bit register CX.

When combined, CL register contains the low order byte of

the word, and CH contains the high-order byte.

Instructions such as SHIFT, ROTATE and LOOP use the

contents of CX as a counter.
Example:

The instruction LOOP START automatically decrements

CX by 1 without affecting flags and will check if [CX] =
0.

If it is zero, 8086 executes the next instruction;

otherwise the 8086 branches to the label START.
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8086 Microprocessor Architecture Execution Unit (EU)

EU
Registers

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10
11
 8086 Microprocessor Architecture Execution Unit (EU)
Auxiliary Carry Flag Carry Flag
This is set, if there is a carry from the
Flag Register lowest nibble, i.e, bit three during
This flag is set, when there is a
carry out of MSB in case of
addition, or borrow for the lowest nibble, addition or a borrow in case of
i.e, bit three, during subtraction. subtraction.
Sign Flag Zero Flag Parity Flag
This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation the computation or comparison byte of the result contains even
is negative performed by an instruction is number of 1’s ; for odd number
zero of 1’s set to zero.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Over flow Flag Tarp Flag

This flag is set, if an overflow occurs, i.e, if the result of a signed If this flag is set, the processor enters
operation is large enough to accommodate in a destination register. The the single step execution mode by
result is of more than 7-bits in size in case of 8-bit signed operation and generating internal interrupts after
more than 15-bits in size in case of 16-bit sign operations, then the the execution of each instruction
overflow will be set.
Direction Flag Interrupt Flag
This is used by string manipulation instructions. If this flag bit is ‘0’, the Causes the 8086 to recognize external
string is processed beginning from the lowest address to the highest address, mask interrupts; clearing IF disables
i.e., auto incrementing mode. Otherwise, the string is processed from the these interrupts.
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highest address towards the lowest address, i.e., auto incrementing mode.
8086 Microprocessor Architecture

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Sl.No. Type Register width Name of register

1 General purpose register 16 bit AX, BX, CX, DX

8 bit AL, AH, BL, BH, CL, CH, DL, DH

2 Pointer register 16 bit SP, BP

3 Index register 16 bit SI, DI

4 Instruction Pointer 16 bit IP

5 Segment register 16 bit CS, DS, SS, ES

6 Flag (PSW) 16 bit Flag register

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8086 Microprocessor Architecture Registers and Special Functions

Register Name of the Register Special Function

AX 16-bit Accumulator Stores the 16-bit results of arithmetic and logic operations

AL 8-bit Accumulator Stores the 8-bit results of arithmetic and logic operations

BX Base register Used to hold base value in base addressing mode to access
memory data

CX Count Register Used to hold the count value in SHIFT, ROTATE and LOOP
instructions

DX Data Register Used to hold data for multiplication and division operations

SP Stack Pointer Used to hold the offset address of top stack memory

BP Base Pointer Used to hold the base value in base addressing using SS register to
access data from stack memory

SI Source Index Used to hold index value of source operand (data) for string
instructions

DI Data Index Used to hold the index value of destination operand (data) for
string operations 14
Types of addressing mode in 8086
1. Immediate addressing mode
2. Direct addressing mode
3. Register addressing mode
4. Register Indirect addressing mode
5. Indexed addressing mode
6. Register relative addressing mode
7. Base plus index addressing mode
8. Base relative plus index addressing mode
1: Immediate addressing mode

• In this type of mode, immediate data is part of instruction

and appears in the form of successive byte or bytes

10 ABH

MOV AX,10ABH AX
 2: Direct addressing mode

• In this type of addressing mode a 16-

bit memory address is directly specified
in the instruction as a part of it. Memory
22 5000
33 5001
MOV AX,[5000H] 5002

AX
3: Register addressing mode

• In this type of addressing mode, the data is

stored in the register and it can be a 8-bit or
16-bit register. All the registers, except IP, may
be used in this mode.
10 AB BX
MOV AL,BLH BH BL
MOV AX,BXH FF 33 AX
AH AL
4: Register Indirect addressing
mode
• The address of the memory location which contains data or
operand is determined in a indirect way, using the offset
register.
Memory
22 5000
AX
33 5001

MOV AX,[BX] 5002

BX
50 00
Reflection Spot
MOV [7000H],CX
Q) Which addressing does instruction above belong,
and why?
Reflection Spot
MOV [7000H],CX
Q) Which addressing does instruction above
belonging and why?
Memory
Ans) Direct addressing mode 22 7000

33 7001
7002

CX 43 56
5: Indexed addressing mode

• In this addressing mode, offset of the operand is stored in

one of the index registers. DS is the default segment for
index register SI and DI.
Memory
22 5000
AX
33 5001
MOV AX,[SI] 5002

50 00 SI
 6: Register relative addressing mode

• In this mode, the data is available at an effective address

formed by adding an 8-bit or 16-bit displacement with the
content of any one of the registers BX, BP, SI and DI in the
default (either DS or ES) segment.
Memory
44 5051
AX
33 5052

MOV AX, 50H[BX] 5053

50 00 + 50H = 5050H
Final
Index
BX Offset Address
7: Base plus index addressing mode

• In this mode the effective address is formed by adding

content of a base register (any one of BX or BP) to the
content of an index register (SI or DI). Default segment
register DS.
12 3000
AX
MOV AX, [BX] [SI] 34 3001
3002

10 00 + 20 00 = 3000H
Final
BX SI Index
Address
8: Base relative plus index addressing mode

• In the effective address is formed by adding an 8 or 16-bit

displacement with sum of contents of any one of the base
registers (BX or BP) and any one of the index registers, in a
default segment.
12 3050
MOV AX,50H[BX][SI] AX
34 3051
3052

50H + 10 00 20 00 = 3050H
Final
BX SI Index
Address
1
 Instruction Set of 8086
An instruction is a binary pattern designed
inside a microprocessor to perform a specific
function.
The entire group of instructions that a
microprocessor supports is called
Instruction Set.
8086 has more than 20,000 instructions.

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 Classification of Instruction Set
1. Data Move/Transfer Instructions
2. Arithmetic Instructions and Logical Instruction
3. Shift and Rotate Instruction
4. Branch and Loop Instruction
5. M/C control Instruction
6. Flag Manipulation Instructions
7. String Instructions

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1. Data Transfer Instructions

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 Data Transfer Instructions
 MOV Des, Src:
 It is used to copy the content of Src to Des
 Src operand can be register, memory location or immediate operand.
 Des can be register or memory operand.
 Both Src and Des cannot be memory location at the same time(except
for string instructions).
 Transferring immediate data to segment register is not possible i.e
 MOV DS, 5000H ; Not permitted
 MOV AX, 5000H
 MOV DS, AC
 E.g.:
 MOV CX, 037A H
 MOV AL, BL
 MOV BX, [0301 H] 5
 Data Transfer Instructions
 PUSH Operand:
 It pushes the operand into top of stack.
 E.g.: PUSH AX
 SP is decremented by 2
• POP Des:
 It pops the operand from top of stack to Des.
 Des can be a general purpose register, segment register (except CS)
or memory location.
 E.g.: POP AX
 SP is incremented by 2

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 Data Transfer Instructions

 XCHG Des, Src:

 This instruction exchanges Src with Des.
 It cannot exchange two memory locations directly.
 Immediate data is also not allowed in this instruction
 E.g.: XCHG DX, AX
 XCHG [5000h], AX

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 Data Transfer Instructions
 IN Accumulator, Port Address:
 It transfers the operand from specified port to accumulator
register.

 E.g.: IN AX, 0028 H

 OUT Port Address, Accumulator:

 It transfers the operand from accumulator to specified port.

 E.g.: OUT 0028 H, AX

DX is the only register (implicit) which is allowed to carry the port
address, if the port address is 16-bit
Ex. IN AX, DX OUT DX, AX

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 Data Transfer Instructions
 LEA Register, Src:

 It loads a 16-bit register with the offset address of the

data specified by the Src.

 E.g.: LEA BX, [DI]

 This instruction loads the contents of DI (offset) into
the BX register.
 LEA SI, ADR[BX] ; base relative address
Where ADR is a EA of Label

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 Data Transfer Instructions
 LAHF:
 It copies the lower byte of flag register to AH.
 SAHF:
 It copies the contents of AH to lower byte of flag register.
 PUSHF:
 Pushes flag register to top of stack. (first Upper byte,
then lower byte)
 POPF:
 Pops the stack top to flag register. (First lower byte, then
upper byte)

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1. Arithmetic And Logical
Instructions
 Arithmetic Instructions
 ADD Des, Src:
 It adds a byte to byte or a word to word.
 It effects AF, CF, OF, PF, SF, ZF flags.
 Both operands can’t be Memory locations
 E.g.:
 ADD AL, 74H
 ADD DX, AX
 ADD AX, [BX]; Reg indirect
 ADD 0100H; implicit AX

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 Arithmetic Instructions
ADC Des, Src:
 It adds the two operands with CF, which was set
by previous calculations.
 It effects AF, CF, OF, PF, SF, ZF flags.
 E.g.:
 ADC AL, 74H
 ADC DX, AX
 ADC AX, [BX]
 ADC 0100H

21-Nov-2010 [email protected] 13
 Arithmetic Instructions
 INC : Increment
 It will increment the content of specified reg./memloc. by 1.
 Here all the condition code flags are affected except CF
 Immediate data can’t be operand for this instruction
 Ex INC AX INC [BX] INC [5000H]
• DEC : Decrement
 It will decrement the content of specified reg./memloc. by 1.
 Here all the condition code flags are affected except CF
 Immediate data can’t be operand for this instruction
 Ex DEC AX DEC [BX] DEC [5000H]

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 Arithmetic Instructions
SUB Des, Src:
 Subtracts the src operand from destination operand and
result is left in des operand
 It subtracts a byte from byte or a word from word.
 It effects AF, CF, OF, PF, SF, ZF flags.
 For subtraction, CF acts as borrow flag.
 E.g.:
 SUB AL, 74H
 SUB DX, AX
 SUB AX, [BX]
 SUB 0100H 15
 Arithmetic Instructions
SBB Des, Src:
 It subtracts the two operands and also the
borrow, which was set by previous calculations.
 It effects AF, CF, OF, PF, SF, ZF flags.
 E.g.:
 SBB AL, 74H
 SBB DX, AX
 SBB AX, [BX]
 SBB 0100H

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 Arithmetic Instructions
 MUL Src:
 It is an unsigned multiplication instruction.
 It multiplies two bytes to produce a word or two words to
produce a double word.
 AX = AL * Src
 DX : AX = AX * Src
 MUL CX ; (DX)(AX)<-(AX)*(CX)
 This instruction assumes one of the operand in AL or AX.
 Src can be a register or memory location. And Flags-OF, CF
 Unused bits of destination register is always filled with sign bit
 IMUL Src:
 It is a signed multiplication instruction.

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 Arithmetic Instructions
 DIV Src:
 It is an unsigned division instruction.
 It divides word by byte or double word by word.
 The operand is stored in AX, divisor is Src and
the result is stored as:
 AH = remainder, AL = quotient (for word/byte)
 DX=remainder, AX=quotient (for D-word/word)

 IDIV Src:
 It is a signed division instruction.

21-Nov-2010 [email protected] 18
 Arithmetic Instructions
 CMP: compare

 This instruction compares the source operand, which may be

register/Memloc./immediate data with the destination operand
which may be in reg./Memloc.

 For comparison, it subtracts the source operand with

destination operand but doesn’t store any result.

 The flags are affected depending on the result of subtraction.

 If both the SrcOp & DestOp are same --- Z=1

 If SrcOp > DestOp then --CY=1 Else CY=0

 Ex CMP BX, 0100H CMP AX, BX CMP [5000H] 0100H

CMP BX, [SI]; reg indirect 19

 Arithmetic Instructions
 CBW (Convert Byte to Word):

 This instruction converts byte in AL to word in AX.

 The conversion is done by extending the sign bit of AL

throughout AH.

 CWD (Convert Word to Double Word):

 This instruction converts word in AX to double word in DX :

AX.

 The conversion is done by extending the sign bit of AX

throughout DX.

 NEG Src:

 It creates 2’s complement of a given number.

 That means, it changes the sign of a number. 20

 Logical Instructions
 NOT Src: (Logical Invert)
 It complements each bit of Src to produce 1’s complement of the
specified operand.
 The operand can be a register or memory location.
 e,.g NOT AX
 AND Des, Src: (Logical AND)
 It performs AND operation of Des and Src.
 Src can be immediate number, register or memory location.
 Des can be register or memory location.
 Both operands cannot be memory locations at the same time.
 CF and OF become zero after the operation.
 PF, SF and ZF are updated.
 AND AX, 0080H AND AX, BX AND [5000H], BX 21
 Logical Instructions
 OR Des, Src: (Logical OR)
 It performs OR operation of Des and Src.
 Src can be immediate number, register or memory
location.
 Des can be register or memory location.
 Both operands cannot be memory locations at the same
time.
 CF and OF become zero after the operation.
 PF, SF and ZF are updated.
 Ex.
OR AX, 0080H OR AX, BX OR [5000H], BX
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 Logical Instructions
 XOR Des, Src:
 It performs XOR operation of Des and Src.
 Src can be immediate number, register or memory
location.
 Des can be register or memory location.
 Both operands cannot be memory locations at the same
time.
 CF and OF become zero after the operation.
 PF, SF and ZF are updated.
 EX.
 XOR AX, 0080H XOR AX, BX XOR [5000H], BX
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 Logical Instructions

 TEST Des, Src:

 It performs AND operation of Des and Src. Result of this
AND operation not available for future use but Flags are
affected.
 Src can be immediate number, and src/Des can be
register or memory location.
 It is Non-Destructive And means Dest is not modified
only flags are affected.
 Both operands cannot be memory locations at the same
time.
 CF and OF become zero after the operation.
 PF, SF and ZF are updated.
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 3. Branch/Program Execution Transfer
Instructions
 These instructions cause change in the sequence of the
execution of instruction.
 This change can be a conditional or sometimes
unconditional.
 The conditions are represented by flags.

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 Branch Instructions
 CALL Des:
 This instruction is used to call a subroutine or function
or procedure.
 The address of next instruction after CALL is saved onto
stack.

 RET:
 It returns the control from procedure to calling program.
 Every CALL instruction should have a RET.

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 Branch Instructions
 JMP Des:
 This instruction is used for unconditional jump from
one place to another.

 Jxx Des (Conditional Jump):

 All the conditional jumps follow some conditional
statements or any instruction that affects the flag.

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 Conditional Jump Table
Mnemonic Meaning Jump Condition

JA Jump if Above CF = 0 and ZF = 0

JAE Jump if Above or Equal CF = 0

JB Jump if Below CF = 1

JBE Jump if Below or Equal CF = 1 or ZF = 1

JC Jump if Carry CF = 1

JE Jump if Equal ZF = 1

JNC Jump if Not Carry CF = 0

JNE Jump if Not Equal ZF = 0

JNZ Jump if Not Zero ZF = 0

JPE Jump if Parity Even PF = 1

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 Loop Instructions
 Loop Des:
 This is a looping instruction.
 The number of times looping is required is placed in the
CX register.
 With each iteration, the contents of CX are
decremented.
 ZF is checked whether to loop again or not.

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ASSUME: Assume Logical Segment Name
The ASSUME directive is used to inform
the as- semble, the names of the logicals
segments to be assumed for different
segments used in the program. In the
assembly language program, each
segment is given a name. For example, the
code segment may be given the name
CODE, data segment may be given the
name DATA etc. The statement ASSUME
CS: CODE directs the assembler that the
machine codes are available in a segment
named CODE, and hence the CS register
is to be loaded with the address (segment)
allotted by the operating system for the
label CODE, while loading.
 UNIT -V
Interrupts in 8086 Microprocessor

Interrupts

Definition: The meaning of ‘interrupts’ is to break the sequence of operation. While the CPU
is executing a program, on ‘interrupt’ breaks the normal sequence of execution of
instructions, diverts its execution to some other program called Interrupt Service Routine
(ISR).After executing ISR , the control is transferred back again to the main program.
Interrupt processing is an alternative to polling.

Need for Interrupt: Interrupts are particularly useful when interfacing I/O devices that
provide or require data at relatively low data transfer rate.

Types of Interrupts: There are two types of Interrupts in 8086. They

are: (i)Hardware Interrupts and
(ii)Software Interrupts

(i) Hardware Interrupts (External Interrupts). The Intel microprocessors support

hardware interrupts through:

 Two pins that allow interrupt requests, INTR and NMI

 One pin that acknowledges, INTA, the interrupt requested on

INTR. INTR and NMI
 INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled
using STI/CLI instructions or using more complicated method of updating the FLAGS
register with the help of the POPF instruction.

 When an interrupt occurs, the processor stores FLAGS register into stack, disables
further interrupts, fetches from the bus one byte representing interrupt type, and jumps
to interrupt processing routine address of which is stored in location 4 * <interrupt
type>. Interrupt processing routine should return with the IRET instruction.

 NMI is a non-maskable interrupt. Interrupt is processed in the same way as the

INTR interrupt. Interrupt type of the NMI is 2, i.e. the address of the NMI processing
routine is stored in location 0008h. This interrupt has higher priority than the maskable
interrupt.

 – Ex: NMI, INTR.

(ii) Software Interrupts (Internal Interrupts and Instructions) .Software interrupts can be
caused by:
 INT instruction - breakpoint interrupt. This is a type 3 interrupt.

 INT <interrupt number> instruction - any one interrupt from available 256 interrupts.

 INTO instruction - interrupt on overflow

 Single-step interrupt - generated if the TF flag is set. This is a type 1 interrupt. When
the CPU processes this interrupt it clears TF flag before calling the interrupt
processing routine.

 Processor exceptions: Divide Error (Type 0), Unused Opcode (type 6) and Escape
opcode (type 7).

 Software interrupt processing is the same as for the hardware interrupts.

 - Ex: INT n (Software Instructions)

 Control is provided through:

o IF and TF flag bits

o IRET and IRETD

Performance of Software Interrupts

1. It decrements SP by 2 and pushes the flag register on the stack.

2. Disables INTR by clearing the IF.
3. It resets the TF in the flag Register.
5. It decrements SP by 2 and pushes CS on the stack.
6. It decrements SP by 2 and pushes IP on the stack.
6. Fetch the ISR address from the interrupt vector table.

Interrupt Vector Table

Functions associated with INT00 to INT04

INT 00 (divide error)

 INT00 is invoked by the microprocessor whenever there is an attempt to divide a

number by zero.

 ISR is responsible for displaying the message “Divide Error” on the screen

INT 01

 For single stepping the trap flag must be 1

 After execution of each instruction, 8086 automatically jumps to 00004H to fetch 4

bytes for CS: IP of the ISR.

 The job of ISR is to dump the registers on to the screen

INT 02 (Non maskable Interrupt)

 When ever NMI pin of the 8086 is activated by a high signal (5v), the CPU Jumps
to physical memory location 00008 to fetch CS:IP of the ISR associated with NMI.

INT 03 (break point)

 A break point is used to examine the CPU and memory after the execution of a group
of Instructions.

 It is one byte instruction whereas other instructions of the form “INT nn” are 2
byte instructions.

INT 04 (Signed number overflow)

 There is an instruction associated with this INT 0 (interrupt on overflow).

 If INT 0 is placed after a signed number arithmetic as IMUL or ADD the CPU
will activate INT 04 if 0F = 1.
 In case where 0F = 0, the INT 0 is not executed but is bypassed and acts as a NOP.

Performance of Hardware Interrupts

 NMI : Non maskable interrupts - TYPE 2 Interrupt

 INTR : Interrupt request - Between 20H and FFH

Interrupt Priority Structure

Pins and signals
8086 Microprocessor Pins and Signals Common signals

AD0-AD15 (Bidirectional)
Address/Data bus
20 Address lines denoted as AD0-AD15 and
A16/S3, A17/S4, A18/S5, A19/S6. 16 Data Lines are
AD0-AD15.

Address and Data lines are separated by ALE

If ALE=1, It carries address in A0-A15, A16-
A19
If ALE=0, It carries data on D0-D15, Status
Lines S3, S4, S5 and S6.
S3 S4 Segment
0 0 ES
0 1 SS
1 0 CS
1 1 DS

S5- reflects to Interrupt Enable flag

2
S6- Always 0, S7- Always 1
8086 Microprocessor Pins and Signals Common signals

BHE (Active Low)/S7 (Output)

Bus High Enable/Status

It is used to enable data onto the most

significant half of data bus, D8-D15. 8-bit device
connected to upper half of the data bus use BHE
(Active Low) signal. It is multiplexed with
status signal S7.

MN/ MX

MINIMUM / MAXIMUM

This pin signal indicates what mode the

processor is to operate in.

3
8086 Microprocessor Pins and Signals Common signals

READY
1-No effect on microprocessor operation
0-8086 enters in to wait state like idle
state, to synchronize with slow
peripheral devices

RD (Read) (Active Low)

The signal is used for read operation.
It is an output signal.
It is active when low. 4
8086 Microprocessor Pins and Signals Common signals

RESET (Input)

Microprocessor can reset by setting logic 1, It

resets CS:IP and registers to zero

CLK
The clock input provides the basic timing for
processor operation and bus control activity.

INTR Interrupt Request

This is level triggered input. If any interrupt

request is pending, the processor enters the
interrupt acknowledge cycle.

This signal is active high and internally

synchronized.

NMI-Non-Maskable Interrupt
It is a edge triggered and is type-2 interrupt
5
8086 Microprocessor Pins and Signals Min/ Max Pins

The 8086 microprocessor can work in two modes

of operations : Minimum mode and Maximum
mode.

In the minimum mode of operation the

microprocessor do not associate with any co-
processors and can not be used for
multiprocessor systems.

In the maximum mode the 8086 can work in multi-

processor or co-processor configuration.

Minimum or maximum mode operations are

decided by the pin MN/ MX(Active low).

When this pin is high 8086 operates in minimum

mode otherwise it operates in Maximum mode.

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8086 Microprocessor Pins and Signals Minimum mode signals

(Data Transmit/ Receive) Output signal from the processor to

control the direction of data flow through the data transceivers

(Data Enable) Output signal from the processor used as out put
enable for the transceivers

Used to differentiate memory access and I/O access. For memory

reference instructions, it is high. For IN and OUT instructions, it is
low.

Write control signal; asserted low Whenever processor writes data

to memory or I/O port

(Interrupt Acknowledge) When the interrupt request is accepted by

the processor, the output is low on this line.

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8086 Microprocessor Pins and Signals Minimum mode signals

HOLD Input signal to the processor form the bus masters

as a request to grant the control of the bus.

Usually used by the DMA controller to get the

control of the bus.

HLDA (Hold Acknowledge) Acknowledge signal by the

processor to the bus master requesting the control
of the bus through HOLD.

The acknowledge is asserted high, when the

processor accepts HOLD.

DMA Operation Without depend on processor for

data transmission between memory and I/O
Devices 8
8086 Microprocessor Pins and Signals Maximum mode signals

9
8086 Microprocessor Pins and Signals Maximum mode signals

Status signals; used by the 8086 bus controller to generate bus

timing and control signals. These are decoded as shown.

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8086 Microprocessor Pins and Signals Maximum mode signals

(Queue Status) The processor provides the status of queue in these

lines.

The queue status can be used by external device to track the

internal status of the queue in 8086.

The output on QS0 and QS1 can be interpreted as shown in the table.

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8086 Microprocessor Memory organization in 8086

12
8086 Microprocessor Memory organization in 8086
Operation A0 Data Lines Used

1 Read/ Write byte at an 1 0 D7 – D0

even address
2 Read/ Write byte at an 0 1 D15 – D8
odd address

_SDATA SEGMENT In this data segment, effective

Assembler ORG 1200H address of memory location assigned
Directive: A DB 4CH to A will be 1200H and that of B will be
EVEN EVEN 1202H and 1203H.
B DW 1052H
_SDATA ENDS

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Stack Structure of 8086 Microprocessor