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S24CSEU0117 Assignment4

The document contains a lab assignment by Aviral Srivastava, detailing the conversion of decimal numbers to binary, Gray code, BCD, and Ex-3 formats. It includes classifications of binary codes, Verilog code implementations for binary to Ex-3 conversion, Boolean expressions, and Gray to binary conversion, along with their respective testbenches. Each section provides code examples and test cases to demonstrate functionality.

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6 views8 pages

S24CSEU0117 Assignment4

The document contains a lab assignment by Aviral Srivastava, detailing the conversion of decimal numbers to binary, Gray code, BCD, and Ex-3 formats. It includes classifications of binary codes, Verilog code implementations for binary to Ex-3 conversion, Boolean expressions, and Gray to binary conversion, along with their respective testbenches. Each section provides code examples and test cases to demonstrate functionality.

Uploaded by

rathoredaksh25
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Name: Aviral Srivastava

Enrollment Number: S24CSEU0117

Lab Assignment 4:

Q1. Write the table for conversion of Decimal Numbers from (0-11) to its equivalent Binary, Gray,
BCD, and Ex-3.

Decimal Binary Gray Code BCD Ex-3

0 0000 0000 0000 0011

1 0001 0001 0001 0100

2 0010 0011 0010 0101

3 0011 0010 0011 0110

4 0100 0110 0100 0111

5 0101 0111 0101 1000

6 0110 0101 0110 1001

7 0111 0100 0111 1010

8 1000 1100 1000 1011

9 1001 1101 1001 1100

10 1010 1111 1010 1101

11 1011 1110 1011 1110

Q2. Write the classification of binary codes with appropriate examples.

Classification of Binary Codes:

1.​ Weighted Codes (e.g., BCD, Ex-3, 8421, 5211)


2.​ Non-weighted Codes (e.g., Gray Code, ASCII, Excess-3)
3.​ Error-detecting & Correcting Codes (e.g., Parity Codes, Hamming Code)
4.​ Alphanumeric Codes (e.g., ASCII, Unicode)
5.​ Self-complementary Codes (e.g., Excess-3)
Q3. Write a Verilog code to implement a 3-bit binary to Ex-3 code converter.

//Aviral_Srivastava

//S24CSEU0117

module q3 (input [2:0] bin, output [3:0] ex3);

assign ex3 = bin + 3;

endmodule

Testbench:

//Aviral_Srivastava

//S24CSEU0117

module tb_q3;

reg [2:0] bin;

wire [3:0] ex3;

q3 obj (.bin(bin), .ex3(ex3));

initial begin

bin = 3'b000; #10;

bin = 3'b001; #10;

bin = 3'b010; #10;

bin = 3'b011; #10;

bin = 3'b100; #10;

bin = 3'b101; #10;

bin = 3'b110; #10;


bin = 3'b111; #10;

$finish;

end

initial begin

$monitor("Time=%0t | bin=%b | ex3=%b", $time, bin, ex3);

end

endmodule

Q4. Write a Verilog code to implement the given Boolean expressions and its Testbench.

//Aviral_Srivastava

//S24CSEU0117

module q4 (input A, B, C, D ,output W, X, Y, Z);

assign W = A | (B & C) | (B & D);

assign X = (~B & C) | (~B & D) | (B & ~C & ~D);

assign Y = (C & D) | (~C | ~D);

assign Z = ~D;

endmodule

Testbench:

//Aviral_Srivastava

//S24CSEU0117

module tb_q4;
reg A, B, C, D;

wire W, X, Y, Z;

q4 obj (.A(A), .B(B), .C(C), .D(D), .W(W), .X(X), .Y(Y), .Z(Z));

initial begin

A = 0; B = 0; C=0; D=0;#10;

A = 0; B = 0; C=0; D=1;#10;

A = 0; B = 0; C=1; D=0;#10;

A = 0; B = 0; C=1; D=1;#10;

A = 0; B = 1; C=0; D=0;#10;

A = 0; B = 1; C=0; D=1;#10;

A = 0; B = 1; C=1; D=0;#10;

A = 0; B = 1; C=1; D=1;#10;

A = 1; B = 0; C=0; D=0;#10;

A = 1; B = 0; C=0; D=1;#10;

A = 1; B = 0; C=1; D=0;#10;

A = 1; B = 0; C=1; D=1;#10;

A = 1; B = 1; C=0; D=0;#10;

A = 1; B = 1; C=0; D=1;#10;

A = 1; B = 1; C=1; D=0;#10;

A = 1; B = 1; C=1; D=1;#10;

end
initial begin

$dumpfile("dump.vcd");

$dumpvars(1);

end

initial begin

$monitor("Time = %0t |A = %b, B = %b, C=%b, D=%b| W=%b, X=%b, Y =


%b, Z=%b", $time, A, B, C, D, W, X, Y, Z);

end

endmodule
Q5. Write a Verilog code to implement a 4-bit Gray to Binary code converter and its Testbench.

//Aviral_Srivastava

//S24CSEU0117

module q5 (input A, B, C, D ,output B1, B2, B3, B4);

assign B1 = A;

assign B2 = (~A & B) | (A & ~B);

assign B3 = (~B2 & C) | (B2 & ~C);

assign B4 = (~B3 & D) | (B3 & ~D);

endmodule

Testbench:

//Aviral_Srivastava

//S24CSEU0117

module tb_q5;

reg A, B, C, D;

wire B1, B2, B3, B4;

q5 obj (.A(A), .B(B), .C(C), .D(D), .B1(B1), .B2(B2), .B3(B3),


.B4(B4));
initial begin

A = 0; B = 0; C=0; D=0;#10;

A = 0; B = 0; C=0; D=1;#10;

A = 0; B = 0; C=1; D=0;#10;

A = 0; B = 0; C=1; D=1;#10;

A = 0; B = 1; C=0; D=0;#10;

A = 0; B = 1; C=0; D=1;#10;

A = 0; B = 1; C=1; D=0;#10;

A = 0; B = 1; C=1; D=1;#10;

A = 1; B = 0; C=0; D=0;#10;

A = 1; B = 0; C=0; D=1;#10;

A = 1; B = 0; C=1; D=0;#10;

A = 1; B = 0; C=1; D=1;#10;

A = 1; B = 1; C=0; D=0;#10;

A = 1; B = 1; C=0; D=1;#10;

A = 1; B = 1; C=1; D=0;#10;

A = 1; B = 1; C=1; D=1;#10;

end

initial begin

$dumpfile("dump.vcd");

$dumpvars(1);

end

initial begin
$monitor("Time = %0t |A = %b, B = %b, C=%b, D=%b| B1=%b, B2=%b, B3
= %b, B4=%b", $time, A, B, C, D, B1, B2, B3, B4);

end

endmodule

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