KS4 – Computer systems Lesson plan

Lesson 3 – The FDE cycle

Lesson 3: The FDE cycle

Introduction
In this lesson, the learners’ knowledge about the components that make up the CPU and
main memory will be furthered with the introduction of the fetch-decode-execute cycle
(FDE). Learners will be able to connect the parts of the CPU to their role in executing
instructions visually.

Learning objectives
● Explain how the fetch-decode-execute cycle works by describing what happens
at each stage
● Describe the role of each part of the CPU as part of the fetch-decode-execute
cycle

Key vocabulary
Fetch, decode, execute

Preparation
Subject knowledge:
You will need to have a clear understanding of how the FDE cycle works in order to
teach this lesson. To prepare, you could read this A level explanation to deepen your
understanding.

We would suggest that you practise using the LMC simulator before you try it with
learners. On this page https://www.101computing.net/LMC/ you can see some practise
exercises that you could use to familiarise yourself with assembly language and the FDE
cycle in action.

This simulator is slightly less abstract, as it has a control unit and ALU. There are sample
programs you can step through to see the FDE cycle using these parts of the CPU
http://www.peterhigginson.co.uk/AQA/

You will need:

Page 1 Last updated: 21/09/2021

KS4 – Computer systems Lesson plan
Lesson 3 – The FDE cycle

● Slides
● FDE jumble! - Activity 1 worksheet
● FDE jumble! - Activity 1 solutions
● Observing the FDE cycle: Activity 2 worksheet
● Question log: Plenary worksheet

Assessment opportunities
The ’Key components of the CPU’ activity is an opportunity to revisit terms from the last
lesson. The ‘High-level language’ activity will allow you to see if learners can sequence
the FDE correctly.

Outline plan
Please note that the slide deck labels the activities in the top right-hand corner to help
you navigate the lesson.

*Timings are rough guides

Page 2 Last updated: 21/09/2021

KS4 – Computer systems Lesson plan
Lesson 3 – The FDE cycle

Starter Key components of the CPU — retrieval practise

activity
(Slides 2–3) Display the roles of components of the CPU on the board. Instruct the
learners to write down the component by their description, without looking
5 mins back on old notes. You should then call on individual learners to provide
definitions.

There are animations on slide 3 to reveal each answer from the top down.

Activity 1 High-level language — recall activity

(Slide 5)
This lesson will focus on how the CPU works and executes instructions. In
10 mins order to activate your learners’ prior knowledge, you are going to have
them investigate a high-level program.

Project the high-level language to the class. You could use the animation to
hide the questions from the learners, or show the learners the questions at
the same time.

Questions and answers:

What is the purpose of this program?

To play the playground game ‘What’s the time Mr Wolf?’ (familiarity with
the game should reduce cognitive load).

On which line is a selection used?

Line 3.

What is the conditional test?

time ≠ “dinner time”

What is the operator used in the test?

Not equal to.

On what line is variable assignment used?

Line 2.

What type of loop is used in this program?

Condition-controlled loop (while).

What will output if the user types “Dinner Time”?

“Step forward” (the input is not identical as it uses upper case characters).

You could expand this activity by asking learners how they could improve
the program, ask them why ‘WHILE True’ could be a problem, etc.

Page 3 Last updated: 21/09/2021

KS4 – Computer systems Lesson plan
Lesson 3 – The FDE cycle

Activity 2 The fetch-decode-execute cycle jumble!

(Slides 6–11)
Introduce the FDE cycle and explain that this is how most modern
15 mins computers execute instructions. It is still a part of the von Neumann model
that you introduced in the previous lesson.

Give the learners an outline of each of the stages before they attempt a
jumble activity where they have to order the full step descriptions that
make up the cycle.

Start with fetch, and explain that all the instructions are loaded into RAM
(in order), before the program starts and any cycles have been completed.
The first stage is for an instruction to be grabbed from RAM and put in the
appropriate registers (more on this later). The instruction is then ready for
the next stages.

The control unit then decodes the instruction, reading the binary value and
figuring out which command it responds to. The mapping of binary to
commands will be different for every processor.

Finally, the instruction is executed and the control unit will send signals to
the other components that are required for the instruction.

The learners are then given the stages jumbled up (as a Parson’s Problem)
and have to order them correctly before colour coding as either fetch,
decode, or execute. You should then lead the learners through the correct
order and discuss/debate any other order presented by them.

Activity 3 Observing the FDE cycle

(Slides 12–
19) For this activity, you will demonstrate how to use the LMC simulator
https://www.101computing.net/LMC/ this is done in the following way:
20 mins 1. Using slide 12 as an illustration, or using the link above, talk through
the parts of the CPU and show a concrete example of the previously
theoretical concepts of RAM, buses, the CPU, and the clock speed
slider. Show the learners the registers and remind them what they
do.
2. Load up the ‘Add’ program from the box in the bottom left that is
labelled ‘SELECT’ — this will load an example program for you.
3. Then demonstrate the example program in the LMC. In a later
lesson, the learners will learn about assembly language, so in this
lesson you are just concentrating on the FDE.
4. To demonstrate, load the program into RAM and show how each
instruction takes up a different place in memory. You can point out
that the data value 1 is held in memory location 7, which links to this
being based on the von Neumann model in which both data and
instructions are stored in RAM. Step through the first instruction by

Page 4 Last updated: 21/09/2021

KS4 – Computer systems Lesson plan
Lesson 3 – The FDE cycle

using the single step arrow (right-hand red arrow). Point out the log
file that explains what has happened in the FDE cycle for that
instruction.

Instruct the learners to load the simulator and follow the instructions on
their worksheets, the questions on slide 13 are there for them to answer.

Note: Make sure they are using the ‘Adding 2 inputs’ program — it is
simpler and will allow them to focus on the cycle.

Once they have had time to record their observations, pull this class
together to provide answers for the exploration questions on slide 14.

Next the learners are going to step through the program and make notes
on what each component does in each stage of the cycle. They can use the
logs for this. Be aware that the ALU and control unit are not on this
simulator so they will need to use their prior learning to fill in those sections.
You can also use the other simulator —
http://www.peterhigginson.co.uk/AQA/ — to help them see what they are
doing.

Give them a few minutes to do this and then bring them back together to
show the answers using slides 16–19.

Use this as an opportunity to link back to the abstract concepts from

earlier to check they have grasped the concepts involved.

Particularly focus on the fact that both data and instructions are in RAM
and need to be fetched.

Plenary Revision question

(Slide 20)
As an exit ticket, ask each learner to write a question in their personal
5 mins question log. They should write a question with a single answer (no long-
form answers) on a component from today’s lesson.

Page 5 Last updated: 21/09/2021

KS4 – Computer systems Lesson plan
Lesson 3 – The FDE cycle

Resources are updated regularly — the latest version is available at: ncce.io/tcc.

This resource is licensed under the Open Government Licence, version 3. For more information on this
licence, see ncce.io/ogl.

Page 6 Last updated: 21/09/2021