Fall2005 2006quiz2
Fall2005 2006quiz2
SIGNATURE
2.5V
Q3 Q4
Q5
v1 Q1 Q2 v2 Q6
v OUT
I REF
Q9 Q 10 Q7 Q8
-2.5V
Figure 1
a) [5 points] How many stages are there? For each stage, identify the type of the
stage, the amplifier transistor(s) and the load transistor(s).
Assume in the following that k’n = 250 μA/V2, Vtn = 0.5 V, λn = 0.05 V–1, k’p = 100
μA/V2, Vtp = –0.6 V, and λp = 0.1 V–1.
Assume IREF = 100 μA, and that all MOSFETs have a (W/L) ratio equal to 20, except
for of Q5 which has (W/L) = 40.
b) [6 points] For each MOSFET, find the drain current and the overdrive voltage VOV
when V1 = V2 = 0. This condition (V1 = V2 = 0) results in VOUT = 0. Show your results
in the following format:
Since Q9 and Q10 are matched, this means that ID9 = ID10 = 100 uA. The current splits
equally in Q1 and Q2 since they are matched and have the same VGS (and channel
length modulation is being neglected). Therefore ID1 = ID2 = 50 uA. ID1 = ID3 and ID2 =
ID4 => ID3 = ID4 = 50 uA. The current in Q7 is 100 uA, since it is mirroring IREF. This
same current flows in Q5 => ID5 = ID7 = 100 uA. Same for Q6 and Q8: ID6 = ID8 = 100
uA.
VOV for the various MOSFETs is calculated from
2I D
I D = 12 k ' ( WL )VOV
2
⇒ VOV = where k’ is k’n for NMOS and k’p for PMOS. For
k ' ( WL )
PMOS transistors, VOV is negative. The table shown below also shows the value of
VGS of the transistors, and the values of gm and ro.
Lambda gm ro
k' (uA/V2) W/L VT (V) (1/V) ID (uA) VOV (V) VGS (V) (mA/V) (kOhm)
Q1 250 20 0.5 0.05 50 0.1414 0.6414 0.7071 400
Q2 250 20 0.5 0.05 50 0.1414 0.6414 0.7071 400
Q3 100 20 -0.6 0.1 50 -0.2236 -0.8236 0.4472 200
Q4 100 20 -0.6 0.1 50 -0.2236 -0.8236 0.4472 200
Q5 100 40 -0.6 0.1 100 -0.2236 -0.8236 0.8944 100
Q6 250 20 0.5 0.05 100 0.2 0.7 1 200
Q7 250 20 0.5 0.05 100 0.2 0.7 1 200
Q8 250 20 0.5 0.05 100 0.2 0.7 1 200
Q9 250 20 0.5 0.05 100 0.2 0.7 1 200
Q10 250 20 0.5 0.05 100 0.2 0.7 1 200
The total power dissipated in the circuit comes from the two supplies.
d) [7 points] Find the differential gain Ad = vout/(v1 – v2) by calculating vd2/(v1 – v2),
vd5/vd2, and vout/vd5.
The first stage gain is given by vout/(v1 – v2) = gm2(ro2//ro4) = 0.7071(200//400) = 94.28
V/V.
The second stage gain is given by vd5/vd2 = –gm5(ro5//ro7) = 0.8944(100//200) = –59.63
V/V.
The third stage gain is given by vout/vd5 = (gm6R’L)/(1+ gm6R’L) with R’L = (ro6//ro8) =
100 K. Therefore vout/vd5 = 100/101 = 0.99 V/V.
The overall gain is 94.28 × (-59.63) × (0.99) = –5565.7 V/V
e) [6 points] Find the common-mode gain Acm = vout/vicm when v1 = v2 = vicm. What is
the common-mode rejection ratio of the amplifier (in dB)?
Since ro3 = ro4 and gm3ro3 >> 1, the first stage common-mode gain is given by
–1/(2gm3ro10) = –1/(2 × 0.4472 × 200) = –0.00559 V/V
The second and third stages have the same gain as in part (d).
The common-mode gain is therefore (–0.00559) × (–59.63) × 0.99 = 0.33 V/V
The CMRR is 20 log(5566/0.33) = 84.54 dB
f) [4 points] Find the input common-mode range by calculating the maximum and
minimum values of V1 = V2 = VICM for which all MOSFETs are saturated.
The maximum VICM is determined by Q1 leaving SAT => VDS1 = VOV1 or VGD1 = Vtn
=> VICMmax – VG3 = Vtn => VICMmax = VGS3 + 2.5 + Vtn = –0.8236 + 2.5 + 0.5 =
2.1764 V
The minimum VICM is determined by Q10 leaving SAT => VDS10 = VOV10 =>
VS1 – (–2.5) = VOV10 => VICMmin – VGS1 + 2.5 = 0.2 => VICMmin = 0.6414 – 2.5 + 0.2 =
–1.659 V
g) [2 points] Find the minimum output voltage VOUT for which all MOSFETs remain
saturated. What transistor determines this limit?
The minimum output voltage corresponds to the condition Q8 at edge of SAT => VDS8
= VOV8 => VOUTmin – (–2.5) = 0.2 => VOUTmin = –2.3 V.
h) [2 points] Find the maximum output voltage VOUT for which all MOSFETs remain
saturated. What transistor determines this limit?
The maximum output voltage corresponds to the condition Q5 at edge of SAT since
Q5 enters the linear region before Q6 does as VOUT increases => |VDS5| = |VOV5| =>
2.5 – (VOUTmax + VGS6) = 0.2236 => VOUTmax = 2.5 – 0.7 – 0.2236 = 1.576 V
The zero is at Gm2/CC where Gm2 is the transconductance of the combined stage 2 –
stage 3 amplifier. The pole is at a 1/(R1R2Gm2CC) where R1 is the output resistance of
stage 1, and R2 is the output resistance of stage 3.
R1 is therefore ro2//ro4 = 133.3 KΩ
R2 is therefore (1/gm6)//ro6//ro8 = 1 // 200 // 200 = 0.99 KΩ
Gm2 is gm5(ro5//ro7)gm6 = 0.8944(100//200)1 = 59.63 mA/V
The zero is therefore at 59.63/(2πCC) = 9.49/CC GHz with CC in pF.
The pole is therefore at 1000/(133.3 0.99 59.63 2π Cc) = 0.0202/CC MHz with CC in
pF.
For a BJT differential amplifier, the value of β for the transistors varies between 100
and 140, around a mean value of 120. The transistors are biased using a 100 μA
current source.
a) [4 points] Find the input bias and the input offset currents.
The input bias current is IB = (I/2)/(β+1) where I is the source current. IB is therefore
(100/2)/(120+1) = 0.413 μA.
The input offset current is given by IBΔβ/β = 0.413 (40/120) = 0.138 μA.
b) [2 points] The circuit uses collector resistors, each equal to 10 KΩ, and emitter
resistors, each equal to 750 Ω. Show the circuit diagram.
c) [4 points] Find the range of values for the differential input resistance.
2V
v IN
R REF Q1
vOUT
RL
Q3 Q2
-2V
Figure 2
Refer to the circuit shown in Figure 2. The load resistor is RL = 1000 Ω. The
MOSFETs have k’n = 200 μA/V2 and Vtn = 0.5 V. The input voltage range is
unrestricted.
b) [10 points] Calculate the values of RREF and the (W/L) ratios for the MOSFETs so
that the output ranges from –0.5 to 0.5 volts with the highest efficiency and smallest
area. All MOSFETs should be in saturation over the range of operation. Assume that
Q2 and Q3 are matched.
The current I, flowing in RREF and mirrored in Q2, should be equal to |VOUTmin|/RL =
0.5/1000 = 0.5 mA, for maximum efficiency.
Q2 is always SAT => vOUT – (–2) > VOV2 => VOV2 < vOUT + 2 => VOV2 = –0.5 + 2 =
I
1.5 V, for minimum area. Therefore, ( WL ) 2 = 1 'D 2 2 = 0.5m/(.1m 1.52)
2 k nVOV
=> (W/L)2 = 2.22.
Since Q2 and Q3 are matched => (W/L)3 = 2.22.
Since VOV3 = VOV2 = 1.5V, the voltage at the drain of Q3 is VG3 = VGS3 – 2 = VOV3 +
Vtn – 2 = 1.5 + 0.5 – 2 = 0 V.
The voltage across RREF is 2 V, therefore RREF = 2V/0.5mA = 4 KΩ.
Q1 should be saturated => VOV1 = VDS1min = 2 – vOUTmax = 2 – 0.5 = 1.5 V
I
When vOUT = vOUTmax, ID1 = IL + ID2 = 1 mA => ( WL )1 = 1 ' D1 2 = 4.44.
2 k nVOV 1
2
Vout 0.52
The power in the load is PL = max
= = 0.125 mW.
2 RL 2000
The power in the two supplies is 2 V (1 mA) + 2 V (1 mA) = 4 mW.
The efficiency is therefore: 0.125/4 = 3.125%
+
Vo
-
50K RL=5K
RS=1K
Rout
1K
+
Vs 10K
Rin
Figure 3
The output is a voltage that is sampled using a shunt. The input is mixed using
currents, which is also a shunt. The type of feedback is therefore shunt-shunt.
b) [7 points] The op-amp is modeled by a differential input resistance Rid = 100 KΩ,
an open-circuit voltage gain of 5000, and an output resistance of 1 KΩ. Using
feedback techniques, find the open-loop gain A. What are the units of A?
1K
+ 5000Vid
+
Vid 100K
- Vo
50K RL=5K
50K
1K
1K
Is RS 10K 10K
c) [4 points] Find the feedback factor β. What are the units of β? What is the loop
gain?
Vo
50K
If 1K
10K
The circuit to find β is shown above. The value of β is given by If/Vo = (1K//10K)/(
1K//10K+50K)( –1/1K) = –17.857 μA/V
The loop gain is Aβ = (–3669.58 KΩ)(–17.857 μA/V) = 65.53
A −3669.58
Af = = = −55.16 KΩ
1+ β A 1 + 65.53
Vo V A
= o = f . The voltage gain is therefore Vo/Vs = –55.16 V/V.
Vs I s Rs Rs
Ri = 1K//100K//(1K+50K//10K) = 895.14 Ω
Rif = Ri/(1+βA) = 895.14/66.53 = 13.45 Ω
Rin = 1/ (1/Rif – 1/RS) = 13.64 Ω
Ro = 5K//1K//(50K+1K//10K) = 819.91 Ω
Rof = Ro/(1+βA) = 819.91/66.53 = 12.324 Ω
Rout = 1/ (1/Rof – 1/RL) = 12.35 Ω