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#LAB1

This document outlines the lab objectives for a Digital System Design course, focusing on gate-level modeling and simulation using Verilog. Students will learn to write Verilog code for combinational circuits, specifically a full adder, and simulate it using EDA Playground. The lab report must include solved activities, exercises, and waveform outputs before the next lab session.

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Hammad Bhatti
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18 views7 pages

#LAB1

This document outlines the lab objectives for a Digital System Design course, focusing on gate-level modeling and simulation using Verilog. Students will learn to write Verilog code for combinational circuits, specifically a full adder, and simulate it using EDA Playground. The lab report must include solved activities, exercises, and waveform outputs before the next lab session.

Uploaded by

Hammad Bhatti
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Department of

Computer Systems
Engineering

Digital System Design

Handout#01
Gate-Level Modelling and Simulation

Lab Learning Objectives:

After completing this session, student should be able to:


• Understand basics of Verilog programming.
• Get familiar with structural description (module instantiation).
• Simulate basic combinational circuits using gate-level modelling.

Note: Submit the lab report (solved activities and exercises) before the next lab.
Lab Hardware and Software Required:

1. Desktop/Laptop Computer with internet connection.

Background Theory:

Gate-level Modelling:
Verilog is both a structural and behavioral language. Internals of each module can be
defined at four levels of abstraction, depending on the need of the design. There are four
levels of abstraction which include switch-level, gate-level, data flow, and behavioral or
algorithm level.

The switch-level is the lowest abstraction level, where module can be implemented
in terms of switches, storage nodes, and interconnections between them.

The gate-level modelling is implemented in terms of logic gates and


interconnections between these gates. This design method is like describing a
design in terms of a gate-level logic diagram.

Verilog allows the designer to mix and match all four levels of design methodologies in
design. The modules behave identically to the external world identically irrespective of
the level of abstraction at which module iss described. Therefore, internals of the
modulecan be changed without any change in the environment.

In the digital design community, the term register transfer level (RTL) is used for Verilog
description that uses a combination of behavioral and data flow modelling. Normally, the
higher level of abstraction, design will be more flexible and technology independent.
Although, the lower-level description provides high performance therefore as the design
matures, high level modules are replaced with the gate-level modelling.
Lab Activity:
We are going to use testbench listing 1.7 (2-bit comparator design and its test vector) you
have covered in chapter#1 of the textbook.

Steps:
1. Open https://www.edaplayground.com/.
2. Write your testbench code at the left and required modules on the right.
3. Add these two lines after initial begin
$dumpfile("eq2_tb.vcd"); // simulator generates output file for the waveforms data
$dumpvars;
Also, replace $stop with $finish.

4. Select Icarus Verilog as your simulator.


5. Enable “Open EPWave after run”.
6. Run the coding.
7. After successful run, select signals to show waveforms.

Fig#1: EDA playground testbench programming and initial settings


Exercise:

Design a full adder circuit along with its test bench. You may give four input vectors (from
the table) in the test bench and observe the output from waveforms.

a b c_in sum c_out


1 0 0 1
2 1 1 0
3 1 0 1
4 1 1 1

Additionally, you are required to attach the input and output waveforms in your lab report.

Solution:

Module:

module full_adder (

input a, // First input


input b, // Second input
input c_in, // Carry input
output sum, // Sum output
output c_out // Carry output

);

assign sum = a ^ b ^ c_in; // XOR operation for sum


assign c_out = (a & b) | (c_in & (a ^ b)); // Carry out logic

endmodule
testbench:

module testbench;

reg a, b, c_in; // Inputs to the full adder


wire sum, c_out; // Outputs from the full adder

// Instantiate the full adder module


full_adder fa (
.a(a),
.b(b),
.c_in(c_in),
.sum(sum),
.c_out(c_out)
);

initial begin
// Open VCD file for waveform
$dumpfile("full_adder_tb.vcd");
$dumpvars;

// Display the headers


$display("Time\t a b c_in | sum c_out");
$monitor("%g\t %b %b %b | %b %b", $time, a, b, c_in, sum, c_out);

// Test vector 1
a = 1; b = 0; c_in = 0;
#10;

// Test vector 2
a = 1; b = 1; c_in = 0;
#10;

// Test vector 3
a = 1; b = 0; c_in = 1;
#10;

// Test vector 4
a = 1; b = 1; c_in = 1;
#10;

$finish; // Terminate simulation


end

endmodule

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