Digital System Design

Lecture 3 -Flip-Flops and related Devices

Instructors:
Dr. Nguyen Tuan Khanh, postdoc, [email protected]
M.Sc. Nguyen Vo That Thuyet, lab engineer, [email protected]
Electrical and Computer Engineering (ECE)
Faculty of Engineering, Vietnamese-German University, Vietnam

1
Sep. 2024
 Introduction
• The logic circuit consider so far has no
memory
• Depending on only current statuses
• Flip-flop is the most important memory
element
• A logic gate cannot store info.
• Several gates are used to form a flip-flop

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 Introduction
•

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 Introduction
• Flip-flop
• Several inputs
• Switch back and forth
• Momentarily activated (pulsed)
• Other names
• Latch
• Bistable multivibrator

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 Introduction

A
A
Y
B B

Set

Set Q
Reset
Reset
Q

• Momentarily activated (pulsed)

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 NAND Gate Latch
• Most basic FF
• Two NAND gates or
• Two NOR gates
• The SET and RESET of NAND gate latch
• Normally in the HIGH state
• LOW pulse

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 NAND Gate Latch
• SET = RESET = 1
• First possibility

• Second possibility

• Two possibilities for the same combination of states of

inputs
• Which possibility occurs depends on what happened
previously
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 NAND Gate Latch
• Setting the latch
• Q=0 • Q=1
• A LOW pulse on SET always causes Q = 1

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 NAND Gate Latch
• Resetting the latch
• Q=0 • Q=1
• A LOW pulse on RESET always causes Q = 0

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 NAND Gate Latch
•

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 NAND Gate Latch
• Summary

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 NAND Gate Latch
• Alternative representations

Active-LOW

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 NAND Gate Latch
• Example
• Given SET and RESET waveforms and initial Q, determine the waveform of Q
• It “remembers” the last input that was activated and will not change until
the opposite input is activated

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 NAND Gate Latch
• Example

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 NOR Gate Latch
•

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 NOR Gate Latch
• Simplified block symbol

NOR Gate Latch NAND Gate Latch

• Example
• Given SET and RESET waveforms and initial Q, determine the waveform of Q

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 NOR Gate Latch
• Example
• Detect the interruption of a light beam
• Normally S = R = 0
• Light beam is interrupted even just a
very short time, Q = 1 to alarm
• Push SW1 to turn off the alarm

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 NOR Gate Latch
• Flip-flop state on power-up
• When power is applied to a circuit, it is not possible to predict the starting state of
a flip-flop’s output
• May depend on
• Internal propagation delays, parasitic capacitance, and external loading
• Or must start off in a particular state to ensure the proper operation of a
circuit
• Must be placed in that state by momentarily activating the SET or RESET
input

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 Troubleshooting Study Case
•

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 Troubleshooting Study Case
• The same circuit with the observation
shown as follows
• When the switch is at B, correctly
• When the switch is at A, Q is not at
HIGH

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 Troubleshooting Study Case
•

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 Troubleshooting Study Case
• Possibilities
• The Q output is stuck LOW, which could be
caused by:
• Z1-3, Z1-4, or Z2-2 internally shorted to
ground
• The Q node externally shorted to ground
• Checking:
• An ohmmeter check from Q to
ground will determine if any of these
conditions are present.
• A visual check should reveal any
external short.
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 Digital Pulses
• A signal switches from a inactive state to an active state, causing sth
to happen
• That signal returns to inactive state but its effect remains
• The signals are called pulses
• Positive pulses: active state = HIGH
• Negative pulses

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Digital Pulses

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 Digital Pulses
• Example
• A microcontroller wants to access data in its external memory,
• It activates an active-LOW output pin called (read)
• Pulse width of 50 ns, a rise time of 15 ns, a fall time of 10 ns

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 Clock Signals and Clocked Flip-Flops
• Digital systems can operate either asynchronously or synchronously.
• In asynchronous systems, the outputs change state any time the inputs change.
• An asynchronous system is generally more difficult to design and troubleshoot.
• Most digital systems are principally synchronous.

• Synchronous systems:
• Outputs can change state only when the clock makes a transition.
• The clock signal
• Distributed to all parts of the system;
• Generally a rectangular pulse train or a square wave.

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 Clock Signals and Clocked Flip-Flops
• Synchronous systems:
• The speed of a synchronous digital system depends on how often the clock
cycles occur
• The number of cycles in 1s = Frequency (F)

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 Clock Signals and Clocked Flip-Flops
• Clocked Flip-Flops
• A clock input that is typically labeled CLK, CK, or CP.
• In most clocked FFs, the CLK input is edge-triggered
(Latches are level-triggered).

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 Clock Signals and Clocked Flip-Flops
• Clocked Flip-Flops
• Control inputs
• No effect on Q until the active clock transition occurs.
• Called synchronous control inputs.
• The control inputs control the WHAT (i.e., what state the output will go to);
the CLK input determines the WHEN.

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 Clock Signals and Clocked Flip-Flops
• Setup and Hold Times
• Two timing requirements must be met if a clocked FF is to respond to its
control inputs and CLK transition

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 Clock Signals and Clocked Flip-Flops
• Setup and Hold Times
• The control inputs must be stable (unchanging) for at least tS prior to the
clock transition, and for at least tH after the clock transition
• These times are measured between the 50% points on the transitions.

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 Clocked S-R Flip-Flop
• A clocked S-R flip-flop similar to a NOR latch but required a ↑

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 Clocked S-R Flip-Flop

• Assume that the setup and hold time

requirements are met

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 Clocked S-R Flip-Flop
• Internal circuitry of the edge-triggered S-R flip-flop
• Although our main interest is the FF’s external operation,
• A simplified version of the FF’s internal circuitry will aid
• Note: NAND latch with NAND pulse-steering circuit
• Active-LOW SET, RESET
• Active-HIGH S, R

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 Clocked S-R Flip-Flop
• Internal circuitry of the edge-triggered S-R flip-flop
• The edge detector produces a narrow positive going spike (CLK*)

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 Clocked J-K Flip-Flop
• The same ways as for the clocked S-R flip-flop
• J = K = 1 does not result in an ambiguous output

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Clocked J-K Flip-Flop

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 Clocked J-K Flip-Flop
• Internal circuitry of the edge-
triggered J-K flip-flop
• The CLK* pulse must be very
narrow,
• It must return to 0 before Q
output a new value,
• Otherwise the latch toggles again

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 Clocked D Flip-Flop
• Only one synchronous control input
• Q will go to the same state that is present on the D input when a PGT occurs at CLK

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 Clocked D Flip-Flop
• Waveforms

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 Clocked D Flip-Flop
• Implementation of the D flip-flop

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 D Latch (Transparent Latch)
• The D latch is not edge-triggered

• Determine the Q waveform for a D latch with the EN and D inputs given. Assume that Q = 0 initially
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 Comments for teaching
• Criteria:
• Module objectives were clear. • Students were encouraged to apply
• Learning materials were sufficient and critical thinking and logics.
useful. • Lecturer gave helpful feedback.
• Content of the module was always • English level of the lecturer was excellent.
relevant. • Lecturer listened to students’ ideas and
contributions.
• Lessons were interesting.
• Lecturer encouraged discussion and
• Module contents were presented questions in class.
understandably.
• Appropriate module workload.
• Various learning activities were used to • Appropriate module difficulty.
teach the content.
• Lecturer offered consultation to individual
• Learning activities supported the intended for academic support.
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learning outcomes.
 Asynchronous Inputs
• Asynchronous Inputs (AIs) operate independently of the synchronous inputs and
clock input
• AIs can be used to set or clear the FF at any time, regardless of the conditions at
the other inputs
• AIs are override inputs

• Note that: asynchronous inputs of a device (e.g., flip-flops) (maybe of an asyn-

/synchronous-system device) are different from concept asynchronous systems

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 Asynchronous Inputs
• Not used in all applications 🡪 permanently held at inactive states

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 Asynchronous Inputs
• Example
• Draw the waveform of Q for given CLK, PRE,
and CLR’s
• Provided long and short active-LOW
segments of PRE and CLR

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 Flip-Flop Timing Considerations
• Manufacturers specify timing parameters and characteristics
• Setup and hold times

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 Flip-Flop Timing Considerations
• Propagation delays
• So please distinguish raising time (tR), falling time (tF), set-up
time (tS) and hold time (tH).

• Propagation delays
• Range from a few ns to 100 ns
• tPLH and tPHL are generally not the same
• Increase w/ the no. of loads driven by the Q output

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 Flip-Flop Timing Considerations
• Maximum clocking frequency, fMAX
• The highest frequency that may be applied to the CLK input of a FF and still have it
trigger reliably.
• Clock pulse HIGH and LOW times
• The min time duration that the CLK must remain LOW before it goes HIGH = tW(L)
• The min time duration that the CLK must remain HIGH before it goes LOW = tW(H)

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 Flip-Flop Timing Considerations
• Asynchronous active pulse width
• tW(L) for active-LOW asynchronous inputs.

• Clock transition times

• Should be kept very short
• Generally should be ≤ 50 ns for TTL and ≤ 200 ns for CMOS

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 Flip-Flop Timing Considerations
• Actual ICs

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 Potential Timing Problem in FF Circuits
• If tPHLis not greater than tH, the response of Q2 is unpredictable
• The FF output will go to a state determined by the logic levels present at its
synchronous control inputs just prior to the active clock transition

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 Flip-Flop Applications
• Applications including
• Counting,
• Storing of binary data,
• Transferring binary data from one location to another,
• Many more
• Almost utilize clocked operation
• A sequential circuit:
• Outputs follow a predetermined sequence of states
• A new state occurring each time a clock pulse occurs

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 Flip-Flop Synchronization
• Most signals change states synchronously with the clock transitions
• External signals may be not synchronized to the clock
• As a result of human’s actuating
• This randomness can produce unpredictable and undesirable results

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 Flip-Flop Synchronization
• Example

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 Flip-Flop Synchronization
• Example

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 Detecting an Input Sequence
Certain combination of inputs Activate something

Certain combination and sequence of inputs Activate something

A must go HIGH prior to B by at least the setup time

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 Data Storage and Transfer
• Synchronous transfer

• Value stored in FF A is transferred to FF B upon the NGT of the TRANSFER

pulse

• Synchronous transfer: the synchronous control and CLK inputs are used
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 Data Storage and Transfer
• Parallel data transfer
• Does not change the contents of the register that is the
source of data

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 Serial Data Transfer: Shift Registers
• Shift registers
• A group of FFs arranged so that the binary numbers stored in the FFs are shifted from
one FF to the next for every clock pulse

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 Serial Data Transfer: Shift Registers
• Shift registers
• The waveforms
• Hold time requirements

CLK

Data in

X3
Hold time
X2

CLK-to-output propagation delay 61

 Serial Data Transfer: Shift Registers
• Remind
• The hold time is the interval following the active transition of the CLK
signal during which the synchronous control input must be maintained at
the proper level

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 Serial Data Transfer: Shift Registers
• Serial transfer between registers

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Serial Data Transfer: Shift Registers

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 Serial Data Transfer: Shift Registers
• Parallel versus serial transfer

• Single pulse
• N clock pulses
• The last FF in reg. X to the first FF in Y
• Economy and simplicity
• Speed

• When the transmission distance is long

• When there are a great no. of bits to be transmitted
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Frequency Division and Counting

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Frequency Division and Counting

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 Frequency Division and Counting
• Frequency division
• Each FF divides the freq. of its input by 2
• Using N flip-flop produce an output freq. = 1/2N of the input freq.
• Example: quartz watch, the “second” display (1Hz) is produced by divided a
much higher freq. signal from the crystal

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 Frequency Division and Counting
• Counting operation
• State table
• State transition diagram

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 Frequency Division and Counting
• MOD number
• Indicates the number of states in the counting sequence
• N flip-flops 🡪 MOD-2N counter

• Example:
• Assume that the MOD-8 counter in the 011 state.
What will be the state (count) after 21 pulses
have been applied?

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 Frequency Division and Counting

• Example:
• Consider a counter circuit that contains 5 FFs similar to the above (i.e., Q4, Q3, Q2, Q1,
Q0).
• (a) Determine the counter’s MOD number.
• (b) Determine the frequency at the output of the last FF (Q4) when the input clock
frequency is 1 MHz.
• (c) What is the range of counting states for this counter?
• (d) Assume a starting state (count) of 00000. What will be the counter’s state after 129
pulses? 71
 Microcomputer Application
• A microprocessor unit (MPU) is the central processing unit of a microcomputer
• Execute a program stored in memory

• E.g., On/Off devices such as

relays, motors, …
• The data determines which
device

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