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ECE204-Digital System Design-Lecture 7 - DSD ch13 Programmable Logic Device Architecture

The document discusses programmable logic devices (PLDs) used in digital system design, highlighting their advantages such as reduced board space, lower power consumption, and increased reliability. It outlines different types of PLDs, including SPLDs, CPLDs, and FPGAs, and emphasizes the importance of design considerations like speed, cost, and power. Additionally, it covers PLD architectures, specifically focusing on Programmable Array Logic (PAL) and its efficiency compared to traditional PROMs.

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21 views19 pages

ECE204-Digital System Design-Lecture 7 - DSD ch13 Programmable Logic Device Architecture

The document discusses programmable logic devices (PLDs) used in digital system design, highlighting their advantages such as reduced board space, lower power consumption, and increased reliability. It outlines different types of PLDs, including SPLDs, CPLDs, and FPGAs, and emphasizes the importance of design considerations like speed, cost, and power. Additionally, it covers PLD architectures, specifically focusing on Programmable Array Logic (PAL) and its efficiency compared to traditional PROMs.

Uploaded by

10223088
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Digital System Design

Lecture 7 -Programmable logic device


architectures

Instructors:
Dr. Nguyen Tuan Khanh, postdoc, [email protected]
M.Sc. Nguyen Vo That Thuyet, lab engineer, [email protected]
Electrical and Computer Engineering (ECE)
Faculty of Engineering, Vietnamese-German University, Vietnam

1
Sep. 2024
Introduction
• Today, digital systems are not implemented with standard logic device chips with only simple
gates or MSI-type functions.

• Programmable logic device (PLD) is used.


• PLD is configured by electronically connecting and disconnecting points in the circuit.

• Functions can be provided obtained with only one


IC.
🡪Less board space, less power required, greater
reliability, less inventory, and overall lower cost in
manufacturing.
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13-1 DIGITAL SYSTEMS FAMILY TREE
• Design engineering decisions consider
Most complex digital designs include a mix of
• Speed of operation, different hardware categories.
• Cost of manufacturing,
• Power consumption, Many trade-offs between the various types of
• System size, hardware have to be weighed.
• Amount of time to design, …

3
13-1 DIGITAL SYSTEMS FAMILY TREE

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13-1 DIGITAL SYSTEMS FAMILY TREE

Gates, flip-flops, decoders,


multiplexers, registers,
Very Most For higher- counters,…
seldom popular, low speed
today. power designs. SSI, MSI
consumption.
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13-1 DIGITAL SYSTEMS FAMILY TREE

Can be controlled electronically by an application program.

High flexibility.

Low speed (for digital-system solution, software is slower than hardware).


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13-1 DIGITAL SYSTEMS FAMILY TREE
Sometimes referred to
as field programmable
logic devices (FPLDs).

Custom-configured to
create simple or
complex digital circuit.

Must contract with an IC foundry


Possible with a to fabricate the desired IC chip.
relatively small capital
investment.
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13-1 DIGITAL SYSTEMS FAMILY TREE

• PLDs
• PLD development
• Gate number increase (billions);
• Input/output number increase (hundreds);
• On-the-fly reconfiguration.

8
Digital-System Family Tree
• PLDs
– The difference among types are fuzzy
• Simple programmable logic devices (SPLDs);
• Complex programmable logic devices (CPLDs);
• Field programmable gate arrays (FPGAs).
– Especially, the last two, which are referred to high-capacity programmable logic devices
(HCPLDs).
– The manufacturers constantly design new, improved PLDs.

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13-2 FUNDAMENTALS OF PLD CIRCUITRY
• Example of a programmable
logic device

• If we blow fuses 1 and 4 at


OR gate 1,

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13-2 FUNDAMENTALS OF PLD CIRCUITRY
• Simplified PLD symbology

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13-2 FUNDAMENTALS OF PLD CIRCUITRY
• Simplified PLD symbology

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13-3 PLD ARCHITECTURES Fuses are blown to program outputs for
• PROMs
given functions

PROM architecture makes


it suitable for PLDs

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13-3 PLD ARCHITECTURES

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13-3 PLD ARCHITECTURES
• PROMs

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13-3 PLD ARCHITECTURES
PLD PAL

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13-3 PLD ARCHITECTURES
• Programmable Array Logic (PAL)
• Using PROMs as PLDs is not efficient in terms of circuitry
• Requires many fuses;
• Many product terms not used.
• PAL
• Inputs to the AND gates are programmable.
• Inputs to the OR gates are hard-wired.
• E.g., only to 4 AND outputs.

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13-3 PLD ARCHITECTURES
• PAL

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13-3 PLD ARCHITECTURES

• PAL

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