Lecture #1 Introduction UC Berkeley: EECS 240B

EECS 240B: Advanced Analog

Integrated Circuits

Osama Shana’a
Sr. Director RF-design, MediaTek Inc.
[email protected]

office: 504 Cory Hall

Copyright© Dr. Osama Shana’a

Lecture #1 Introduction UC Berkeley: EECS 240B
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office hours:
- Regular: TueThu 5:05pm-6:05pm/ 504 Cory
(shortly after class)
- Upon request: (email me if you have any
questions and if I can’t answer by email, we will
schedule a ZOOM meeting

GSI/TA: Rami Hijab

email: [email protected]
DIS (recorded): Fri 9:00am-10:00am
TA office hour (not recorded): TBA

Copyright© Dr. Osama Shana’a

Lecture #1 Introduction UC Berkeley: EECS 240B
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Class objectives:
● Hands on experience in the art of analog circuit
design, with emphasis on practical considerations.

● Develop design methodologies and techniques for

optimizing analog circuits
● Create proper understanding of basic tradeoffs
● adopt learned analog circuit design fundamentals to
build complex analog circuits that are robust for
volume production

Prerequisite: 140, 240A

Copyright© Dr. Osama Shana’a

Lecture #1 Introduction UC Berkeley: EECS 240B
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Grading:
● 20% homework
You can collaborate! In the real world you will be part of a team,
so need to learn how to work in a team. However, do not copy
each other. Use discussions to enrich your understanding of the
subject but then you need to come up with your own design and
solution to submit and defend. This is how it is in the real world!
Will be using a modified 45nm CMOS process in this class.

● 25% midterm exam (March)

Will announce the logistics later
● 30% project:
The details and formality of the project will be provided later. The project
starts right after the midterm exam.
● 25% final exam
Copyright© Dr. Osama Shana’a
Lecture #1 Introduction UC Berkeley: EECS 240B
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Lecture notes:
● can be downloaded from the bCourse website:
https://bcourses.berkeley.edu/courses/1540021

● Please print lecture prior to coming to class to take

your own notes. If you want to stay “green”, download
an electronic copy on your tablet and take electronic
notes
• bCourse will be used to communicate with students
for blast emails.
• Ed Discussion will be used for discussions

Copyright© Dr. Osama Shana’a

Lecture #1 Introduction UC Berkeley: EECS 240B
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CAD tools:
● will be using Spectre/Virtuoso for circuit simulation

→ Any CAD/setup related problems please consult with

GSI.

- No late homework. If you have an urgent reason to delay

your homework, please contact me to get approval.
Delayed homework will be pro-rated to be fair to other
students who submit their work on time (in the real world,
late projects result in lower bonus and no promotions!)

Copyright© Dr. Osama Shana’a

Lecture #1 Introduction UC Berkeley: EECS 240B
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Lectures:
• Notes in PDF can be downloaded from bCourse
• Lectures will NOT be recorded to help with the in-
person leaning spirit.
• better come to class to attend live discussion. In normal
circumstance we may take attendance.

Copyright© Dr. Osama Shana’a

Lecture #1 Introduction UC Berkeley: EECS 240B
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Text book?
• No specific text book. Lecture notes are posted on
bCourse
• However, below are some good references:

Copyright© Dr. Osama Shana’a

Lecture #1 Introduction UC Berkeley: EECS 240B
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Why this class is good for you?

● the world is, and will always be, analog!
❑ Analog contents in any cellular phone are increasing:
• Power management units, chargers and LDOs
• Audio amplifiers
• Some RF transceiver ICs have as much as ~50% analog circuits!

Copyright© Dr. Osama Shana’a

Lecture #1 Introduction UC Berkeley: EECS 240B
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Typical RF transceiver :
Cellular and connectivity:
• Receiver analog TIA (also called TZ or trans-impedance amplifier)
• Receive/Transmit continuous-time analog filters
• LDOs, PLL, temp-sensors, bandgap reference, biasing generators
WiFi6 Shanaa, et. Al., ISSCC 2020

Copyright© Dr. Osama Shana’a

Lecture #1 Introduction UC Berkeley: EECS 240B
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Analog sensors:
• All kinds: temperature, pressure, vibration, viscosity, photo/light,
gas, sound etc.
• biomedical: ECG, blood pressure, sugar content, EEG, ultrasound
imaging, hearing aid, etc.

Carbon monoxide sensor

Copyright© Dr. Osama Shana’a

Lecture #1 Introduction UC Berkeley: EECS 240B
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Standard (standalone/catalog) analog components:
• Voltage references, LDOs, video amplifiers, audio amplifiers, industrial
temperature sensors, reference clocks, etc.
• Automotive → growing sector of analog design
• Total annual sales of standard analog components >$50B
• Key players: TI, ADI, Infineon, NXP, ST Micro

Copyright© Dr. Osama Shana’a

Lecture #1 Introduction UC Berkeley: EECS 240B
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Course outline:
Part I: Some Fundamentals, useful for Analog design
o MOS transistor modeling (and impact on design flow):
o Square-law model vs gm/Id
o Short channel effects and impact on device
performance/parameters
o Electronic noise and noise analysis
o Gain-bandwidth (GBW) product and its use in amplifier
design

Copyright© Dr. Osama Shana’a

Lecture #1 Introduction UC Berkeley: EECS 240B
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Part II: Analog Amplifier design

❑ Operational Transcodcutance Amplifier (OTA)
o Where do you need an OTA
o Single-stage vs multi-stage
o Single-ended vs differential
o Feedback
o Differential compensation
o Common-mode circuits and compensation
❑ Interference and interference mitigation techniques

Copyright© Dr. Osama Shana’a

Lecture #1 Introduction UC Berkeley: EECS 240B
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Part III: Variable/Programmable-Gain Amplifier,

VGA/PGA, design
o VGA/PGA specifications
o Popular VGA/PGA topologies
o Current steering
o Variable degeneration diff-pair
o Shunt-feedback
o MOS-based soft-switching AGC
o Digital AGC control
o DC offset analysis and cancellation techniques
o Design techniques for fast dynamic DC offset settling
o Servo-loop design. Chopper stabilization. Digital DC offset cal

Copyright© Dr. Osama Shana’a

Lecture #1 Introduction UC Berkeley: EECS 240B
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Part IV: Analog Filters

- Introduction to filters
o Filter function and specifications
o Integrated filter Architectures
o Ladder
o Cascade
o Integrated filter topologies
o Opamp-RC
o Gm-C
o Switched-cap
o Realization methods of active filters
o direct replacement
o Signal-flow graph
o Tuning
o Frequency tuning methods
o Q-tuning methods
o Group delay equalizer design
Copyright© Dr. Osama Shana’a
Lecture #1 Introduction UC Berkeley: EECS 240B
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Part V: Misc.
o Transistor matching:
o Area and Vth mismatch (basics)
o Mismatch calculation
o Layout techniques to improve device matching
o Few practical considerations
o Layout techniques to improve device matching
o Comparator design
o Settling (if we have time)

Copyright© Dr. Osama Shana’a

Lecture #1 Introduction UC Berkeley: EECS 240B
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Part VI: Biasing and Supply regulation

Biasing flavors for analog circuits
– PTAT, CTAT and constant-gm
– Bandgap design
– Current mirror generation for biasing
– Bias slope control vs temperature
– Using bias flavors to obtain robust amplifier performance
over PVT
Practical examples of how biasing mistakes can cause
problems

Copyright© Dr. Osama Shana’a

Lecture #1 Introduction UC Berkeley: EECS 240B
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Part VII: PLL Design

- PLL specifications and its impact on RF system
o Integrated phase error
o Stability
o Spectral purity
- Integer-N PLL architecture and loop analysis
- Integer-N PLL design
o CMOS digital divider design
o PFD design and analysis
o Charge-pump design
o Design of loop filter
- Fractional-N PLL design , if time permits ☺
o Design of Σ-Δ modulator
o Verification of Frac-N PLL using Matlab
o Design of loop filter

Copyright© Dr. Osama Shana’a

Lecture #1 Introduction UC Berkeley: EECS 240B
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Introduction to analog design

Copyright© Dr. Osama Shana’a

Lecture #1 Introduction UC Berkeley: EECS 240B
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analog design- the big picture:
What does an analog block usually do?

sensor analog DSP

Desired
signal
few µV few 100mV
S/N SNDR harmonics

noise distortion noise

Freq (Hz) Freq (Hz)

An analog block either senses, amplifies or filters analog

signals, faithfully, and make them suitable for digitization
and further digital signal processing. It can also do all
these tasks combined Copyright© Dr. Osama Shana’a
Lecture #1 Introduction UC Berkeley: EECS 240B
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Important analog specs:
1. Sensitivity (input referred noise)

sensor analog DSP

Desired
signal
few µV few 100mV Noise added by
S/N SNDR analog circuit
noise
Freq (Hz)

Sensitivity is the lowest input signal level detectable by the

system while still meeting the min acceptable signal/noise
ratio at the DSP detector. Input referred noise of analog
circuits degrades the S/N, hence sensitivity Copyright© Dr. Osama Shana’a
Lecture #1 Introduction UC Berkeley: EECS 240B
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2. Selectivity

analog DSP

unwanted
few 10’s dB signal
desired
desired signal
signal

Freq (Hz) unwanted

signal

Selectivity is the level ratio of desired signal to all other

“unwanted” interferers in dB (integrated over the signal
bandwidth). An analog block should be able to “select”
the desired signal, faithfully, in presence of large
interference
Copyright© Dr. Osama Shana’a
Lecture #1 Introduction UC Berkeley: EECS 240B
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3. Linearity (distortion)

sensor analog DSP

Desired
signal
few µV few 100mV
SNDR harmonics

distortion
Freq (Hz)

Analog block should create little in-band as well as out

of band (harmonic) distortion set by in-band SNDR and
out of band distortion specifications
Copyright© Dr. Osama Shana’a
Lecture #1 Introduction UC Berkeley: EECS 240B
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4. Dynamic range: Gain control

analog
DSP

Can be
90dB! fixed signal
level fed to A/D
desired
signal
desired
Freq (Hz) signal

In some cases, analog block is required to provide a

fixed signal level to DSP A/D despite the variation of the
desired signal level at its input by as much as 90dB
(dynamic range). The gain control range level is set by
the A/D dynamic range Copyright© Dr. Osama Shana’a
Lecture #1 Introduction UC Berkeley: EECS 240B
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What differentiates one analog design from the other?

• Silicon area
• Trimming
• Calibration
• Test time
• Off-chip components
→ cost

Analog specs are interrelated (in many cases fixing one

parameter messes up the other). A tradeoff at the end
needs to be made. On top of that, the company that
meets the required specifications with lowest die
area/cost wins. Copyright© Dr. Osama Shana’a
Lecture #1 Introduction UC Berkeley: EECS 240B
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So how can one go about analog design?

There are actually 4 methods (flow):

1. Handcraft. This has been the traditional analog design
flow in which designer with good fundamentals knows how
to make proper topology selection and proper design
tradeoff to meet target spec.

This flow is time consuming, requires sharp design skills and

tends to be iterative in nature with no guarantee the output is
optimum. However, it can result in a very creative/innovative
design for those who think out of the box (new topologies).

Copyright© Dr. Osama Shana’a

 Lecture #1 Introduction UC Berkeley: EECS 240B
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2. partially-automated analog synthesis: (Barcelona)
This flow relies on the following:
a. starting with known topologies for a given design (say opamp →
folded cascode).
b. The design then is represented by a series of equations (gain,
input/output impedance, bandwidth, noise, etc. relating device
parameters (W/L, bias, etc) to these specifications
c. The design then is subject to boundary conditions (maximum die
area, maximum current consumption, Vdd, etc.)
d. An optimization engine (say convex optimizer) is used to sweep
the device parameters to meet design specs while staying within
boundary condition
e. The engine spits out the chosen topology with device size and
component values calculated. Some also spit out the layout!
Short coming of this flow is that it relies on pre-set topologies (no innovation).
It just makes the design calculation faster. Copyright© Dr. Osama Shana’a
Lecture #1 Introduction UC Berkeley: EECS 240B
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3. Semi-automated analog synthesis: (BAG)
This flow relies on the following:
a. The flow also starts with known topologies for a given design.
b. Parameterizeable scripts (Python) are used to express the design
c. The tool then interfaces with simulator and layout tools for
simulation and layout extraction
d. With boundary conditions (specs, area, current, etc) the engine
generates the design schematic and layout

Short coming of this flow is same as the partially automated

flow in that it relies on pre-set topologies. It just makes the
design calculation faster with less iterations because it includes
layout impact as well.
→ For more details, consult with prof. Elad Elon and Prof.
Vladimir Stojanavic Copyright© Dr. Osama Shana’a
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4. fully-automated analog synthesis: (AI)
I personally feel the only rout to fully automated analog
synthesis is via artificial intelligence-driven engine:
a. The AI engine “learns” from the huge database of analog design
topologies, analysis, performance limits, etc.
b. For a given set of specs, the engine can decide which topology
best fits the target specs and boundary conditions
c. The engine has no issues taking layout and its impact on design
into consideration even at the start of topology selection.
d. The issue is the database needed for learning
e. This area is just starting (excellent Ph.D thesis topic).

Short coming of this flow is the computation power (Watt)

needed is huge. Furthermore, at this stage it is doubtful that AI
can invent new topologies. Innovation may still need human
brains ☺
Copyright© Dr. Osama Shana’a
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In this class, we will go over important analog

design concepts and fundamentals first. Then
we will use these to build complex analog
blocks, such as OTAs, filters, VGAs, LDOs, etc.
You can build on this knowledge later to build
even more complex analog systems such as
high-speed SERDES

Copyright© Dr. Osama Shana’a