Scribd
Upload
8 views2 pages

Assignment - 3 - Set 4 - Thusday

This document outlines Lab Assignment 3 for the B.Tech Digital Design course, focusing on the implementation of Boolean expressions using logic gates and Verilog-HDL. It includes tasks such as proving Boolean algebra laws, creating truth tables, drawing schematic diagrams, and writing Verilog code for given Boolean expressions. Submission instructions emphasize the importance of proper documentation, timely submission, and adherence to academic integrity standards.

Uploaded by

Prejval Yadav
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
8 views2 pages

Assignment - 3 - Set 4 - Thusday

This document outlines Lab Assignment 3 for the B.Tech Digital Design course, focusing on the implementation of Boolean expressions using logic gates and Verilog-HDL. It includes tasks such as proving Boolean algebra laws, creating truth tables, drawing schematic diagrams, and writing Verilog code for given Boolean expressions. Submission instructions emphasize the importance of proper documentation, timely submission, and adherence to academic integrity standards.

Uploaded by

Prejval Yadav
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

Practical

Course- B.Tech Type- Core


Course Code-CSET-105 Course Name- Digital Design
Session-2024-25 Semester-Even
Date- 30 Jan 2025 Batch- ALL

Lab Assignment 3_Set 4

Practical title: Implementation of Boolean expressions using logic gates

Name CO1 CO2 CO3


✓ ✓
In this Lab, we will be able to determine the truth table of any given Boolean expression and then
implement the expression with logic gates. Also, we will learn to implement an expression in Verilog-
HDL.

1. State and prove following laws of Boolean algebra.


(a) Consensus Law
(b) Absorption Law

2. State and prove following laws of Boolean algebra.


(a) De-Morgan’s Law
(b) Distributive Law

3. Given Boolean expression: F(ABC) = AB + A’B’ + B’C


a) Write the truth table for the above Boolean expression.
b) Draw the schematic diagram for the above Boolean expression.
c) Write the Verilog code for the Boolean expression and then compare testbench generated
waveform with the truth table to verify your circuit.

4. Given Boolean expression: F(A,B) = AB + A’B’


a) Write the truth table for the above Boolean expression.
b) Draw the schematic diagram for the above Boolean expression.
c) Write the Verilog code for the Boolean expression and then compare testbench generated
waveform with the truth table to verify your circuit.

5. Given Boolean expression F(ABC) = ABC + AB’C’+A’BC’+A’BC+ A’B’C’


a) Write the truth table for the above Boolean expression.
b) Draw the schematic diagram for the above Boolean expression.
c) Write the Verilog code for the Boolean expression and then compare testbench generated
waveform with the truth table to verify your circuit.
Practical

Submission Instructions:

• Prepare the submission file according to the following process:

1. Copy the Verilog code, the Test Bench Code in a Word File.
2. Take the ScreenShot of Waveform and paste into the same word file.
3. Repeat Step 1 and 2 for all the programs.
4. Copy and Paste all the Verilog code, Testbench Code and Waveform into a single word
file as 1_verilog, 1_TestBench, 1_Waveform, 2_verilog, 2_TestBench, 2_Waveform…
etc.
5. Convert it into pdf file, name it as RollNo_Assignment# (Example: E20CSE001_
Assignment3.pdf).

6. Submit your file on LMS within the deadline.

• Write your Name and Roll No. as comment before starting of each program. Keep in mind this
is Mandatory. Failing which you may lose your marks.
• Make it sure that in each program, you have mentioned enough comments regarding the
explanation of program instructions.
• Each student will submit their assignment on their corresponding group slot only.
• Late submission will lead to penalty.
• Any form of plagiarism/copying from peer or internet sources will lead penalty.
• Following of all instructions at submission time is mandatory. Missing of any instructions at
submission time will lead penalty.

You might also like