Unit -1 IC Technologies, MOS & Bi CMOS Circuits Unit -1 IC Technologies, MOS & Bi CMOS Circuits Unit -1 IC Technologies, MOS

IC Technologies, MOS & Bi CMOS Circuits Unit -1 IC Technologies, MOS & Bi CMOS Circuits

Moore’s Law:

INTRODUCTION TO IC TECHNOLOGY  Gordon E. Moore - Chairman Emeritus of Intel Corporation MOS TECHNOLOGY:
The development of electronics endless with invention of vaccum tubes and associated  1965 - observed trends in industry - of transistors on ICs vs release dates MOS technology is considered as one of the very important and promising technologies in
electronic circuits. This activity termed as vaccum tube electronics, afterward the evolution of solid  Noticed number of transistors doubling with release of each new IC generation the VLSI design process. The circuit designs are realized based on pMOS, nMOS, CMOS and
state devices and consequent development of integrated circuits are responsible for the present status  Release dates (separate generations) were all 18-24 months apart BiCMOS devices.
of communication, computing and instrumentation. The pMOS devices are based on the p-channel MOS transistors. Specifically, the pMOS
“The number of transistors on an integrated circuit will double every 18 months”
• The first vaccum tube diode was invented by john ambrase Fleming in 1904. channel is part of a n-type substrate lying between two heavily doped p+ wells beneath the
• The vaccum triode was invented by lee de forest in 1906. source and drain electrodes. Generally speaking, a pMOS transistor is only constructed in
The level of integration of silicon technology as measured in terms of number of devices per IC
Early developments of the Integrated Circuit (IC) go back to 1949. German engineer consort with an NMOS transistor.
Semiconductor industry has followed this prediction with surprising accuracy.
Werner Jacobi filed a patent for an IC like semiconductor amplifying device showing five The nMOS technology and design processes provide an excellent background for other
transistors on a common substrate in a 2-stage amplifier arrangement. Jacobi disclosed small IC Technology:
technologies. In particular, some familiarity with nMOS allows a relatively easy transition to
cheap of hearing aids.
• Speed / Power performance of available technologies CMOS technology and design.
Integrated circuits were made possible by experimental discoveries which showed that
• The microelectronics evolution The techniques employed in nMOS technology for logic design are similar to GaAs technology..
semiconductor devices could perform the functions of vacuum tubes and by mid-20th-century
• SIA Roadmap Therefore, understanding the basics of nMOS design will help in the layout of GaAs circuits
technology advancements in semiconductor device fabrication.
In addition to VLSI technology, the VLSI design processes also provides a new degree of
The integration of large numbers of tiny transistors into a small chip was an enormous • Semiconductor Manufacturers 2001 Ranking
freedom for designers which helps for the significant developments. With the rapid advances in
improvement over the manual assembly of circuits using electronic components.
technology the the size of the ICs is shrinking and the integration density is increasing.
The integrated circuits mass production capability, reliability, and building-block approach to
Circuit Technology The minimum line width of commercial products over the years is shown in the graph below.
circuit design ensured the rapid adoption of standardized ICs in place of designs using discrete
transistors.

An integrated circuit (IC) is a small semiconductor-based electronic device consisting of

IC Technology
fabricated transistors, resistors and capacitors. Integrated circuits are the building blocks of
most electronic devices and equipment. An integrated circuit is also known as a chip or Bipolar CMOS BiCMOS SOI SiGe GaAs
microchip.
There are two main advantages of ICs over discrete circuits: cost and performance. Cost is Category BJT CMOS
Lower
low because the chips, with all their components, are printed as a unit by photolithography rather Power Moderate less Power
Dissipation
than being constructed one transistor at a time. Furthermore, much less material is used to construct a Dissipation to High
Speed Faster Fast Appr. High
packaged IC die than a discrete circuit. Performance is high since the components switch quickly and Equal rise packing The graph shows a significant decrease in the size of the chip in recent years which implicitly
consume little power (compared to their discrete counterparts) because the components are small and Gm 4ms 0.4ms and fall Why density
time CMOS indicates the advancements in the VLSI technology.
positioned close together. As of 2006, chip areas range from a few square millimeters to around 350 Switch poor Good
mm2, with up to 1 million transistors per mm
implementation ?
Techn ology slower Faster Fully
Scaledown
improvement restored
logic levels moreeasily

Unit -1 IC Technologies, MOS & Bi CMOS Circuits Unit -1 IC Technologies, MOS & Bi CMOS Circuits Unit -1 IC Technologies, MOS & Bi CMOS Circuits

MOS Transistor Symbol: NMOS FABRICATION

The following description explains the basic steps used in the process of fabrication.
(a) The fabrication process starts with the oxidation of the silicon substrate.
It is shown in the Figure 1.9 (a).
(b) A relatively thick silicon dioxide layer, also called field oxide, is created on the surface of the
substrate. This is shown in the Figure 1.9 (b).
(c) Then, the field oxide is selectively etched to expose the silicon surface on which the MOS
transistor will be created. This is indicated in the Figure 1.9 (c).
(d) This is followed by covering the surface of substrate with a thin, high-quality oxide layer, which
will eventually form the gate oxide of the
MOS transistor as illustrated in Figure 1.9 (d).
(e) On top of the thin oxide, a layer of polysilicon (polycrystalline silicon) is deposited as is shown in
the Figure 1.9 (e). Polysilicon is used both as gate electrode material for MOS transistors and also as
an interconnect medium in silicon integrated circuits. Undoped polysilicon has relatively high
resistivity. The resistivity of polysilicon can be reduced, however, by doping it with impurityatoms.
(f) After deposition, the polysilicon layer is patterned and etched to form the interconnects and the
MOS transistor gates. This is shown in Figure 1.9 (f).
(g) The thin gate oxide not covered by polysilicon is also etched along, which exposes the bare
silicon surface on which the source and drain junctions are to be formed (Figure 1.9 (g)).
(h) The entire silicon surface is then doped with high concentration of impurities, either through
ENHANCEMENT AND DEPLETION MODE MOS TRANSISTORS CMOS FABRICATION:
diffusion or ion implantation (in this case with donor atoms to produce n-type doping). Diffusion is
achieved by heating the wafer to a high temperature and passing the gas containing desired impurities
MOS Transistors are built on a silicon substrate. Silicon which is a group IV material is the CMOS fabrication can be accomplished using either of the three technologies:
over the surface. Figure 1.9 (h) shows that the doping penetrates the exposed areas on the silicon
eighth most common element in the universe by mass, but very rarely occurs as the pure free element • N-well technologies/P-well technologies
surface, ultimately creating two n-type regions (source and drain junctions) in the p-type substrate.
in nature. It is most widely distributed in dusts, sands, planetoids, and planets as various forms of • Twin well technology
The impurity doping also penetrates the polysilicon on the surface, reducing its resistivity.
silicon dioxide (silica) or silicates. It forms crystal lattice with bonds to four neighbours. Silicon is a • Silicon On Insulator (SOI)
(i) Once the source and drain regions are completed, the entire surface is again covered with an
semiconductor. Pure silicon has no free carriers and conducts poorly. But adding dopants to silicon
insulating layer of silicon dioxide, as shown in
increases its conductivity. If a group V material i.e. an extra electron is added, it forms an n-type The fabrication of CMOS can be done by following the below shown twenty steps, by which CMOS
Figure 1.9 (i).(j) The insulating oxide layer is then patterned in order to provide contact windows for
semiconductor. If a group III material i.e. missing electron pattern is formed (hole), the resulting can be obtained by integrating both the NMOS and PMOS transistors on the same chip substrate. For
the drain and source junctions, as illustrated in Figure 1.9 (j).
semiconductor is called a p-type semiconductor. integrating these NMOS and PMOS devices on the same chip, special regions called as wells or tubs

A junction between p-type and n-type semiconductor forms a conduction path. Source and are required in which semiconductor type and substrate type are opposite to each other.

Drain of the Metal Oxide Semiconductor (MOS) Transistor is formed by the “doped” regions on the
 Unit -1 IC Technologies, MOS & Bi CMOS Circuits Unit -1 IC Technologies, MOS & Bi CMOS Circuits
Unit -1 IC Technologies, MOS & Bi CMOS Circuits

Vgs = 0 depletion mode characteristic curve is superimposed on the family of curves for the there exists a short time when both Q1 and Q2 are on, making a direct path from the supply
Basic Electrical Properties of MOS and Bi CMOS circuits enhancement mode device and from the graph it can be seen that , maximum voltage across the (VDD) to the ground. This results to a current spike that is large and has a detrimental effect on
enhancement mode device corresponds to minimum voltage across the depletion mode transistor. both the noise and power consumption, which makes the turning off of the bipolar transistor
ID-VDS Characteristics of MOS Transistor : fast .
The graph below shows the ID Vs VDS characteristics of an n- MOS transistor for several values of Comparison of BiCMOS and C-MOS technologies
VGS .It is clear that there are two conduction states when the device is ON. The saturated state and The BiCMOS gates perform in the same manner as the CMOS inverter in terms of power
the non-saturated state. The saturated curve is the flat portion and defines the saturation region. For consumption, because both gates display almost no static power consumption.
Vgs < VDS + Vth, the nMOS device is conducting and ID is independent of VDS. For Vgs > VDS + When comparing BiCMOS and CMOS in driving small capacitive loads, their performance are
Vth, the transistor is in the non-saturation region and the curve is a half parabola. When the transistor comparable, however, making BiCMOS consume more power than CMOS. On the other hand,
is OFF (Vgs < Vth), then ID is zero for any VDS value. driving larger capacitive loads makes BiCMOS in the advantage of consuming less power than
CMOS, because the construction of CMOS inverter chains are needed to drive large capacitance
loads, which is not needed in BiCMOS.
The BiCMOS inverter exhibits a substantial speed advantage over CMOS inverters, especially
when driving large capacitive loads. This is due to the bipolar transistor’s capability of
From the graph it is clear that as Vin(=Vgs p.d. transistor) exceeds the Pulldown threshold voltage
effectively multiplying its current.
current begins to flow. The output voltage Vout thus decreases and the subsequent increases in Vin
For very low capacitive loads, the CMOS gate is faster than its BiCMOS counterpart due to
will cause the Pull down transistor to come out of saturation and become resistive.
small values of Cint. This makes BiCMOS ineffective when it comes to the implementation of
CMOS Inverter: internal gates for logic structures such as ALUs, where associated load capacitances are small.
The inverter is the very important part of all digital designs. Once its operation and properties are
BiCMOS devices have speed degradation in the low supply voltage region and also BiCMOS is
clearly understood, Complex structures like NAND gates, adders, multipliers, and microprocessors
having greater manufacturing complexity than CMOS.
can also be easily done. The electrical behavior of these complex circuits can be almost completely
derived by extrapolating the results obtained for inverters. As shown in the diagram below the CMOS
transistor is designed using p-MOS and n-MOS transistors.

The boundary of the saturation/non-saturation bias states is a point seen for each curve in the graph as
the intersection of the straight line of the saturated region with the quadratic curve of the non-
saturated region. This intersection point occurs at the channel pinch off voltage called VDSAT. The
diamond symbol marks the pinch-off voltage VDSAT for each value of VGS. VDSAT is defined as
the minimum drain-source voltage that is required to keep the transistor in saturation for a given VGS
.In the non-saturated state, the drain current initially increases almost linearly from the origin before
bending in a parabolic response. Thus the name ohmic or linear for the non- saturated region.
The drain current in saturation is virtually independent of VDS and the transistor acts as a current

41

Unit-2 VLSI Circuit Design Processes Unit-2 VLSI Circuit Design Processes Unit-2 VLSI Circuit Design Processes

VLSI DESIGN FLOW Front-end design (Logical design): MOS LAYERS

1. Design entry – Enter the design in to an ASIC design system using a hardware description
A design flow is a sequence of operations that transform the IC designers’ intention (usually MOS design is aimed at turning a specification into masks for processing silicon to meet the
language (HDL) or schematic entry
represented in RTL format) into layout GDSII data. specification. We have seen that MOS circuits are formed on four basic layers
2. Logic synthesis – Generation of net list (logic cells and their connections) from HDL code.
A well-tuned design flow can help designers go through the chip-creation process relatively smoothly  N-diffusion
and with a decent chance of error-free implementation. And, a skilful IC implementation engineer Logic synthesis consists of following steps: (i) Technology independent Logic optimization (ii)
 P-diffusion
can use the design flow creatively to shorten the design cycle, resulting in a higher likelihood that the Translation: Converting Behavioral description to structural domain (iii) Technology mapping or
 Poly Si
product will catch the market window. Library binding
 Metal
3. System partitioning - Divide a large system into ASIC-sized pieces
which are isolated from one another by thick or thin (thinox) silicon silicon dioxide insulating
4. Pre-layout simulation - Check to see if the design functions correctly. Gate level
layers. The thin oxide (thinox) mask region includes n-diffusion, p-diffusion, and transistor
functionality and timing details can be verified.
channels. Polysilicon and thinox regions interact so that a transistor is formed where they cross
Back-end design (Physical design):
one another.
5. Floor planning - Arrange the blocks of the netlist on the chip
STICK DIAGRAMS
6. Placement - Decide the locations of cells in a block
7. Routing - Make the connections between cells and blocks A stick diagram is a diagrammatic representation of a chip layout that helps to abstract a model
8. Circuit Extraction - Determine the resistance and capacitance of the interconnect for design of full layout from traditional transistor schematic. Stick diagrams are used to convey
9. Post-layout simulation - Check to see the design still works with the added loads of the the layer information with the help of a color code.
interconnect “A stick diagram is a cartoon of a layout.”
Partitioning The designer draws a freehand sketch of a layout, using colored lines to represent the various
process layers such as diffusion, metal and polysilicon. Where polysilicon crosses diffusion,
transistors are created and where metal wires join diffusion or polysilicon, contacts are formed.
For example, in the case of nMOS design,
 Green color is used for n-diffusion
 Red for polysilicon
 Blue for metal
 Yellow for implant, and black for contact areas.
Monochrome encoding is also used in stick diagrams to represent the layer information.

2 3 4
Unit-2 VLSI Circuit Design Processes Unit-2 VLSI Circuit Design Processes Unit-2 VLSI Circuit Design Processes

CMOS Design Style: Design Rules and Layout Layout Diagrams for NMOS and CMOS Inverters and Gates
The CMOS design rules are almost similar and extensions of n-MOS design rules except the
In VLSI design, as processes become more and more complex, need for the designer to
Implant (yellow) and the buried contact (brown). In CMOS design Yellow is used to identify p
understand the intricacies of the fabrication process and interpret the relations between the
transistors and wires, as depletion mode devices are not utilized. The two types of transistors 'n'
different photo masks is really troublesome. Therefore, a set of layout rules, also called design
and 'p', are separated by the demarcation line (representing the p-well boundary) above which all
rules, has been defined. They act as an interface or communication link between the circuit
p-type devices are placed (transistors and wires (yellow). The n-devices (green) are consequently
designer and the process engineer during the manufacturing phase. The objective associated with
placed below the demarcation line and are thus located in the p-well as shown in the diagram
layout rules is to obtain a circuit with optimum yield (functional circuits versus non-functional
below.
circuits) in as small as area possible without compromising reliability of the circuit. In addition,
Design rules can be conservative or aggressive, depending on whether yield or performance is
desired. Generally, they are a compromise between the two. Manufacturing processes have their
inherent limitations in accuracy. So the need of design rules arises due to manufacturing
problems like –
• Photo resist shrinkage, tearing.
• Variations in material deposition, temperature and oxide thickness.
• Impurities.
• Variations across a wafer.
Diffusion paths must not cross the demarcation line and n-diffusion and p-diffusion wires must
These lead to various problems like :
not join. The 'n' and 'p' features are normally joined by metal where a connection is needed. Their • Transistor problems:
geometry will appear when the stick diagram is translated to a mask layout. However, one must not forget Variations in threshold voltage: This may occur due to variations in oxide thickness, ion- Basic Gate Design
to place crosses on VDD and Vss rails to represent the substrate and p-well connection respectively. The implantation and poly layer. Changes in source/drain diffusion overlap. Variations in
substrate.
design style is explained by taking the example the design of a single bit shift register. The design begins
• Wiring problems:
with the drawing of the VDD and Vss rails in parallel and in metal and the creation of an (imaginary) Diffusion: There is variation in doping which results in variations in resistance,
demarcation line in-between, as shown in Fig.below. The n-transistors are then placed below this line and capacitance. Poly, metal: Variations in height, width resulting in variations in resistance,

thus close to Vss, while p-transistors are placed above the line and below VDD In both cases, the capacitance. Shorts and opens.
• Oxide problems:
transistors are conveniently placed with their diffusion paths parallel to the rails (horizontal in the
Variations in height.
diagram) as shown in Fig.(b). A similar approach can be taken with transistors in symbolic form.
Lack of planarity.

• Via problems:
Via may not be cut all the way through.

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Unit-2 VLSI Circuit Design Processes Unit-2 VLSI Circuit Design Processes Unit-2 VLSI Circuit Design Processes

Layout & Stick Diagram of CMOS Inverter 2 input NOR gate

Scaling of MOS circuits

2 input NAND gate

31 32 33
Unit-3 Gate level design & Basic circuit concepts Unit-3 Gate level design & Basic circuit concepts Unit-3 Gate level design & Basic circuit concepts

CMOS Logic gates and other complex gates Examples:

CMOS Static logic

CMOS logic gate concept:

Design Procedure:

2 3 4

UNIT 4 Carry-Ripple Adder: An N-bit adder can be constructed by cascading N full adders for N = 4. This is called a hot shift amount. In practice, multiplexers with more than 4–8 inputs have excessive parasitic capacitance, so they
carry-ripple adder (or ripple-carry adder). The carry-out of bit i, Ci , is the carry-in to bit i + 1. This carry is said to are faster to construct from logv N levels of v-input multiplexers. This is called a logarithmic shifter.
Subsystem Design: have twice the weight of the sum Si. The delay of the adder is set by the time for the carries to ripple through the N
stages, so the tCq Cout delay should be minimized. VLSI Design Styles
Datapath operators benefit from the structured design principles of hierarchy, regularity, modularity, and locality.
Every other stage operates on complementary data. The delay inverting the adder inputs or sum outputs is off the Several design styles can be considered for chip implementation of specified algorithms or logic functions. Each
They may use N identical circuits to process N-bit data. Related data operators are placed physically adjacent to
critical ripple-carry path. design style has its own merits and shortcomings, and thus a proper choice has to be made by designers in order to
each other to reduce wire length and delay. Generally, data is arranged to flow in one direction, while control signals
provide the specified functionality at low cost and in a timely manner.
are introduced in a direction orthogonal to the dataflow. Common data path operators include adders, one/zero
detectors, comparators, counters, Boolean logic units, error-correcting code blocks, shifters, and multipliers.
Field Programmable Gate Array (FPGA) Fully fabricated FPGA chips containing thousands or even more, of
logic gates with programmable interconnects, are available to users for their custom hardware programming to
Adder: Addition forms the basis for many processing operations, from ALUs to address generation to realize desired functionality. This design style provides a means for fast prototyping and also for cost-effective chip
multiplication to filtering. As a result, adder circuits that add two binary numbers are of great interest to digital design, especially for low-volume applications. A typical field programmable gate array (FPGA) chip consists of I/O
system designers. Half adders and full adders for single-bit addition. The half adder adds two single-bit inputs, A
buffers, an array of configurable logic blocks (CLBs), and programmable interconnect structures. The programming
and B. The result is 0, 1, or 2, so two bits are required to represent the value; they are called the sum S and carry-out
of the interconnects is accomplished by programming of RAM cells whose output terminals are connected to the
Cout.
gates of MOS pass transistors. Thus, the signal routing between the CLBs and the I/O blocks is accomplished by
Magnitude Comparator setting the configurable switch matrices accordingly. The general architecture of an FPGA chip from Xilinx .
A magnitude comparator determines the larger of two binary numbers. To compare two unsigned numbers A and B, showing the locations of switch matrices used for interconnect routing.
compute B – A = B + A + 1. If there is a carry-out, A f B; otherwise, A > B. A zero detector indicates that the
numbers are equal.

The carry-out is equivalent to a carry-in to the next more significant column of a multibit adder, so it can be
described as having double the weight of the other bits. If multiple adders are to be cascaded, each must be able to
receive the carry-in. Such a full adder has a third input called C or Cin.

Gate Array Design :In terms of fast prototyping capability, the gate array (GA) ranks second after the FPGA with a
Shifters: typical turn-around time of a few days. While user programming is central to the design implementation of the
FPGA chip, metal mask design and processing is used for GA. Gate array implementation requires a two-step
Shifts can either be performed by a constant or variable amount. Constant shifts are trivial in hardware, requiring manufacturing process: The first phase, which is based on generic (standard) masks, results in an array of
only wires. They are also an efficient way to perform multiplication or division by powers of two. A variable shifter uncommitted transistors on each GA chip. These uncommitted chips can be stored for later customization, which is
takes an N-bit input, A, a shift amount, k, and control signals indicating the shift type and direction. It produces an completed by defining the metal interconnects between the transistors of the array. Since the patterning of metallic
N-bit output, Y. There are three common types of variable shifts, each of which can be to the left or right: Rotate: interconnects is done at the end of the chip fabrication process, the turn-around time can still be short, a few days to
Rotate numbers in a circle such that empty spots are filled with bits shifted off the other end a few weeks. A corner of a gate array chip which contains bonding pads on its left and bottom edges, diodes for 1O
○ Example: 1011 ROR 1 = 1101; 1011 ROL 1 = 0111 protection, nMOS transistors and pMOS transistors for chip output driver circuits adjacent to bonding pads, arrays
N-bit adders take inputs {AN, ..., A1}, {BN, ..., B1}, and carry-in Cin, and compute the sum {SN, ..., S1} and the
Logical shift: Shift the number to the left or right and fills empty spots with zeros. of nMOS transistors and pMOS transistors, underpass wire segments, and power and ground buses along with
carry-out of the most significant bit Cout. They are called carry-propagate adders (CPAs) because the carry into
○ Example: 1011 LSR 1 = 0101; 1011 LSL 1 = 0110 contact windows. The availability of these routing channels simplifies the interconnections, even using one metal
each bit can influence the carry into all subsequent bits.
Arithmetic shift: Same as logical shifter, but on right shifts fills the most significant bits with copies of the sign bit layer only. Interconnection patterns that perform basic logic gates can be stored in a library, which can then be used
(to properly sign, extend two’s complement numbers when using right shift by k for division by 2k). to customize rows of uncommitted transistors according to the netlist.
○ Example: 1011 ASR 1 = 1101; 1011 ASL 1 = 0110
Conceptually, rotation involves an array of N N-input multiplexers to select each of the outputs from each of the
possible input positions. This is called an array shifter. The array shifter requires a decoder to produce the 1-of-N-
 UNIT-V existing systems rely on Boolean logic representations of circuits and stuck-at fault modeling.
CMOS TESTING
Observability
Need for testing
The observability of a particular circuit node is the degree to which you can observe
Design of logic integrated circuits in CMOS technology is becoming more and more complex since
VLSI is the interest of many electronic IC users and manufacturers. A common problem to be that node at the outputs of an integrated circuit (i.e., the pins). This metric is relevant when you
solved by both users and manufacturers is the testing of these ICs. want to measure the output of a gate within a larger circuit to check that it operates correctly.
Given the limited number of nodes that can be directly observed, it is the aim of good chip
designers to have easily observed gate outputs. Adoption of some basic design for test
techniques can aid tremendously in this respect. Ideally, you should be able to observe directly
or with moderate indirection (i.e., you may have to wait a few cycles) every gate output within
an integrated circuit. While at one time this aim was hindered by the expense of extra test
circuitry and a lack of design methodology, current processes and design practices allow you
to approach this ideal.
Testing can be expressed by checking if the outputs of a functional system (functional block,
Controllability
Integrated Circuit, Printed Circuit Board or a complete system) correspond to the inputs applied to
Standard-Cells Based Design: The standard-cells based design is one of the most prevalent full custom design
it. If the test of this functional system is positive, then the system is good for use. If the outputs are The controllability of an internal circuit node within a chip is a measure of the ease of
styles which require development of a full custom mask set. The standard cell is also called the polycell. In this different than expected, then the system has a problem: so either the system is rejected (Go/No Go
setting the node to a 1 or 0 state. This metric is of importance when assessing the degree of
design style, all of the commonly used logic cells are developed, characterized, and stored in a standard cell library. test), or a diagnosis is applied to it, in order to point out and probably eliminate the problem's
A typical library may contain a few hundred cells including inverters, NAND gates, NOR gates, complex AOI, OAI causes. difficulty of testing a particular signal within a circuit. An easily controllable node would be
gates, D latches, and flip-flops. Each gate type can be implemented in several versions to provide adequate driving Testing is applied to detect faults after several operations : design, manufacturing, packaging and directly settable via an input pad. A node with little controllability, such as the most significant
capability for different fan-outs. For instance, the inverter gate can have standard size, double size, and quadruple especially during the active life of a system, and thus since failures caused by wear-out can occur at
size so that the chip designer can choose the proper size to achieve high circuit speed and layout density. Each cell is any moment of its usage. bit of a counter, might require many hundreds or thousands of cycles to get it to the right state.
characterized according to several different characterization categories, including: Delay time versus load Design for Testability (DFT) is the ability of simplifying the test of any system. DFT could be Often, you will find it impossible to generate a test sequence to set a number of poorly
capacitance, Circuit simulation model, Timing simulation model, Fault simulation model, Cell data for place-and-
synthesized by a set of techniques and design guidelines where the goals are :
route, Mask data. To enable automated placement of the cells and routing of inter-cell connections, each cell layout controllable nodes into the right state. It should be the aim of good chip designers to make all
 minimizing costs of system production
is designed with a fixed height, so that a number of cells can be abutted side-by-side to form rows. The power and
 minimizing system test complexity : test generation and application nodes easily controllable. In common with observability, the adoption of some simple design
ground rails typically run parallel to the upper and lower boundaries of the cell, thus, neighboring cells share a
common power and ground bus. The input and output pins are located on the upper and lower boundaries of the cell.  improving quality for test techniques can aid in this respect tremendously. Making all flip-flops resettable via a
 Avoiding problems of timing discordance or block nature incompatibility. 
global reset signal is one step toward good controllability.

Fault Coverage
In the production process cycle, a fault can occur at the chip level. If a test strategy is considered at
the beginning of the design, then the fault could be detected rapidly, located and eliminated at a A measure of goodness of a set of test vectors is the amount of fault coverage it
very low cost. When the faulty chip is soldered on a printed circuit board, the cost of fault remedy
would be multiplied by ten. And this cost factors continues to apply until the system has been achieves. That is, for the vectors applied, what percentages of the chip’s internal nodes
assembled and packaged and then sent to users.
werechecked? Conceptually, the way in which the fault coverage is calculated is as follows.
Each circuit node is taken in sequence and held to 0 (S-A-0), and the circuit is simulated
with thetest vectors comparing the chip outputs with a known good machine––a circuit with
Full Custom Design no nodes artificially set to 0 (or 1). When a discrepancy is detected between the faulty
Although the standard-cells based design style is sometimes called full custom design, in a strict sense, it is
somewhat less than fully customized since the cells are pre-designed for general use and the same cells are utilized machine and thegood machine, the fault is marked as detected and the simulation is stopped.
This is repeatedfor setting the node to 1 (S-A-1). In turn, every node is stuck (artificially) at
1 and 0 sequentially. The fault coverage of a set of test vectors is the percentage of the total
nodes that can be detected as faulty when the vectors are applied. To achieve world-class

quality levels, circuits are required to have in excess of 98.5% fault coverage. The
Verification MethodologyManual is the bible for fault coverage techniques.

IDDQ TESTING: It is a simple method to identify defects on IC on the steady state

power supply current. It is also a method for testing CMOS integrated circuits for the presence
of manufacturing faults. It relies on measuring the supply current (Idd) in the quiescent state
(when the circuit is not switching and inputs are held at static values). The current consumed
in the state is commonly called Iddq for Idd (quiescent) and hence the name. Iddq testing uses
the principle that in a correctly operating quiescent CMOS digital circuit, there is no static
current path between the power supply and ground, except for a small amount of leakage. Many
common semiconductor manufacturing faults will cause the current to increase by orders of
magnitude, which can be easily detected. This has the advantage of checking the chip for many
possible faults with one measurement. Another advantage is that it may catch faults that are
not found by conventional stuck-at fault test vectors. Iddq testing is somewhat more complex
than just measuring the supply current. If a line is shorted to Vdd, for example, it will still draw
no extra current if the gate driving the signal is attempting to set it to '1'. However, a different
vector set that attempts to set the signal to 0 will show a large increase in quiescent current,
signaling a bad part. Typical Iddq test vector sets may have 20 or so vectors. Note that Iddqtest
vectors require only controllability, and not observability. This is because the observability is
through the shared power supply connection. Iddq testing has many advantages:

□ It is a simple and direct test that can identify physical defects.

□ The area and design time overhead are very low.

□ Test generation is fast.