Important interfacing IC’S

• 8251- USART- Universal Synchronous

Asynchronous Receiver and Transmitter
• 8253/54- Programmable timer / counter
• 8255-PPI/PIO-Parallel i/p o/p device
• 8257/37- DMA controller
• 8259-PIC-Priority Interrupt controller
• 8279- Keyboard/Display controller
• 8155– Multipurpose programmable I/o device
Mother board of a computer

8251 8259

Microprocessor
Or
CPU

8257 8255 8253

33 Q. How is serial data transmitted in
asynchronous mode using 8251.
8251: Universal Synchronous Asynchronous
Receiver and Transmitter
Features:
>Used for serial Communication between
Microprocessor and Serial peripherals
>also known as communication Interface
>Decides data format for transmission
>In asynchronous mode, one start bit, 8 bit
data and 1 or 2 stop bits are transmitted
RS232C is a Serial Communication Standard
RS – Recommended standard for serial comm...
• Features of RS232C:

 Speed: 20kbauds(Baud = symbols /sec)

 Distance: 50feet
 Voltage levels:
Logic 0-- +3v to +25v
Logic 1-- -3v to -25v
But TTL logic levels are different, so line drivers are
required. Ex. MAX232 IC (converts RS 232C signals
to TTL levels and TTL to RS232C signals)
Asynchronous form of data transmission:

Stop bit is always 1

Stop bit is 1 bit or 1

Start bit is always 0 1 ½ bit or 2 bit duration

Assume that the data is transmitted from transmitter to receiver from LSB,
for every single byte start and stop bits will be present so overhead ( extra
data is more) . The number of stop bits can be set by control word in 8251.
8253/54-ProgrammableTimer/Counter

Used for applications which require timing and

counting operations
Ex: Real time clock, Event counter, Square and
complex waveforms generator and to measure
delay between external events
Has 3 timers/counters-T0,T1,T2
24 PIN IC, +5V DC Supply
Can operate in 6 modes
 Each counter has 3 pins:
Clock- i/p clock
Gate – to start or stop the counter; 1- 0n; 0-off
OUT - o/p signal

 Modes of operation:
1. Mode0- Interrupt on terminal count
2. Mode1- Programmable one shot/hardware
re-triggerable
3. Mode2- Rate generator
4. Mode3- Square wave generator
5. Mode4- Software triggered strobe
6. Mode5- Hardware triggered strobe
 Modes & similarities
• Count & Gate signal is required to start the mode, in some
modes when GATE is on/off , its count changes at o/p.

Mode-0: When GATE—1, count loaded, in next clock for every one
clock, count decrements and finally an interrupt is generated. If
GATE-0, while running , count also stops for that many clocks ,
when GATE – 1 again , count starts.

Mode-4 : Mode-0 & Mode-4 are same except, strobe signal is

generated instead of an interrupt.

Mode-1 : Even the count is loaded, GATE –1(must), then only count
starts decrementing, if GATE is off while running, count continues
but when GATE is on , then count restarts again , that is why it is
known as re-triggerable.
Mode-5 : Similar to Mode-1 , except that a strobe signal is
generated.

Mode -2 : When count starts, in the last clock , o/p is low for
one clock period but this mode is auto-reloadable, again the
count starts and continues.

Mode-3 : If the count is odd then o/p will be n+1/2 clocks high
and n-1/2 clocks low.
If the count is even then n/2 clocks , o/p will be high and n/2
clocks o/p will be low.

Mode -2 & 3 are auto-reloadable so count is automatically

reloaded when it becomes 0.
WRn 3
GATE

O/P 3 2 1 0
O/P COUNT
3 STOPS 2 1 0

WRn 3

GATE
O/P 3 2 1 0

GATE
O/P 3 2 3 2 1 0
WRn 3
3 2 1 3 2 1
O/P 0 0

GATE

O/P
3 2 3 2 1 0

WRn 3

1 1 1
0 0
O/P
1 1 1 1
O/P
WRn 3
3 2 1 0
O/P
STROBE
GATE

O/P
COUNT
3 STOPS 2 1 0 STROBE

WRn 3

GATE 3 2 1 0
O/P

GATE
O/P
3 2 3 2 1 0
 34 Q. What do mean by handshaking
signals . Explain with example using 8255
PPI
• 8255-PPI/PIO
-Programmable Peripheral Interface or
Parallel i/p o/p device
Features:
 Has 24 i/o lines , i.e 3 ports-PortA,PortB,PortC
Port C- can be 4bit/ 8 bit Port
Group A signals->PA and PC7- PC4
Group B signals-> PB and PC3- PC0
Select lines A1 and A0 are used to select port
and CWR(Control Word Register)
 CS A1 A0 SELECTION
0 0 0 PORT-A
0 0 1 PORT-B
0 1 0 PORT-C
0 1 1 CWR
 Modes of operation
1.BSR Mode: Bit Set Reset Mode
 Only Port C pins can be used to make 0/1
2.I/O Mode
 Mode 0: Simple I/O mode
Any ports can be used as i/p or o/p
 Mode 1: Strobed I/O mode
(strobed mode indicates , communication with
acknowledgements).
PA and PB ---- i/p or o/p
PC--- Control/ Handshake signals for PA & PB
 Mode 2: Strobed Bi-directional I/O Mode
PA–> Bi-Directional Port
PB-> i/p or o/p port
PC- >to generate control signals.

Ex : BSR mode .
find control word to ‘set’ PC7.
D7 – D0 bits in control word would be
0 0 0 0 1 1 1 1 = 0 FH loaded into control word
register.
 INTR STB
INTR i/p
Device
IBF
8255
8085
OBF

o/p Device
ACK

Handshake or Control Signals for Data transfer

8257/37- DMA CONTROLLER
 Used to transfer more data between Memory and I/O
devices at faster rate.
 8257 can support 4 channels of 16kB each, where as
8237 can support 4 channels
 Each channel has address and count register. Once the
count and address is loaded , data transfer takes place
till the count becomes 0000H.
 Modes : 1. Burst mode
2. Cycle stealing technique
3. Interleaved DMA
35Q. What is the advantage of 8259 over
normal interrupt mechanism with
respect to microprocessor.
Signals associated with 8259 to respond
an interrupt
8259- PIC- Priority Interrupt Controller
 Used to increase the interrupt handling capability of
a processor.
 Can support 8 i/o devices in interrupt mode
- highest priority is IR0(Interrupt Request)
 Maximum of 64 i/o devices can be possible.
 Modes of operation:
1. Fully nested mode. –IR0 has highest priority
2. Automatic rotation mode---device after service
receives least priority
3. Specific rotation mode---similar to automatic but
user can select any IR for the lowest priority
Operation:(clue:Microprocessor requires instruction
for every operation)
• Similar to INTR where opcode of RSTn is placed,
here opcode of CALL and 16 bit address is placed
after receiving INTA from microprocessor.
• So, 3 INTA’s are required to go to actual ISR after the
interrupt is triggered as CALL is 3 byte instruction.
• In cascaded mode Master places the slave address
so the slave will send the address, depending on ISR.
• ISR can be present at any location in memory unlike
vector address in case of vectored interrupts
[HIGHER BYTE CALL ADDRESS]
3
ICW4: The use of this command word depends on the IC4
bit of ICW1. If IC4=1, IC4 is used, otherwise it is neglected.
The bit functions of ICW4 are described as follow:
• SFNM=1; special fully nested mode
If BUF = 1, the buffered mode is selected. In the buffered mode, SP/EN acts as
enable output and the master/slave is determined using the M/S bit of ICW4.
• M/S: If M/S = 1, 8259A is a master. If M/S =0, 8259A is slave.
If BUF = 0, M/S is to be neglected.
• AEOI: If AEOI = 1, the automatic end of interrupt mode is
Selected.
μPM : If the μPM bit is 0, the Mcs-85 system operation is
selected and if μPM=1, 8086/88 operation is selected.
 Operation Command words
• There are 3 OCW’S
• OCW-1 ---To mask the interrupts connected to
8259
OCW 2--- To select level of interrupt and mode
of operation
OCW3---- To enable special mask mode and
poll command
 µp 8259
3. INTA

INTR INT IR0 I/O 1

8085 8259

INTA INTA
IR7 I/O 8
 IR0

INTR INT IR0 8259

SLAVE IR7

8085 8259
MASTER
IR0
INTA INTA
IR7 8259
SLAVE IR7

Interrupt procedure for cascaded mode—Maximum 64

i/o devices are possible by using 9(nine) 8259’s.
8279-keyboard/ Display controller
Used to Interface keyboard or a display to the
processor

8155- Multipurpose Programmable I/O Device

 3 Ports- PA & PB(8 bits),PC-6bits
256B RAM
One timer/counter- Can operate in 4modes
Has 14bit down counter
 6

(14 bit timer) 6 bit port

 Calculation of Count
Clock period = 1/3x106 = 330ns
Pulse period
• Timer count = -----------------
Clock period
Ex. If 100µs of square wave pulse width is
required then (pulse period will be 200µs)
Timer count = (100x2)x10-6 /330x10-9
= 606=025E H
If decoding logic for Timer LSB = 24H
Timer MSB = 25H
• Then LSB is 5Eh
• MSB is calculated as
M2 M1 T13 T12 T11 T10 T9 T8
0 1 0 0 0 0 1 0 = 42H
Control word is D7 D6 D5 D4 D3 D2 D1 D0
1 1 0 0 0 0 1 1
i.e C3 H
Instructions required to generate a square wave:
MVI A, 5EH; initializing LSB
OUT 24 H
MVI A, 42H ; Intializing MSB
OUT 25H
MVI A, C3H; Start the counter in Mode 1( Square wave)
OUT 20H
HLT
 Timer/Counter Modes
• Mode 0- Single square wave-

• Mode 1- Square Wave-

• Mode 2- Pulse on terminal count-

• Mode 3- Every pulse on terminal count-
 Applications of Microprocessors
1. Industrial process and control applications
2. Bio-medical instrumentation
 ECG and patient monitoring systems
 MRI, CT scanning systems.
3. Military and navigation equipment
 Radar control, communication
 Satellite and Rover systems in exploration.
4. Educational Institutes i.e laboratory purpose
5 Home appliances like TV, Intelligent washing machines,
fridges etc.
6 Automobile industry – Car high end applications like- Anti
braking system, cruise control .
7 Audio speech processing .
8 Electronic gadgets
9 Robotics and neural networks
• Assembler directives:
 These are hints given to assembler by programmer
while writing an assembly language program.
 ORG—origin, start program/data @ a location.
 DB – define byte – 1byte memory space is allocated
for the variable .
 Ex: x db 12h,34h/ x db 10h dup( 00 )—16 bytes are
allocated for variable ‘x’ and duplicated with 00.
 DW- define word –2bytes space
 DQ –define quadword
 EQU – equate ; pi EQU 3.14
 End –end of program, ENDS—end of segment
• Fields of an instruction:
• LABEL: MNEMONIC OPERANDS; STATEMENT
Between operands , must be used
Ex:Rep: DCR C ;Decrement the content of Reg--C
 Differences b/w 8085 & 8086
8085 8086
Type 8 bit µp 16 bit µp
Address lines 16 20
Data lines 8 16
Total memory 216 = 64KB 220 = 1 MB
Segmented M/M
Memory architecture Von-Neumann Von-Neumann
Operating frequrency 3 Mhz 5Mhz
Operating voltage + 5 V DC + 5V DC
Registers 8 bit & 16bit All are 16 bit
Flags 5—S,Z,AC,P,CY 9—O,D,I,T,S,Z,AC,P,CY
When reset , program 0000H FFFFO H
control transfers to
 8085 8086
Modes of operation ------- Minimum & Maximum

Interrupts 5 hardware & 8 Maximum -256

software
Interrupt Interval 8 bytes 4B x 256=1024B/1KB
Interrupt vector table
IC 40 PIN 40 PIN
Max length of 3 bytes 6 Bytes
Instruction
Pipelining technique Not possible possible
Multiplication & Not possible Possible
division
 Important features of 8086
It is a 16 bit processor, has 20 Address lines
Max memory that can be interfaced is 1MB
Follows Von-Neumann architecture
Operating voltage +5v DC supply
Frequency of operation5Mhz(5-8Mhz)
40 pin IC
MN/MX0- Maximum mode; 8086with others
1- Minimum mode; only 8086
All registers = 16bits
GDR’sGeneral Data reg’s--AX, BX, CX, DX
AX--Accumulator, default register in Mul..& Div..
BX -- Offset pointer
CX– Default counter
DX– Default register in multiplication and divisions
Special purpose Registers:
1. Segment Registers:
 CS-Code segment register
 DS- Data segment register
 SS-Stack segment register
 ES- Extra segment register
2. Pointer & Index registers:
IP – Instruction Pointer(Similar to PC in 8085)r
SP– Stack Pointer
BP—Base Pointer
SI- Source index register; used in string instructions
DI—Destination index register; used in string
instructions
3. Flag Register:
D15 D14 ------------------------D7 --------------------D1 D0
X X X X O D I T S Z X A X P X C
C Y
• T- Trap flag 1; Single step execution mode; Processor
stops after every instruction, such that results of the
registers can be verified.
• I- Interrupt1; Maskable interrupts are
recognised
0; Not recognised
Ex; INTR
• D- Direction : Used in string manipulation instructions
0; Auto increment mode; String is
processed from lower address to higher.
1;Auto decrement mode; Processed from
higher address to lower address.
• O- Overflow 1; if destination register is not able to hold
result of a signed operation.
 Maximum interrupts possible = 256
 If reset , the processor is initialised at FFFFOh
 ALE=1; All 20 lines  Address bus
=0; A19 – A16  status signals
AD15 -- AD0 Data bus
 Maximum length of Instruction---6Bytes
 Has 6bytes of Instruction byte queue in which
maximum length of instruction can be pre-fetched.

 Pipelining Technique:
More than one instruction can be at different
stages of execution at a single interval of time, so
speed increases.
 36 Q. Explain the significance of
effective address calculation in 8086
 Memory Segmentation
• 1 MB of memory is divided into 16 logical segments
of each 64KB.
• Base Address: It indicates the starting location of a
particular segment. It is present in Segment
registers.
• Offset Address : It is the distance of required
memory location from the beginning of the
segment. It is present in offset or index registers.
• Physical/Effective Address: It is the distance of
required memory location from the beginning of
memory.
• Physical address calculation:
1. Shift the Base/Segment address by 4 bit
locations left or 1 hexadecimal digit.
Shifting is equalent to multiplying CS by 10H.
2.Add the offset address to the shifted segment
value.
Ex: CS 9000H & IP 0FFF H
90000 H
+ 0FFF H
90FFF H
Effective Adrs Base Adrs 1MB
00000H 0000H 0000h
64KB

0FFFFH FFFFh
1000H
10000H 0000h
64KB

FFFFh
2000H
0000h
64KB

FFFFh

F000H
0000h
64KB
FFFFFH
FFFFh
 Registers to point Segment and offset addresses
1. Code Segment: To store program or code
 Base Address : CS
 Offset Address: IP
2. Data Segment: To store Data
 Base Address : DS
 Offset Address: BP/BX
3. Stack Segment: To store temporary data
 Base Address : SS
 Offset Address :SP
4. Extra Segment: Alternate Data segment
 Base Address : ES
 Offset Address: SI/DI
Range of segment address- 0000H to F000H
Range of offset address  0000H to FFFFH
 Addressing modes
• There are two types of instructions in 8086
1.Sequential flow ---8 modes
2. Control transfer--- 4 modes
Effective address: DS * 10H + offset address
1. Immediate --MOV AL, 80H; MOV AX,8000H
2. Direct ---MOV AL, [8000H]
3. Register---MOV AL, BL; MOV AX,BX
4. Register Indirect---MOV AL, [BX]
5. Register relative---MOV AL, 06H[BX]
6. Indexed---MOV AL, [SI]
7. Based Indexed--- MOV AL, [BX][SI]
8. Relative based indexed -- MOV AL, 07H[BX][SI]
Ex: Mathematically effective address can be
written as DS * 10H + offset address for data
segment.
Control transfer:
1. Intra segment – Program control is transferred
within the same segment
2. Inter segment – Program control is transferred
from one segment to another.
 Important Pins in 8086
• ALE – Address latch enable
 1; All 20 line --- As address bus
 0; A19 – A 16  status signals
AD15 – AD0  Data bus
AD15 – AD8 : Higher byte of Data bus
AD7 – AD0 : Lower byte of Data bus
BHE- Bus high enable,
-- 0; If AD15 – AD8 are used for Data/Address .
BHE is used along with A0 line for selecting the even or odd bank of
memory
BHE A0
0 0 --- whole word (Two bytes)
0 1 --- odd bank byte
1 0 ---- even bank bye
1 1 --- Not used
• DT/R–> Data transmit or receive for bidirectional
buffers
-- 0: Receive ; 1: transmit
• DEN  To enable the data buffers when data is
transmitted through AD15 – AD0 lines
• LOCK –> o/p signal , which indicates that Mp is
executing some important instruction having lock
prefix and buses can not be used by other system.
• TEST  0: then only processor executes further
instruction, used with WAIT instruction.
 Miscellaneous topics(for IES)
• Communication Interfaces
• Disadvantage of RS232C:
Slow in operation and can’t support voice data
synchronously
• Synchronous serial transfer protocols:
USART-Universal Synchronous Asynchronous
Receiver and Transmitter
SPI- Synchronous Peripheral Interface bus
IIC- Inter-Integrated circuit bus
CAN –Control Area Network bus
USB-Universal Serial Bus
 SPI
 Clock source is supplied only by transmitting device
 Receiving device must accept clock
 Transmitting Unit- Master
Receiving Unit – Slave
 Uses 3 wires for communication apart from the
ground.
MOSI: Master out slave in
MISO: Master in slave out
SCK : Clock source from master
SS : Slave select pin
 IIC BUS
2 Wire synchronous bus with
SCK—Clock signal(by Master)
SDA– Data signal by both Master and slave
 Used for inter IC Communication applications
Doesn’t require decoders as 7 bit address is
given for identifying slave
Multi master capability
 CAN
Developed by BOSCH –For multi-master
broadcast system having 1mega bit per sec
Used for Automotive industry to replace complex
wiring with 2 wire bus
Has robust noise immunity and fault tolerance
A node in the bus may have a Microcontroller,
CAN controller, CAN transceiver
Uses 4 different message types:
Data frame, remote frame , error frame and overload
frame
Suitable in applications requiring large short
messages with high reliability
CAN is message based not address based
 USB
 Advantages
1. One interface for many devices
2. Automatic configuration
3. No power supply required
4. Loss less data transfers
5. Speed can be up to 1.5 Mbps to 480 Mbps
6. Low power consumption
7. It is a packet based protocol- start frame ,
transactions and handshake signals with ack and
nak controls
8. Has 4 wires-Gnd, 2 data, power supply
Reference Books for Microprocessor:
8085: Ramesh .S. Gaonkar or B.Ram
8086: A.K.Ray
Interfacing IC’s: Data sheets ,Material given in the lectures
& Reference books.

Doubts can be posted to [email protected] if any.

“Taste your hard and smart work with a fruit of success”.

Thank you
B J Vijaya kumar. M.Tech
Faculty , Made Easy Education.