Slide 23
Slide 23
2018/19-1
Lecture 23
Diode applications:
iv) Clamper
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Clamper
A clamping circuit is a circuit to shift a waveform either
above or below a different dc level without distorting
the waveform.
The network has a capacitor, a diode and a resistor.
The magnitude of R and C must be chosen such that the
time constant t = RC is large enough to ensure that the
voltage across the capacitor does not discharge
significantly during the interval the diode is non-
conducting.
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SSCP 2313- Basic electronics 2012/13-1 2
Negative Clampers
Negative clamper shifts the input waveform so that the
signal is pushed downward by the circuit
- the positive peak of the input signal coincides with
the zero level.
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Operation of negative clamper
+ ve region
C
+ - • 0 - T/2: Diode is ON (shorted)
• Assume RC time is small and
+ capacitor charge to V volts
Vi R Vo
very quickly
• Vo=0 V (ideal diode)
Vi
V -
t
• T/2 -T: Diode is OFF
0 T/2 T
- ve region C
-V + - (opened)
V + + • Both for the stored voltage
across capacitor and applied
R
V Vo Vo signal current through
cathode to anode
- -
•KVL: Vo = -2V
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Positive Clampers
Positive clamper shifts the input waveform so that the
signal is pushed upward by the circuit
- the negative peak of the signal coincides with the
zero level.
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Operation of a positive clamper circuit:
C1
+ 2.5 V
D1
0V RL
ON
- 2.5 V
+ 5.0 V
RL I
D1
0V
OFF
(d) Output of clamper circuit
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Biased Clamping Circuits
• Biased clamper enable us to shift a waveform so
that it occurs above or below a DC reference voltage
other than 0 V.
C
Vm
Vo -Vm
Vs
VB 2Vm+VB
VB
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(b) Negative biased clamper
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Thank you…
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