EXPERIMENT – 1

Draw the Input Vs Output timing waveform after behavioral simulation:

Name of port Waveform

Input not_in

Output not_out

Observation after hardware implementation:

Input Output

not_in not_out

1
 EXPERIMENT – 2

AND GATE OR GATE

Input Output Input Output
a b and_out a b or_out
0 0 0 0 0 0
0 1 0 0 1 1
1 0 0 1 0 1
1 1 1 1 1 1

NAND GATE NOR GATE

Input Output Input Output
a b nand_out a b nor_out
0 0 1 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 0

XOR GATE XNOR GATE

Input Output Input Output
a b xor_out a b xnor_out
0 0 0 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 1

Observations:

S.N. Input Output

a b and_out nand_out or_out nor_out xor_out xnor_out
1 0 0
2 0 1
3 1 0
4 1 1
 EXPERIMENT – 3

Observations:

Half-Adder
Input Output
S.N.
A B carry_HA sum_HA
1 0 0
2 0 1
3 1 0
4 1 1

Full-Adder
Input Output
S.N.
A B C carry_FA sum_FA
1 0 0 0
2 0 0 1
3 0 1 0
4 0 1 1
5 1 0 0
6 1 0 1
7 1 1 0
8 1 1 1
 EXPERIMENT – 4

VHDL Code of 4-bit comparator

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity comparator4bit is
Port ( A : in STD_LOGIC_VECTOR(3 downto 0);
B : in STD_LOGIC_VECTOR(3 downto 0);
A_greater : out STD_LOGIC);
A_equal_B : out STD_LOGIC;
B_greater : out STD_LOGIC);
end comparator4bit;

architecture Behavioral of comparator4bit is

begin
process (A, B)
begin
if (A > B) then
A_greater <= ‘1’;
A_equal_B <= ‘0’;
B_greater <= ‘0’;
elsif (B > A) then
A_greater <= ‘0’;
A_equal_B <= ‘0’;
B_greater <= ‘1’;
else
A_greater <= ‘0’;
A_equal_B <= ‘1’;
B_greater <= ‘0’;
end if;
end process;
end Behavioral;
Observations

4-Bit Comparator
Input Output
S.N.
A B A_greater A_equal_B B_greater
1 0000 0010
2 0001 0000
3 0010 0101
4 0011 0011
5 0100 0001
6 0101 0111
7 0110 0001
8 0111 0111
9 1000 0101
10 1001 1100
11 1010 1100
12 1011 1011
13 1100 1011
14 1101 1111
15 1110 0111
16 1111 1101
 EXPERIMENT – 5

VHDL Code of 4-bit Binary to Gray Code Convertor

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity binary2gray is
Port ( A : in STD_LOGIC_VECTOR(3 downto 0);
Y : out STD_LOGIC_VECTOR(3 downto 0));
end binary2gray;

architecture Behavioral of binary2gray is

begin
Y[3] <= A[3];
Y[2] <= A[3] XOR A[2];
Y[1] <= A[2] XOR A[1];
Y[0] <= A[1] XOR A[0];
end Behavioral;

Observations:
4-Bit Binary to Gray Code Converter
Input Output
S.N. MSB … … … … LSB MSB … … … … LSB
A[3] A[2] A[1] A[0] Y[3] Y[2] Y[1] Y[0]
1 0 0 0 0
2 0 0 0 1
3 0 0 1 0
4 0 0 1 1
5 0 1 0 0
6 0 1 0 1
7 0 1 1 0
8 0 1 1 1
9 1 0 0 0
10 1 0 0 1
11 1 0 1 0
12 1 0 1 1
13 1 1 0 0
14 1 1 0 1
15 1 1 1 0
16 1 1 1 1
 EXPERIMENT – 6

VHDL Code of 4-bit Binary to Gray Code Convertor

- - VHDL Code of MUX2x1
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity MUX2x1 is
Port ( A, B : in STD_LOGIC;
S0 : in STD_LOGIC;
Y : out STD_LOGIC);
end MUX2x1;

architecture BEHAVIORAL of MUX2x1 is

begin
process (S0, A, B)
begin
case S0 is
when '0' => Y <= A;
when others => Y <= B;
end case;
end process;
end BEHAVIORAL;

- - VHDL Code of MUX4x1

library IEEE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity MUX4x1 is
Port ( A, B, C, D : in STD_LOGIC;
S0, S1 : in STD_LOGIC;
Y : out STD_LOGIC);
end MUX4x1;

architecture BEHAVIORAL of MUX4x1 is

begin
process (S0, S1, A, B, C, D)
begin
if (S0 = '0' AND S1 = '0') then
Y <= A;
elsif (S0 = '0' AND S1 = '1') then
Y <= B;
elsif (S0 = '1' AND S1 = '0') then
Y <= C;
else
Y <= D;
end if;
 end process;
end BEHAVIORAL;

- - VHDL Code of MUX8x1_MUX4x1

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity MUX8x1_MUX4x1 is
Port ( IN0, IN1, IN2, IN3, IN4, IN5, IN6, IN7 : in STD_LOGIC;
SEL0, SEL1, SEL2 : in STD_LOGIC;
Y_OUT : out STD_LOGIC);
end MUX8x1_MUX4x1;

architecture BEHAVIORAL of MUX8x1_MUX4x1 is

component MUX2x1 is
Port ( A, B : in STD_LOGIC;
S0 : in STD_LOGIC;
Y : out STD_LOGIC);
end component;
component MUX4x1 is
Port ( A, B, C, D : in STD_LOGIC;
S0, S1 : in STD_LOGIC;
Y : out STD_LOGIC);
end component;
signal sig1, sig2 : STD_LOGIC;
begin
comp1 : MUX4x1 port map
(A => IN0,
B => IN1,
C => IN2,
D => IN3,
S0 => SEL0,
S1 => SEL1,
Y => sig1);
comp2 : MUX4x1 port map
(A => IN4,
B => IN5,
C => IN6,
D => IN7,
S0 => SEL0,
S1 => SEL1,
Y => sig2);
comp3 : MUX2x1 port map
(A => sig1,
B => sig2,
S0 => SEL2,
Y => Y_OUT);

end BEHAVIORAL;
Pin Assignment for FPGA Implementation

Port
Reference
Name Port
Port of Pin
in Name
Type Component Number
VHDL on Kit
/ Pin
Code
SEL[2] SW1 P4
Control Slide
SEL[1] SW2 P9
Input Switches
SEL[0] SW3 P20
IN7 SW4 P46
IN6 SW5 P52
IN5 SW6 P39
Data Slide IN4 SW7 P79
Input Switches IN3 SW8 P64
IN2 SW9 P108
IN1 SW10 P113
IN0 SW11 P116
Data
LED Y LED1 P180
Output

Observations

8x1 Multiplexer
Input Output
S.N.
SEL2 SEL1 SEL0 Y_OUT
0
1 0 0
1
2 0 0

0
3 0 1
1
4 0 1

0
5 1 0
1
6 1 0

0
7 1 1
1
8 1 1
 EXPERIMENT – 7

VHDL Code of 3x8 Decoder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity decoder3x8 is
Port ( DIN : in STD_LOGIC_VECTOR(2 downto 0);
EN : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR(7 downto 0));
end decoder3x8;

architecture BEHAVIORAL of decoder3x8 is

begin
process (EN, DIN)
begin
if (EN = '0') then
Y <= "00000000";
else
if (DIN = "000") then
Y <= "00000001";
elsif (DIN = "001") then
Y <= "00000010";
elsif (DIN = "010") then
Y <= "00000100";
elsif (DIN = "011") then
Y <= "00001000";
elsif (DIN = "100") then
Y <= "00010000";
elsif (DIN = "101") then
Y <= "00100000";
elsif (DIN = "110") then
Y <= "01000000";
else
Y <= "10000000";
end if;
end if;
end process;
end BEHAVIORAL;

Pin Assignment for FPGA Implementation

Reference of Port Name in Port Name Pin

Port Type
Component / Pin VHDL Code on Kit Number
Data Input Slide Switches DIN(2) SW1 P4
 DIN(1) SW2 P9
DIN(0) SW3 P20
Enable Input Slide Switch EN SW4 P46
Y (7) LED1 P180
Y(6) LED2 P203
Y(5) LED3 P176
Y(4) LED4 P191
Output LED
Y(3) LED5 P175
Y(2) LED6 P196
Y(1) LED7 P182
Y(0) LED8 P172

Observations

Input Output
S.N.
EN DIN2 DIN2 DIN1 Y(7) Y(6) Y(5) Y(4) Y(3) Y(2) Y(1) Y(0)
X
1 0 X X
0
2 1 0 0
1
3 1 0 0
0
4 1 0 1
1
5 1 0 1
0
6 1 1 0
1
7 1 1 0
0
8 1 1 1
1
9 1 1 1
 EXPERIMENT – 8

VHDL Code of Frequency Divider

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity freq_div is
Port ( CLK_IN : in STD_LOGIC;
RESET : in STD_LOGIC;
CLK_div2 : out STD_LOGIC;
CLK_div4 : out STD_LOGIC;
CLK_1Hz : out STD_LOGIC;
CLK_2Hz : out STD_LOGIC;
CLK_4Hz : out STD_LOGIC);
end freq_div;
architecture BEHAVIORAL of freq_div is
signal clk_sig : std_logic_vector(26 downto 0);
begin
process (CLK_IN, RESET)
begin
if RESET = '0' then
if rising_edge(CLK_IN) then
clk_sig <= clk_sig + 1;
end if;
else
clk_sig <= (others=>'0');
end if;
end process;
CLK_div2 <= clk_sig(0);
CLK_div4 <= clk_sig(1);
CLK_1Hz <= clk_sig(24);
CLK_2Hz <= clk_sig(25);
CLK_4Hz <= clk_sig(26);
end BEHAVIORAL;
Pin Assignment for FPGA Implementation

Reference of Port Name in Port Name

Port Type Pin Number
Component / Pin VHDL Code on Kit

Slide Switches CLK_IN SW1 P87

Input
Slide Switch RESET SW4 P4
CLK_div2 LED1 P180
CLK_div4 LED2 P203
Output LED CLK_1Hz LED3 P176
CLK_2Hz LED4 P191
CLK_4Hz LED5 P175

Observations
Input Output
S.N.
RESET CLK_IN CLK_div2 CLK_div4 CLK_1Hz CLK_2Hz CLK_4Hz

1 1 X

2 0 80 MHz
 EXPERIMENT – 9

VHDL Code of 8-bit Even and Odd Parity Generator

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity parity_gen is
Port ( CLK, RESET : in STD_LOGIC;
B0, B1, B2, B3, B4, B5, B6, B7 : in STD_LOGIC;
even_parity, odd_parity : out STD_LOGIC);
end parity_gen;
architecture BEHAVIORAL of parity_gen is
begin
process (CLK, RESET, B0, B1, B2, B3, B4, B5, B6, B7)
begin
if RESET = '0' then
if rising_edge(CLK) then
even_parity <= B0 xor B1 xor B2 xor B3 xor B4 xor B5 xor B6 xor B7;
odd_parity <= NOT (B0 xor B1 xor B2 xor B3 xor B4 xor B5 xor B6 xor B7);
end if;
else
even_parity <= ‘0’;
odd_parity <= ‘0’;
end if;
end process;
end BEHAVIORAL;

Observations
Input Output
S.N.
B0 B1 B2 B3 B4 B5 B6 B7 Odd_parity Even_parity
1 0 1 0 1 1 1 0 0 1 0
2 1 1 0 1 0 1 0 1 0 1
3 1 0 0 1 0 0 1 0 0 1
4 0 1 1 0 1 0 1 1 0 1
5 1 1 1 0 0 1 1 0 0 1
6 0 0 0 0 1 1 1 1 1 0
7 1 1 1 0 0 0 0 0 0 1
8 0 1 0 1 1 1 1 1 1 0
 EXPERIMENT – 10

VHDL Code of 8-bit Even and Odd Parity Generator

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bcd_7seg is
Port ( CLK, RESET : in STD_LOGIC;
P, Q, R, S : in STD_LOGIC;
a, b, c, d, e, f, g : out STD_LOGIC;
disp1, disp2, disp3, disp4 : out STD_LOGIC);
end bcd_7seg;
architecture BEHAVIORAL of bcd_7seg is
begin
process (CLK, RESET, P, Q, R, S)
begin
if RESET = '0' then
if rising_edge(CLK) then
a <= (not Q and not S) or R or (Q and S) or P;
b <= (not Q) or (not Rand not S) or (R and S);
c <= (not R) or S or Q;
d <= (not Q and not S) or (not Q and R) or (not Q and R and S) or (R and not
S) or P;
e <= (not Q and not S) or (R and not S);
f <= (not Q and not S) or (Q and not R) or (Q and not S) or P;
g <= (not Q and R) or (Q and not R) or (Q and not S) or P;
end if;
else
a <= ‘0’;
b <= ‘0’;
c <= ‘0’;
d <= ‘0’;
e <= ‘0’;
f <= ‘0’;
g <= ‘0’;
end if;
end process;
disp1 <= ‘0’;
disp2 <= ‘1’;
disp3 <= ‘1’;
disp4 <= ‘1’;
end BEHAVIORAL;
Pin Assignment for FPGA Implementation
Reference of Port Name in Port Name Pin
Port Type
Component / Pin VHDL Code on Kit Number
CLK SW1 P6
RESET SW2 P14
P SW3 P32
Input Slide Switches
Q SW4 P43
R SW5 P51
S SW6 P54
a A P22
b B P23
c C P66
d D P25
e E P28
Output LED f F P29
g G P30
disp1 Disp1 P33
disp2 Disp2 P34
disp3 Disp3 P35
disp4 Disp4 P36

Observations
Input Output
S.
N. Reset P Q R S a b c d e f g
1 1 X X X X 0 0 0 0 0 0 0
2 0 0 0 0 1 1 1 1 1 1 0
3 0 0 0 1 0 1 1 0 0 0 0
4 0 0 1 0 1 1 0 1 1 0 1
5 0 0 1 1 1 1 1 1 0 0 1
6 0 1 0 0 0 1 1 0 0 1 1
0
7 0 1 0 1 1 0 1 1 0 1 1
8 0 1 1 0 1 0 1 1 1 1 1
9 0 1 1 1 1 1 1 0 0 0 0
10 1 0 0 0 1 1 1 1 1 1 1
11 1 0 0 1 1 1 1 1 0 1 1