01.

Microprocessor Vs Microcontroller:

02.Types of microcontroller?

On the basis of architecture the types of microcontroller are:

1. Havard Architecture
2. Von Neumann Architecture

On the basis of Service Provider or Vendor the types of microcontroller are:

1. AVR
2. PIC
3. Hitachi
4. Motorola
EEE3231(Section-B) Microcontrollers Session – 2018-19

❖ Harvard vs Princeton Architecture.

Answer:

❖ I2C Bus Protocol for IO Pins.

Answer: I2C(Inter-Integrated Circuit, eye-squared-C), alternatively known as I2C or IIC, is
a synchronous, multi-controller/multi-target (controller/target), packet switched, single-ended, serial
communication bus invented in 1982 by Philips Semiconductors. It is widely used for attaching lower-
speed peripheral ICs to processors and microcontrollers in short-distance, intra-board communication.
8-bit, serial communication bus protocol that uses just two bus wires; a serial data wire (SDA) and a
serial clock wire (SCL).
I2C operates on a master-slave basis.
Real time clocks, memory devices, and many others also use I2C to communicate information to other
chips, which is often a microcontroller or processor.

[Binay K. Paul] Page 1

Harvard Architecture
The Harvard architecture offers separate storage and signal buses for instructions and
data. This architecture has data storage entirely contained within the CPU, and there is
no access to the instruction storage as data. Computers have separate memory areas
for program instructions and data using internal data buses, allowing simultaneous
access to both instructions and data.
Programs needed to be loaded by an operator; the processor could not boot itself. In a
Harvard architecture, there is no need to make the two memories share properties.
Advantage of Harvard Architecture:
Harvard architecture has two separate buses for instruction and
data. Hence, the CPU can access instructions and read/write
data at the same time. This is the major advantage of Harvard
architecture.
In practice, Modified Harvard Architecture is used where we
have two separate caches (data and instruction). This is
common and used in X86 and ARM processors.
• Fast and efficient data access: Since Harvard architecture
has separate memory spaces for instructions and data, it
allows for parallel and simultaneous access to both memory
spaces, which leads to faster and more efficient data access.
• Better performance: The use of fixed instruction length,
parallel processing, and optimized memory usage in
Harvard architecture can lead to improved performance and
faster execution of instructions.
• Suitable for real-time applications: Harvard architecture
is commonly used in embedded systems and other real-
time applications where speed and efficiency are critical.
• Security: The separation of instruction and data memory
spaces can also provide a degree of security against
certain types of attacks, such as buffer overflow attacks.
Disadvantages of Harvard Architecture:
• Complexity: The use of separate memory spaces for instructions and
data in Harvard architecture adds to the complexity of the processor
design and can increase the cost of manufacturing.
• Limited flexibility: Harvard architecture has limited flexibility in
terms of modifying instructions at runtime because instructions and
data are stored in separate memory spaces. This can make certain
types of programming more difficult or impossible to implement.
• Higher memory requirements: Harvard architecture requires more
memory than Von Neumann architecture, which can lead to higher
costs and power consumption.
• Code size limitations: Fixed instruction length in Harvard
architecture can limit the size of code that can be executed, making it
unsuitable for some applications with larger code bases.

Princeton Architecture
Advantage of princeton Architecture

• Less physical space is required than Harvard

• Handling just one memory block is simpler and easier to achieve
• Cheaper to use than Harvard

Disadvantage
• Shared memory - a defective program can overwrite another in memory,
causing it to crash
• Memory leaks - some defective programs fail to release memory when
they are finished with it, which could cause the computer to crash due to
insufficient memory
• Data bus speed - the CPU is much faster than the data bus, meaning it
often sits idle (Von Neumann bottleneck)
• Fetch rate - data and instructions share the same data bus, even though
the rate at which each needs to be fetched is often very different
⁕⁕ CISC vs RISC Processor :
CISC Processor RISC Processor

1. Simple instructions taking one cycle. 1. Complex instructions taking multiple

cycle .
2. Very few instructions refer memory. 2. Most of instructions may refer memory.

3. Instruction are executed by hardware. 3. Instruction are executed by micro

program.
4. Fined formed instruction. 4. Variable formed instruction.

5. Few addressing mode and most instruction 5. Many addressing mode.

have register to register addressing mode.
6. Multiple register set, 6. Single register set,

7. Highly pipelined . 7. Non or use pipelined.

8. Low cycle per second with large code size. 8. High cycle per second with small code
size.

⁕⁕ Define: Clocking, instruction cycle, Clock cycle?

Clocking:
In the context of microcontrollers, "clocking" refers to the process of generating and
synchronizing the clock signals that regulate the timing and operation of the microcontroller's
internal components. Clocking is a crucial aspect of microcontroller design, as it determines how
the microcontroller processes instructions, performs calculations, and communicates with other
devices.

Instruction cycle:
The instruction cycle refers to the sequence of operations that the microcontroller performs
to fetch, decode, and execute a single instruction from memory. This process is fundamental to
the operation of any microcontroller or processor.

Clock cycle:
A clock cycle refers to the basic unit of time used to synchronize operations within the
microcontroller's central processing unit (CPU) and other components. It is also known as a
clock tick or clock pulse.
Q13. Basic feature of 8051 MP.

Sol: Basic feature of 8051 microprocessor are listed below.

1. 8-bit CPU

2. Harvard Architecture

3. 4KB ROM, 128 bytes RAM (typical)

4. 4 bidirectional I/O ports (P0, P1, P2, P3)

5. Timers/Counters

6. Serial Communication (UART)

7. Interrupts (Hardware and Software)

8. Simple Instruction Set

9. Power Modes

10. External Clock/Oscillator Circuit

Q14. Basic Architecture of 8051

Microprocessor.
 Q9. A diagram for 8051 parallel i/o pin?

Ans:

The 8051 microcontroller has four 8-bit ports named P0, P1, P2, and P3, which serve as parallel
input/output (I/O) ports. Each port has 8 pins that can be individually configured as input or
output. Here's the pin diagram for the 8051 microcontroller, specifically showing the parallel I/O
pins:

Vcc [ 1 ] [ 40 ] GND
P0.0/TXD [ 2 ] [ 39 ] P0.7/RXD
P0.1/RXD [ 3 ] [ 38 ] P1.0/T2
P0.2/TXD [ 4 ] [ 37 ] P1.1/T2EX
P0.3/INT0 [ 5 ] [ 36 ] P1.2
P0.4/INT1 [ 6 ] [ 35 ] P1.3
P0.5/T0 [ 7 ] [ 34 ] P1.4
P0.6/T1 [ 8 ] [ 33 ] P1.5
P0.7/WR [ 9 ] [ 32 ] P1.6/AIN0
EA [10 ] [ 31 ] P1.7/AIN1
ALE [11 ] [ 30 ] P2.0
PSEN [12 ] [ 29 ] P2.1
P2.7 [13 ] [ 28 ] P2.2
P2.6 [14 ] [ 27 ] P2.3
P2.5 [15 ] [ 26 ] P2.4
P2.6 [16 ] [ 25 ] RST
P2.7 [17 ] [ 24 ] XTAL2
P3.0 [18 ] [ 23 ] XTAL1
P3.1 [19 ] [ 22 ] RXD/T1
P3.2 [20 ] [ 21 ] TXD/T0

Explanation:

• The pins labeled P0.0 to P0.7 are the individual pins of Port 0.
• The pins labeled P1.0 to P1.7 are the individual pins of Port 1.
• The pins labeled P2.0 to P2.7 are the individual pins of Port 2.
• The pins labeled P3.0 to P3.2 are the individual pins of Port 3.

Each of these pins can be configured as either input or output, depending on the needs of the
application. The input/output configuration can be set using the appropriate control registers in
the 8051 microcontroller.

* Port-0 Pin Structure Port -0 has 8 pins (P0.0-P0.7).

• Port-1 Pin Structure Port-1 has 8 pins (P1.1-P1.7) .The structure of a port-1
pin is shown in fig below.

* PORT 2 Pin Structure Port-2 has 8-pins (P2.0-P2.7) . The structure of a port-2 pin
is shown in figure below:
• Port-3 has 8 pin (P3.0-P3.7). Port-3 pins have alternate functions. The
structure of a port-3 pin is shown in figure
Q 14. Basic Architecture of 8051 Microprocessor?
Ans:

Basic Architecture of 8051 Microprocessor Basic Architecture of 8051 Microprocessor

Microprocessor vs Microcontroller
Let us now take a look at the most notable differences between a microprocessor and
a microcontroller.
Microprocessor Microcontroller

Microprocessors are multitasking in Single task oriented. For example, a

nature. Can perform multiple tasks at washing machine is designed for
a time. For example, on computer we washing clothes only.
can play music while writing text in
text editor.

RAM, ROM, I/O Ports, and Timers can RAM, ROM, I/O Ports, and Timers
be added externally and can vary in cannot be added externally. These
numbers. components are to be embedded
together on a chip and are fixed in
numbers.

Designers can decide the number of Fixed number for memory or I/O
memory or I/O ports needed. makes a microcontroller ideal for a
limited but specific task.

External support of external memory Microcontrollers are lightweight and

and I/O ports makes a cheaper than a microprocessor.
microprocessor-based system heavier
and costlier.

External devices require more space A microcontroller-based system

and their power consumption is consumes less power and takes less
higher. space.

Instruction cycle consists of fetch, execute and interrupt stage show in below.

If any interrupt occurs, it is indicated by an interrupt flag. The CPU will go to interrupt handler routine.
Interrupt handler then checks the type of interrupt and executes the appropriate function. It involves
overhead but still better than the CPU waiting for I/O completion or other activities.
Interrupt handler activates most prior able activity first and later deferrable part will be handled.

Example
The of data arrives on the network line.

Kernel marks the presence of data (urgent part) and gives the CPU back to the process that was running
before.

Rest of processing can be done later (moving data to buffer where recipient will find it)

Interrupt vector
Table of pointers in memory contains the addresses of interrupt service routines at a fixed location for a
given CPU.

Interrupt processing
Step 1 − First device issues interrupt to CPU.

Step 2 − Then, the CPU finishes execution of current instruction.

Step 3 − CPU tests for pending interrupt request. If there is one, it sends an acknowledgment to the
device which removes its interrupt signal.

Step 4 − CPU saves program status word onto control stack.

Step 5 − CPU loads the location of the interrupt handler into the PC register.

Step 6 − Save the contents of all registers from the control stack into memory.

Step 7 − Find out the cause of interrupt, or interrupt type or invokes appropriate routine.

Step 8 − Restore saved registers from the stack.