Computer Laboratory Manual

DIGITAL LOGIC DESIGN

Name:______________________________
Student ID:_______________________________
Department:______________________________

NEWPORTS INSTITUTE OF COMMUNICATIONS

AND ECONOMICS
 STUDENT GUIDELINES
There is 1Hr 40 Minutes allocated to a laboratory session in Digital
Electronics. It is a necessary part of the course at which attendance is
compulsory.
Here are some guidelines to help you perform the experiments and to
submit the reports:
1 Read all instructions carefully and carry them all out.
2 Ask a demonstrator if you are unsure of anything.
3 Record actual results (comment on them if they are unexpected!)
4 Write up full and suitable conclusions for each experiment.
5 If you have any doubt about the safety of any procedure, contact the
demonstrator beforehand.
6 THINK about what you are doing!

2
LA INDEX PAGE
B NO
NO

1 Introduction to Digital Laboratory Equipments & IC‟s 4

2 To study basic gates and verify their truth tables 11

3 To design and construct basic flip-flops 13

4 To design and implement encoder and decoder 15

5 To design and implement multiplexer 18

6 To design and implement demultiplexer 21

7 To Design adder, subtractor circuit using a 4-bit adder 23

IC

8 To design and construct of Synchronous Counter 24

9 To design and construct Asynchronous counter 26

10 To realize Basic gates (AND,OR,NOT) From Universal 29

Gates( NAND & NOR

11 To study about full adder & verify its truth table 32

3
 Experiment No:1
AIM: Introduction to Digital Laboratory Equipments & IC‟s
The Breadboard
The breadboard consists of two terminal strips and two bus strips (often
broken in the centre). Each bus strip has two rows of contacts. Each of the two
rows of contacts are a node. That is, each contact along a row on a bus strip is
connected together (inside the breadboard). Bus strips are used primarily for
power supply connections, but are also used for any node requiring a large
number of connections. Each terminal strip has 60 rows and 5 columns of
contacts on each side of the centre gap. Each row of 5 contacts is a node.
You will build your circuits on the terminal strips by inserting the leads of
circuit components into the contact receptacles and making connections with
22-26 gauge wire. There are wire cutter/strippers and a spool of wire in the
lab. It is a good practice to wire +5V and 0V power supply connections to
separate bus strips.

Fig 1. The breadboard. The lines indicate connected holes.

The 5V supply MUST NOT BE EXCEEDED since this will damage the ICs
(Integrated circuits) used during the experiments. Incorrect connection of
power to the ICs could result in them exploding or becoming very hot - with
4
the possible

5
 serious injury occurring to the people working on the experiment! Ensure
that the power supply polarity and all components and connections are
correct before switching on power.
Building the Circuit:
Throughout these experiments we will use TTL chips to build circuits. The
steps for wiring a circuit should be completed in the order described below:
1 Turn the power (Trainer Kit) off before you build anything!
2 Make sure the power is off before you build anything!
3 Connect the +5V and ground (GND) leads of the power supply to the
power and ground bus strips on your breadboard.
4 Plug the chips you will be using into the breadboard. Point all the chips in the
same direction with pin 1 at the upper-left corner. (Pin 1 is often identified by
a dot or a notch next to it on the chip package)
5 Connect +5V and GND pins of each chip to the power and ground bus strips
on the breadboard.
6 Select a connection on your schematic and place a piece of hook-up wire
between corresponding pins of the chips on your breadboard. It is better to
make the short connections before the longer ones. Mark each connection on
your schematic as you go, so as not to try to make the same connection again
at a later stage.
7 Get one of your group members to check the connections, before you turn
the power on.
8 If an error is made and is not spotted before you turn the power on. Turn
the power off immediately before you begin to rewire the circuit.
9 At the end of the laboratory session, collect you hook-up wires, chips and
all equipment and return them to the demonstrator.
10.Tidy the area that you were working in and leave it in the same condition
as it was before you started.
Common Causes of Problems:
1 Not connecting the ground and/or power pins for all chips.
2 Not turning on the power supply before checking the operation of the circuit.
3 Leaving out wires.
4 Plugging wires into the wrong holes.
5 Driving a single gate input with the outputs of two or more gates
6 Modifying the circuit with the power on.
In all experiments, you will be expected to obtain all instruments, leads,
components at the start of the experiment and return them to their proper
place after you have finished the experiment. Please inform the demonstrator
or technician if you locate faulty equipment. If you damage a chip, inform a
demonstrator, don't put it back in the box of chips for somebody else to use.
Example Implementation of a Logic Circuit:
6
Build a circuit to implement the Boolean function F = /(/A./B), please note
that the notation /A refers to . You should use that notation during the
write-up of your laboratory experiments.

Quad 2 Input 7400 Hex 7404 Inverter

Fig 2. The complete designed and connected circuit

Sometimes the chip manufacturer may denote the first pin by a small indented
circle above the first pin of the chip. Place your chips in the same direction, to
save confusion at a later stage. Remember that you must connect power to the
chips to

7
get them to work.
Useful IC Pin details
IC Description of IC
NU
MBE
R
740 Quad2inputNANDGATE
0
740 Quad2inputNANDGate(openc
1 ollector)
740 Quad 2 input NOR Gate
2
740 Quad2inputNORGates(opencoll
3 ector)
740 Hex Inverts
4
7421 Dual 4 input AND Gates

7430 8 input NAND Gate

7432 Quad 2 input OR Gates

7486 Quad 2 input EX-OR Gate

7410 Dual j-k Flip Flop
7
7410 Dual j-k Flip Flop
9
7417 Hex D Flip Flop
4
7417 Quad D Flip Flop
3
7473 Dual j-k Flip Flop

7474 Dual D Flip Flop

7475 Quad Bi-stable latch

8
 7400(NAND)

7402(NOR)

9
 7404(NOT)

7408(AND)

7420(4‐i/pNAND)

10
7411(3‐i/p AND) 7432(OR)

7486(EX- R)

11
 Experiment No:2

AIM:- To study basic gates ( AND , OR , NOT ) and verify their truth tables.

APPARATUS:- LED, IC‟s , Wires , 5 volt DC supply, Bread Board etc.

THEORY:-

AND Gate

Input Input Output

A B Q
0 0 0
0 1 0
1 0 0
1 1 1
Traditional symbol Truth Table

In AND gate circuit it has n input and only one output. Digital signals are applied in input terminal. In the AND
gate operation is „t‟ if and only if all the input are „1‟ otherwise zero.
Mathematically :The output Q is true if input A AND input B are both true: Q = A AND B
An AND gate can have two or more inputs, its output is true if all inputs are true.
OR Gate

Input Input Output

A B Q
0 0 0
0 1 1
Traditional symbol Truth 1 0 1
Table 1 1 1
In OR-Gate operation it has also n input and only one output. In OR
operation output is one if and only if one or more input are ‘1’.
Mathematically
The output Q is true if input A OR input B is true (or both of them are true):
Q = A OR B

12
 An OR gate can have two or more inputs, its output is true if at least one
input is true.
NOT Gate (Inverter)

Input Output
A Q
0 1
1 0
Traditional symbol Truth Table

It is also known as inverter. It has only one input and one

output.Mathematically
The output Q is true when the input A is NOT true, the output is
the inverse of the input:Q = NOT A. A NOT gate can only have one
input. A NOT gate is also called an inverter.
RESULT:- Corresponding truth tables of logic gates are verified.

PRECAUTIONS:-
1. Supply should not exceed 5v.
2. Connections should be tight and easy to inspect.
3. Use L.E.D. with proper sign convention and check it before
conneting in circuit.

13
 Experiment No:3
Aim: ‐To design and construct basic flip-flops R-S ,J-K,J-K Master slave flip-flops using gates and verify their
truth tables
Apparatus: ‐
1 IC‟s - 7404, 7402, 7400
2 Electronic circuit designer
3 Connecting patch chords

Circuit Diagrams:-
Basic flipflop using NAND gates
Truth Table
S R Q
0 0 Forbi
dden
0 1 1
1 0 0
1 1 No
Chan
ge

Basic flipflop using NOR gates

S R Q
0 0 No
Change
0 1 0
S1 0 1
1 1 Forbidden

R-S flip-flop using NAND gates

R Q
0 0 No Change
0 1 0
1 0 1
1 1 Forbidden

14
 J-k flip-flop using NAND gates

J K Q
0 0 No Change
0 1 0
1 0 1
1 1 Race
around

J-K Master Slave using NAND gates

J K Q
0 0
0 1 0
1 0 1
1 1

Procedure:
1. Connect the Flip-flop circuits as shown above.
2. Apply different combinations of inputs and observe the outputs
.

Precautions: All the connections should be made properly.

Result: Different Flip-flops using gates are constructed and their truth tables are verified

15
Experiment No:4

AIM: To design and implement encoder and decoder using logic gates and study of IC 7445 and IC 74147.

APPARATUS REQUIRED:

S COMPONENT SPECIFICA Q
l. TION T
N Y
o .
.
1 3 I/P NAND IC 7410 2
. GATE
2 OR GATE IC 7432 3
.
3 NOT GATE IC 7404 1
.
2 IC TRAINER KIT - 1
.
3 PATCH CORDS - 2
. 7

THEO

RY:

ENCO

DER:
An encoder is a digital circuit that performs inverse operation of a decoder. An encoder has 2 n input lines and n
output lines. In encoder the output lines generates the binary code corresponding to the input value. In octal to
binary encoder it has eight inputs, one for each octal digit and three output that generate the corresponding binary
code. In encoder it is assumed that only one input has a value of one at any given time otherwise the circuit is
meaningless. It has an ambiguila that when all inputs are zero the outputs are zero. The zero outputs can also be
generated when D0 = 1.

DECODER:
A decoder is a multiple input multiple output logic circuit which converts coded input into coded output where
input and output codes are different. The input code generally has fewer bits than the output code. Each input code
word produces a different output code word i.e there is one to one mapping can be expressed in truth table. In the
block diagram of decoder circuit the encoded
n n output values are from 0
information is present as n input producing 2 through possible
output 2n-1 outputs. 2

16
17
LOGIC DIAGRAM FOR ENCODER

INPUT OUTPUT
Y Y Y Y Y Y Y A B C
1 2 3 4 5 6 7
1 0 0 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 1 1
0 0 0 1 0 0 0 1 0 0
0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 1 1 1

18
 TRUTH TABLE:

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:

Thus the design and implementation of encoder and decoder using logic gates and study of IC 7445 and IC
74147 were done

19
 Experiment No: 5 & 6

AIM: To design and implement Multiplexer and Demultiplexer using logic gates and study of IC 74150 and IC
74154.

APPARATUS REQUIRED:
Sl.No COMPONEN SPECIFICA Q
. T TION T
Y
.
1. 3 I/P AND I 2
GATE C
7
4
1
1
2. OR GATE I 1
C
7
4
3
2
3. NOT GATE I 1
C
7
4
0
4
4. IC TRAINER 1
KIT -
5. PATCH
CORDS -
THE
ORY
:

MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a smaller number of channels or lines. A
digital multiplexer is a combinational circuit that selects binary information from one of many input lines and
directs it to a single output line. The selection of a particular input line is controlled by a set of selection lines.
Normally there are 2n input line and n selection lines whose bit combination determine which input is selected.

DEMULTIPLEXER:
The function of Demultiplexer is in contrast to multiplexer function. It takes information from one line and
distributes it to a given number of output lines. For this reason, the demultiplexer is also known as a data
distributor. Decoder can also be used as demultiplexer. In the 1: 4 demultiplexer circuit, the data input line goes to
all of the AND gates. The data select lines enable only one gate at a time and the data on the data input line will
pass through the selected gate to the associated data output line.

BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

20
21
FUNCTION TABLE:

TRUTH TABLE:

22
S S INPUT
1 0
0 0 X → D0 = X S1’
S0’
0 1 X → D1 = X S1’
S0
1 0 X → D2 = X S1
S0’
1 1 X → D3 = X S1
S0

23
 TRUTH TABLE:
INPUT OUTPUT
S S I D D D D
1 0 / 0 1 2 3
P
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1

PIN DIAGRAM FOR IC 74154:

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.

24
(iii) Observe the output and verify the truth table.

RESULT:
Thus the design and implementation of Multiplexer and Demultiplexer using logic gates and study of IC 74150
and IC 74154 were done

25
 Experiment No:7

AIM: To verify the truth table of 4- bit adder and 2's compliment subtractor circuit using a 4-bit adder IC(7483)
are verified

Apparatus: Logic trainer kit, 4-bit adder (IC 7483), X-OR gates (IC 7486), wires

Theory: IC 7483 is a 4 bit adder. In binary, subtraction can be performed by using 2's
complement method. In this method negative number is converted into its 2's complement and it
is added to the other number. The result of this addition is the subtraction of origin numbers.
If we modify the adder circuit, such that 2's complement and simple representation are presented,
we can perform addition subtraction as required. X-OR gate is used as a controlled inverter/
buffer for this purpose. Use it as buffer for addition and inverter for subtraction.

Procedure:
1. Connect the IC 7483 and IC 7486 as per diagram.
2. Connect all A's and all B's to logic sources, S's to logic indicators.
3. Connect Cin to logic 0, this will set the circuit for addition.
4. Give various input combinations, verify adder operation. Here Cout is MSB of addition.
5. Connect Cin to logic 1, this will set the circuit for subtraction by 2's complement method.
6. Give various input combinations and observe outputs. Here Cout is neglected (2's
complement subtraction)
7. Switch off power supply

Precautions: All the connections should be made properly.

Result: The truth table of 4- bit adder, 2's compliment subtractor circuit using a 4-bit adder IC are verified.

26
 Experiment No:8
Aim:-To design and construct of 3-bit Synchronous up and down counters,2-bit up/down
counter.
Apparatus:
1 IC‟s - 7408,7476,7400,7432
2 Electronic circuit designer
3 Connecting patch chords

Circuit Diagram:
Truth Table

Two Bit up/Down Counter using negative edge-triggered flip-flops

27
 WHEN M=1 WHEN M=0

CLK Q2 Q1 CLK Q2 Q1
0 0 0 0 1 1
1 0 1 1 1 0
2 1 0 2 0 1
3 1 1 3 0 0

Procedure:
1 Connections are made as per the circuit diagram
2 Switch on the power supply.
3 Apply clock pulses and note the outputs after each clock pulse and note done
the out puts.

Result: 3-bit Synchronous up and down counters,2-bit up/down counter are designed and truth tables are
verified.

Precautions:
1 All the connections should be made properly.
2 IC should not be reversed.

28
 Lab Manual: Digital Electronics Lab
(EE-224-F)
Experiment No:9
AIM: To design and construct of Asynchronous up and down counters, 2-bit up/down counter.
Apparatus:
1 IC‟s - 7408,7476,7400,7432
2 Electronic circuit designer
3 Connecting patch chords

Circuit Diagram: 3-
bit Asynchronous up
counter:

3-bit Asynchronous down counter:

29
 Lab Manual: Digital Electronics Lab
(EE-224-F)

TRUTH TABLE

Two Bit up/Down Counter using negative edge-triggered flip-

30
 Lab Manual: Digital Electronics Lab
(EE-224-F)

WHEN M=1 WHEN M=0

CLK Q2 Q1 CLK Q2 Q1
0 0 0 0 1 1
1 0 1 1 1 0
2 1 0
3 1 1

Procedure:
1 Connections are made as per the circuit diagram
2 Switch on the power supply.
3 Apply clock pulses and note the outputs after each clock pulse and note done
the out puts.

Result: 3-bit Asynchronous up and down counters,2-bit up/down counter are designed and truth tables are
verified.

Precautions:
1 All the connections should be made properly.
2 IC should not be reversed.

31
 Experiment No:10

AIM:- Realize Basic gates (AND,OR,NOT) From Universal Gates( NAND & NOR).

APPARATUS:- L.E.D., Bread-Board, I.C.‟s, Wires, “5.0” V d.c. supply, etc.

THEORY:-
NAND Gates to AND, OR, NOT Gates:-
NAND gates is Universal gate. The Basic gates AND, OR, NOT can be realized from it. The Boolean equations
and logic diagrams are as follows :

NAND TO AND :

NAND TO NOT :

NAND TO OR :

NOR Gate to AND, OR, NOT Gates :

32
NOR gate is also an Universal gate. The Basic gates AND, OR, NOT can be realized from it. The Boolean
equations and logical diagrams are as follows :

NOR to OR Gate :

NOR to AND Gate

NOR to NOT Gate

Truth tables :
NAND to AND Gate
Inputs Output
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
NAND to OR Gate
Inputs Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 1

33
 NAND to NOT Gate
input output
A Y
0 1
1 0

NOR to AND Gate

Inputs Output
A B Y
0 0 0
0 1 0
1 0 0
1 1 1

NOR to OR Gate
Inputs Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 1

NOR to NOT Gate

input output
A Y
0 1
1 0

RESULT:
The realization of basic gates(AND ,OR ,NOT) from universal gates( NAND &NOR ) is successful.& The
corresponding truth-tables are also verified.

PRECAUTIONS:-

1) Supply should not exceed 5v.

2) Connections should be tight and easy to inspect.
3) Use L.E.D. with proper sign convention and check it before conneting in circuit.

34
Experiment No:11

AIM:-To study about full adder & verify its truth table.

APPARATUS:-IC-(7486,7408,7432),Connecting wires, LED, Bread board,Cutter,5v supply.

THEORY:-
An half adder has only two inputs and there is no provision to add a carry coming from the lower order bits when
multibit addition is performed. For this purpose, a third input terminal is added and this circuit is used to add An,
Bn and Cn-1 where An and Bn are the nth order bits of the numbers A and B respectively and Cn-1 is the carry
generated from the addition of (n-1)th order
bits. This circuit is referred to as FULL-ADDER.

An Bn Cn-1
1

1
U10A U9A U8A
74H04 74H04 74H04

U3A
2

1
12 2
13
74H1 5
U4A
1
12
32 1 U7A
1
U5A
74H1 5
5
2
4
6
Sn
1 74H20
2 12
13
74H1 5
74H15 U6A
1 12
2
13

An
Bn U 1
1
2 3
5
A
Bn
Cn-1
1
74H01

3
2
An
Cn-1 U
74H01
1
6 3
A
1 74H01

U
1
7
A
35
U14 2 12
A 13
1 74H15
Cn

36
 TRUTH TABLE:-

INPUTS OUTPUTS

An Bn Cn-1 S C
U A
M R
R
Y
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

PROCEDURE:-

1. Write the truth table for variables An, Bn and Cn-1.

2. Truth table was solved with the help of K-map.
3. Circuit was connected and the outputs of sum and carry was got separately.
4. Connect the pin no.14 to 5v supply of all IC‟s used in
circuit. 5.Pin no. 7 will be grounded of all IC‟s.
RESULT:- The truth table of full adder is verified.

PRECAUTIONS:-

1. Supply should not exceed 5v.

2. Connections should be tight and easy to inspect.
3. Use L.E.D. with proper sign convention and check it before conneting in circuit.

37