VLSI Design

Th- 3 hrs/week, Pr -2 hrs/week

 Introduction to VLSI

 1958, 1st flip flop IC developed with 2

transistors
 Earlier vacuum tubes, now MOSFETs : low
power consumption, low area, high speed
 1965, Gordon Moore: number of transistors on
IC doubles every 18 months.
 Corollary of Moore’s law: transistors become
cheaper, faster and consume less area and
power.
Moore’s Law
 Then and now

First IC Planar(1961) Intel Nehalem Quad

Processor Die
 AI, IOT fuel new chip designs, India
at the centre of it
 Google, Facebook, Amazon, Alibaba,
Apple, Samsung and Microsoft are all
accelerating efforts to design chips
 Google’s setting up a team in Bengaluru
for chip design and 66 of the job offerings
are for this function
 Qualcomm has 263 job openings in India
 Intel has 403 job openings in Bengaluru
 40,000 job openings in semiconductor
industry, which will double in next 5 years
Opportunities in VLSI earlier
Opportunities in VLSI now
Analog Domain
IC fabricated from SCL,
Chandigarh
 Various Design Styles

• Programmable Logic Devices

– Field Programmable Gate Array (FPGA)
– Complex Programmable Logic Devices (CPLD)
• Standard Cell (Semi-Custom Design) –
Digital ICs (ASIC)
• Full-Custom Design – Analog ICs (ASIC)
5
10
 Which Design Style toUse?

Basically a tradeoff among several design

parameters.
 Hardware cost
 Circuit delay

 Time required to design

Optimizing on these parameters is often conflicting.

6
11
 FPGA Design Flow

• Design Entry
– In schematic, VHDL or Verilog.
• Implementation
– Placement & Routing
– Bitstream generation
– Analyze timing, view layout, simulation, etc.
• Download
– Directly to Xilinx hardware devices with unlimited
reconfigurations.
12
 Students working in VLSI Domain
 Dikita Chauhan –San Jose State University, working at Intel
Corporation, California
 Rohan Jagtap – Portland State University, working at
Synopsys, Oregon
 Raviraj Kokil - Portland State University, working at Intel
Corporation, Oregon
 Sonia Patwardhan - San Jose State University, working at
Intel Corporation
 Aakash Thakare – Arizona State University, working at Intel
Corporation
 Chetan Udawant - San Jose State University, working at Intel
Corporation
 Aditya Kshirsagar - Penn State University, working at Intel
Corporation
 Sanmati Jain - Working at Intel Corporation, India
 IITs offering M. Tech in VLSI
 IIT, Madras – SHAKTI Processor - Open-source
Processor Development Ecosystem- developing
family of 6 processors of RISC architecture:
https://shakti.org.in/
 IIT, Bombay
 IIT, Delhi
 IIT, Kharagpur
 NITs
 Manipal University
 MIT-WPU
 Hardware Description Language -
Introduction

 HDL is a language that describes the hardware of digital

systems in a textual form.
 It resembles a programming language, but is specifically
oriented to describing hardware structures and behaviors.
 The main difference with the traditional programming
languages is HDL’s representation of extensive parallel
operations whereas traditional ones represents mostly serial
operations.
 The most common use of a HDL is to provide an alternative
to schematics.
 HDL – Introduction (2)

 HDL can be used to represent logic

diagrams, Boolean expressions, and other
more complex digital circuits.
 There are two applications of HDL
processing: Simulation and Synthesis
 Logic Simulation
 A simulator interprets the HDL description and produces a
readable output, such as a timing diagram, that predicts
how the hardware will behave before its is actually
fabricated.
 Simulation allows the detection of functional errors in a
design without having to physically create the circuit.
 The stimulus that tests the functionality of the design is
called a test bench.
 To simulate a digital system
◼ Design is first described in HDL
◼ Verified by simulating the design and checking it with a test bench
which is also written in HDL.
 Logic Simulation
 Logic simulation is a fast,
accurate method of
analyzing a circuit to see its
waveforms
 Types of HDL

 There are two standard HDL’s that are supported by IEEE.

◼ VHDL (Very-High-Speed Integrated Circuits Hardware

Description Language) - Sometimes referred to as

VHSIC HDL, this was developed from an initiative by
US. Dept. of Defense.
◼ Verilog HDL – developed by Cadence Data systems and

later transferred to a consortium called Open Verilog

International (OVI).
 Verilog

 Verilog HDL has a syntax that describes precisely

the legal constructs that can be used in the
language.
 It uses about 100 keywords pre-defined, lowercase,
identifiers that define the language constructs.
 Example of keywords: module, endmodule, input,
output wire, and, or, not , etc.,
 Any text between two slashes (//) and the end of
line is interpreted as a comment.
 Blank spaces are ignored and names are case
sensitive.
 Verilog - Module
 A module is the building block in Verilog.
 It is declared by the keyword module and is always
terminated by the keyword endmodule.
 Each statement is terminated with a semicolon, but there is
no semi-colon after endmodule.
 Verilog – Module (2)
HDL Example
module smpl_circuit(A,B,C,x,y);
input A,B,C;
output x,y;
wire e;
and g1(e,A,B);
not g2(y,C);
or g3(x,e,y);
endmodule
 Verilog – Gate Delays
 Sometimes it is necessary to specify the amount of delay
from the input to the output of gates.
 In Verilog, the delay is specified in terms of time units and
the symbol #.
 The association of a time unit with physical time is made
using timescale compiler directive.
 Compiler directive starts with the “backquote (`)” symbol.
`timescale 1ns/100ps
 The first number specifies the unit of measurement for time
delays.
 The second number specifies the precision for which the
delays are rounded off, in this case to 0.1ns.
 Verilog – Module (4)
//Description of circuit with delay
`timescale 1ns/100ps
module circuit_with_delay
(A,B,C,x,y);
input A,B,C;
output x,y;
wire e;
and #(30) g1(e,A,B);
or #(20) g3(x,e,y);
not #(10) g2(y,C);
endmodule
 Verilog – Module (7)
Bitwise operators (performs bitwise operation
on two operands)
◼ Bitwise NOT : ~
◼ Bitwise AND: &
◼ Bitwise OR: |
◼ Bitwise XOR: ^
◼ Bitwise XNOR: ~^ or ^~
 Verilog - Module
 A module is the building block in Verilog.
 It is declared by the keyword module and is always
terminated by the keyword endmodule.
 Each statement is terminated with a semicolon, but there is
no semi-colon after endmodule.
 Verilog – Module (8)

Boolean Expressions:
 These are specified in Verilog HDL with a
continuous assignment statement consisting of the
keyword assign followed by a Boolean Expression.
 The earlier circuit can be specified using the
statement:

assign x = (A&B)|~C)
 Verilog – Module (9)

//Circuit specified with Boolean equations

module circuit_bln (x,y,A,B,C);
input A,B,C;
output x,y;
assign x = (A&B)|~C)
assign y = ~C;
endmodule
 Verilog – Module (10)

User Defined Primitives (UDP):

 The logic gates used in HDL descriptions
with keywords and, or, etc., are defined by
the system and are referred to as system
primitives.
 The user can create additional primitives by
defining them in tabular form.
 These type of circuits are referred to as
user-defined primitives.
 Verilog – Module (12)
UDP features ….
 UDP’s do not use the keyword module. Instead they are
declared with the keyword primitive.
 There can be only one output and it must be listed first in
the port list and declared with an output keyword.
 There can be any number of inputs. The order in which they
are listed in the input declaration must conform to the order
in which they are given values in the table that follows.
 The truth table is enclosed within the keywords table and
endtable.
 The values of the inputs are listed with a colon (:). The
output is always the last entry in a row followed by a
semicolon (;).
 It ends with the keyword endprimitive.
 Can be used for truth tables and also state tables for
sequential circuits.
 Verilog – Module (13)
//User defined primitive(UDP)
primitive crctp (x,A,B,C);
output x;
input A,B,C;
//Truth table for x(A,B,C) = Minterms (0,2,4,6,7)
table
// A B C : x (Note that this is only a
comment)
0 0 0 : 1;
0 0 1 : 0;
0 1 0 : 1; // Instantiate primitive
0 1 1 : 0;
1 0 0 : 1; module declare_crctp;
1 0 1 : 0;
1 1 0 : 1; reg x,y,z;
1 1 1 : 1; wire w;
endtable
endprimitive crctp c11(w,x,y,z);
endmodule
 Verilog – Module (14)
 A module can be described in any one (or a
combination) of the following modeling techniques.
◼ Switch-level modeling using switches and
interconnections between them. This is the lowest level
of abstraction.
◼ Gate-level modeling using instantiation of primitive
gates and user defined modules.
⚫ This describes the circuit by specifying the gates and how they
are connected with each other.
◼ Dataflow modeling using continuous assignment
statements with the keyword assign.
⚫ This is mostly used for describing combinational circuits.
◼ Behavioral modeling using procedural assignment
statements with keywords 1. always, 2. initial
⚫ This is used to describe digital systems at a higher level of
abstraction.
 Gate-Level Modeling
 Here a circuit is specified by its logic gates and
their interconnections.
 It provides a textual description of a schematic
diagram.
 Verilog recognizes basic gates as predefined
primitives.
◼ and, nand, or, nor, xor, xnor, not, buf
 When the gates are simulated, the system assigns a
four-valued logic set to each gate – 0,1,unknown (x)
and high impedance (z)
 Gate-level modeling (2)
 When a primitive gate is incorporated into a
module, we say it is instantiated in the module.
 In general, component instantiations are
statements that reference lower-level components
in the design, essentially creating unique copies
(or instances) of those components in the higher-
level module.
 Thus, a module that uses a gate in its description is
said to instantiate the gate.
 Gate-level Modeling (3)
 Modeling with vector data (multiple bit widths):
◼ A vector is specified within square brackets and two
numbers separated with a colon.
e.g. output[0:3] D; - This declares an output vector
D with 4 bits, 0 through 3.
wire[7:0] SUM; – This declares a wire vector
SUM with 8 bits numbered 7 through 0.
The first number listed is the most significant bit of the
vector.
 Gate-level Modeling

 Two or more modules can be combined to build a

hierarchical description of a design.
 There are two basic types of design methodologies.
◼ Top down: In top-down design, the top level block is defined and
then sub-blocks necessary to build the top level block are
identified.
◼ Bottom up: Here the building blocks are first identified and then
combine to build the top level block.
 In a top-down design, a 4-bit binary adder is defined as
top-level block with 4 full adder blocks. Then we describe
two half-adders that are required to create the full adder.
 In a bottom-up design, the half-adder is defined, then the
full adder is constructed and the 4-bit adder is built from
the full adders.
 Gate-level Modeling

 A bottom-up hierarchical description of a 4-bit

adder is described in Verilog as
◼ Half adder: defined by instantiating primitive gates.
◼ Then define the full adder by instantiating two half-
adders.
◼ Finally the third module describes 4-bit adder by
instantiating 4 full adders.
 Note: In Verilog, one module definition cannot be
placed within another module description.
4-bit Half Adder
4-bit Full Adder
 4-bit Full Adder
//Gate-level hierarchical description of 4-bit adder
module halfadder (S,C,x,y);
input x,y;
output S,C;
//Instantiate primitive gates
xor x1(S,x,y);
and x2(C,x,y);
endmodule

module fulladder (S,C,x,y,z);

input x,y,z;
output S,C;
wire S1,D1,D2; //Outputs of first XOR and two AND
gates
//Instantiate the half adders
halfadder HA1(S1,D1,x,y);
halfadder HA2(S,D2,S1,z);
or g1(C,D2,D1);
endmodule
 4-bit Full Adder
module _4bit_adder (S,C4,A,B,C0);
input [3:0] A,B;
input C0;
output [3:0] S;
output C4;
wire C1,C2,C3; //Intermediate carries

//Instantiate the full adder

fulladder FA0 (S[0],C1,A[0],B[0],C0);
fulladder FA1 (S[1],C2,A[1],B[1],C1);
fulladder FA2 (S[2],C3,A[2],B[2],C2);
fulladder FA3 (S[3],C4,A[3],B[3],C3);
endmodule
2 to 4 Decoder
 2 to 4 Decoder
//Gate-level description of a 2-to-4-line
decoder
module decoder_gl (A,B,E,D);
input A,B,E;
output[0:3]D;
wire Anot,Bnot,Enot;

not n1 (Anot,A),
not n2 (Bnot,B),
not n3 (Enot,E);

nand n4 (D[0],Anot,Bnot,Enot),
nand n5 (D[1],Anot,B,Enot),
nand n6 (D[2],A,Bnot,Enot),
nand n7 (D[3],A,B,Enot);
endmodule
Three-State Gates
 Three-State Gates
 Three-state gates have a control input that can place the
gate into a high-impedance state. (symbolized by z in
HDL).
 The bufif1 gate behaves like a normal buffer if
control=1. The output goes to a high-impedance state z
when control=0.
 bufif0 gate behaves in a similar way except that the
high-impedance state occurs when control=1
 Two not gates operate in a similar manner except that the
o/p is the complement of the input when the gate is not in a
high impedance state.
 The gates are instantiated with the statement
◼ gate name (output, input, control);
 Three-State Gates

The output of 3-state gates

can be connected together to
form a common output line.
To identify such connections, module muxtri(A,B,sel,out);
HDL uses the keyword tri (for
input A,B,sel;
tri-state) to indicate that the
output OUT;
output has multiple drivers.
tri OUT;
bufif1 (OUT,A,sel);
bufif0 (OUT,B,sel);
endmodule
 Three-State Gates
• Keywords wire and tri are examples of net data type.
• Nets represent connections between hardware elements. Their value
is continuously driven by the output of the device that they represent.
• The word net is not a keyword, but represents a class of data types
such as wire, wor, wand, tri, supply1 and supply0.
• The wire declaration is used most frequently.
• The net wor models the hardware implementation of the wired-OR
configuration.
• The wand models the wired-AND configuration.
• The nets supply1 and supply0 represent power supply and
ground.
 Dataflow Modeling

 Dataflow modeling uses a number of operators that act on

operands to produce desired results.
 Verilog HDL provides about 30 operator types.
 Dataflow modeling uses continuous assignments and the
keyword assign.
 A continuous assignment is a statement that assigns a value
to a net.
 The value assigned to the net is specified by an expression
that uses operands and operators.
2 to 4 Decoder
 Verilog – Module (7)

Bitwise operators (performs bitwise operation

on two operands)
◼ Bitwise NOT : ~
◼ Bitwise AND: &
◼ Bitwise OR: |
◼ Bitwise XOR: ^
◼ Bitwise XNOR: ~^ or ^~
2 to 4 Decoder
 Dataflow Modeling (2)
//Dataflow description of a 2-to-
4-line decoder
module decoder_df (A,B,E,D);
input A,B,E;
output [0:3] D;
assign D[0] = ~(~A & ~B & ~E),
D[1] = ~(~A & B & ~E),
D[2] = ~(A & ~B & ~E),
D[3] = ~(A & B & ~E);
endmodule
 Dataflow Modeling (5)
 Dataflow Modeling provides the means of describing combinational
circuits by their function rather than by their gate structure.
 Conditional operator (?:)
condition ? true-expression : false-expression;
 A 2-to-1 line multiplexer
assign OUT = select ? A : B;

//Dataflow description of 2-to-1-line mux

module mux2x1_df (A,B,select,OUT);
input A,B,select;
output OUT;
assign OUT = select ? A : B;
endmodule
 Behavioral Modeling

 Behavioral modeling represents digital circuits at a

functional and algorithmic level.
 It is used mostly to describe sequential circuits, but
can also be used to describe combinational circuits.
 Behavioral descriptions use the keyword always
followed by a list of procedural assignment
statements.
 The target output of procedural assignment
statements must be of the reg data type.
 A reg data type retains its value until a new value
is assigned.
 Behavioral Modeling (2)

 The procedural assignment statements inside the always block are executed
every time there is a change in any of the variable listed after the @ symbol.
(Note that there is no “;” at the end of always statement)
//Behavioral description of 2-to-1-line
multiplexer
module mux2x1_bh(A,B,select,OUT);
input A,B,select;
output OUT;
reg OUT;
always @(select or A or B)
if (select == 1) OUT = A;
else OUT = B;
endmodule
 Writing a Test Bench

 A test bench is an HDL program used for applying stimulus

to an HDL design in order to test it and observe its response
during simulation.
 In addition to the always statement, test benches use the
initial statement to provide a stimulus to the circuit
under test.
 The always statement executes repeatedly in a loop. The
initial statement executes only once starting from simulation
time=0 and may continue with any operations that are
delayed by a given number of units as specified by the
symbol #.
 Writing a Test Bench (2)
initial begin
A=0; B=0; #10 A=1; #20 A=0; B=1;
end
 The block is enclosed between begin and end.
At time=0, A and B are set to 0. 10 time units
later, A is changed to 1. 20 time units later (at
t=30) a is changed to 0 and B to 1.
 Multiple initial blocks are allowed and they
are executed parallel
 If only one statement after initial then begin
and end are not required.
 Writing a Test Bench (2)

 Inputs to a 3-bit truth table can be generated with

the initial block
initial begin
D = 3’b000; repeat (7); #10 D = D +
3’b001;
end
 The 3-bit vector D is initialized to 000 at time=0.
The keyword repeat specifies looping
statement: one is added to D seven times, once
every 10 time units.
 Writing a Test-Bench (3)
 A stimulus module is an HDL program that has the following
form.
module testname
Declare local reg and wire identifiers
Instantiate the design module under test.
Generate stimulus using initial and always statements
Display the output response.
endmodule
 A test module typically has no inputs or outputs.
 The signals that are applied as inputs to the design module for
simulation are declared in the stimulus module as local reg data
type.
 The outputs of the design module that are displayed for testing
are declared in the stimulus model as local wire data type.
 The module under test is then instantiated using the local
identifiers.
 Writing a Test-Bench (4)

The stimulus model generates inputs for the design module by declaring
identifiers TA and TB as reg data type, and checks the output of the
design unit with the wire identifier TC. The local identifiers are then used
to instantiate the design module under test.
 Writing a Test-Bench (5)
 The response to the stimulus generated by the initial and
always blocks will appear at the output of the simulator as
timing diagrams.
 It is also possible to display numerical outputs using
Verilog system tasks.
◼ $display – display one-time value of variables or
strings with end-of-line return,
◼ $write – same $display but without going to next line.

◼ $monitor – display variables whenever a value

changes during simulation run.
◼ $time – displays simulation time

◼ $finish – terminates the simulation

$monitor – System task that displays variables on the

monitor
%b – used to display binary values.
 Writing a Test-Bench (7)

//Dataflow description of 2-to-1-line

multiplexer
module mux2x1_df (A,B,select,OUT);
input A,B,select;
output OUT;
assign OUT = select ? A : B;
endmodule
 Writing a Test-Bench (6)
`timescale 1ns / 1ps
module testmux;
reg TA,TB,TS; //inputs for mux – local identifiers
wire Y; //output from mux – local identifiers
mux2x1_df instantiation(.A(TA),.B(TB),.select(TS),.OUT(Y));
initial
begin
TS = 0;
TA = 0;
TB = 0;
end
always #40 TS=~TS;
always #30 TA=~TA;
always #20 TB=~TB;
always @(TS or TA or TB)
$monitor(”select=%b A=%b B=%b OUT=%b",TS,TA,TB,Y);
endmodule
 Half Adder

module halfadder (S,C,x,y);

input x,y;
output S,C;
//Instantiate primitive gates
xor x1(S,x,y);
and x2(C,x,y);
endmodule
 posedge, negedge

posedge – triggers the circuit

on the positive edge of signal
(clk)
negedge - triggers the circuit
on the positive edge of signal
(clk)
 D Flip-Flop

//D flip-flop
module D_FF (Q,D,CLK);
output Q;
input D,CLK;
reg Q;
always @(posedge CLK)
Q <= D;
endmodule
 D Flip Flop
//D flip-flop with set and reset
module D_FF1 (Q,D,CLK, set, reset);
output Q;
input D,CLK,set,reset;
reg Q;
always @(posedge CLK)
begin
if (set ==1) Q <=1;
else if (reset ==1) Q<=0;
else Q <= D;
end
endmodule
 Relational Operators-
Returns true or false ( 1 or 0)
Operator Description

a<b a less than b

a>b a greater than b

a <= b a less than or equal to b

a >= b a greater than or equal to b

a == b a equal to b

a !=b a not equal to b

 Dataflow Modeling (3)

//Dataflow description of a
4-bit comparator.
module magcomp
(A,B,ALTB,AGTB,AEQB);
input [3:0] A,B;
output ALTB,AGTB,AEQB;
assign ALTB = (A < B);
assign AGTB = (A > B);
assign AEQB = (A == B);
endmodule
 Arithmetic Operators

+ (addition) : A + B
- (subtraction) : A-B
* (multiplication) : A*B
/ (division) : A/B
% (modulo) : A % B
4-bit Full Adder
 Dataflow Modeling (4)

//Dataflow description of 4-bit

adder
module binary_adder
(A,B,Cin,SUM,Cout);
input [3:0] A,B;
input Cin;
output [3:0] SUM;
output Cout;
assign {Cout,SUM} = A + B + Cin;
endmodule
 Dataflow Modeling (4)
 The addition logic of 4 bit adder is described by a
single statement using the operators of addition and
concatenation.
 The plus symbol (+) specifies the binary addition of
the 4 bits of A with the 4 bits of B and the one bit of
Cin.
 The target output is the concatenation of the output
carry Cout and the four bits of SUM.
 Concatenation of operands is expressed within
braces and a comma separating the operands. Thus,
{Cout,SUM} represents the 5-bit result of the
addition operation.
 Behavioral Modeling

 Behavioral modeling represents digital circuits at a

functional and algorithmic level.
 It is used mostly to describe sequential circuits, but
can also be used to describe combinational circuits.
 Behavioral descriptions use the keyword always
followed by a list of procedural assignment
statements.
 The target output of procedural assignment
statements must be of the reg data type.
 A reg data type retains its value until a new value
is assigned.
 Behavioral Modeling (2)
 The procedural assignment statements inside the always block are executed
every time there is a change in any of the variable listed after the @ symbol.
(Note that there is no “;” at the end of always statement)

//Behavioral description of 2-to-1-line

multiplexer
module mux2x1_bh(A,B,select,OUT);
input A,B,select;
output OUT;
reg OUT;
always @(select or A or B)
if (select == 1) OUT = A;
else OUT = B;
endmodule
Behavioral Modeling (3)

4-to-1 line
multiplexer
 Behavioral Modeling (4)

//Behavioral description of 4-to-1 line mux

module mux4x1_bh (i0,i1,i2,i3,select,y);

input i0,i1,i2,i3;
input [1:0] select;
output y;
reg y;
always @(i0 or i1 or i2 or i3 or select)
begin
if (select==00)y = i0;
else if (select ==01) y = i1;
else if (select == 10)y=i2;
else y=i3;
end
endmodule
 Behavioral Modeling (4)

//Behavioral description of 4-to-1 line mux

module mux4x1_bh (i0,i1,i2,i3,select,y);

input i0,i1,i2,i3;
input [1:0] select;
output y;
reg y;
always @(i0 or i1 or i2 or i3 or select)
case (select)
00: y = i0;
01: y = i1;
10: y = i2;
11: y = i3;
endcase
endmodule
 Behavioral Modeling (5)

 In 4-to-1 line multiplexer, the select input is defined

as a 2-bit vector and output y is declared as a reg
data.
 The always block has a sequential block enclosed
between the keywords case and endcase.
 The block is executed whenever any of the inputs
listed after the @ symbol changes in value.
 T Flip Flop
//T flip-flop
module T_FF (Q,T,CLK);
output Q;
input T,CLK;
reg Q;
always @(posedge CLK)
begin
if (T==1)
Q <= ~Q;
else
Q <= Q;
end
endmodule
 T Flip Flop
//T flip-flop
module T_FF (Q,T,CLK,s,r);
output Q;
input T,CLK,s,r;
reg Q;
always @(posedge CLK)
begin
if (s==1)
Q <= 1;
else if (r==1)
Q <= 0;
else if (T==1)
Q <= ~Q;
else
Q <= Q;
end
 Data Types in Verilog

 1. Net
 Continuously driven
 Cannot be used to store a value
 2. Register
 Retains the last value assigned
 Often used to represent storage elements but
sometimes can refer to combinational cct
 1. Net data type

 Represents connection between hardware

elements.
 Nets are continuously driven by the hardware
they are connected to
 E.g : AND gate
 Nets are 1-bit values (unless specified as
vectors) and default value is “z”
 Various net data types are : wire, tri, wand,
wor, supply0, supply1
Example on wor, wand,
supply0, supply1
 2. Register data type
 A register is a variable that can hold value and it is not continuously
driven
 A register data type does not mean a register will be generated in
hardware, it can refer to combinational cct also
 Register data types supported by Verilog are:
 1. reg – mostly used (sequential ccts)
 2. integer - for loops
 3. real – for storing real data
 4. time – for simulation
e.g: reg X;
X = A+B; (assignment happens without “assign” statement)
X – will hold the value until a new value is assigned to it
 Data Values
• Verilog supports this 4 logic values 0, 1, x and z.
– 0 is logic 0, 1 is logic 1, x is unknown which is not
initialized it can be 0, it can be 1, but z is high
impedance state.
• When initialized, all unconnected nets, the wires
they are initialized to z.
• If variables are declared of type register,
registers are initialized to x.
 Behavioral Modeling

 The statements within the always block, after the event

control expression, execute sequentially and the execution
suspends after the last statement has executed.
 Then the always statement waits again for an event to
occur.
 Two kind of events:
◼ Level sensitive (E.g. in combinational circuits and in latches)
always @(A or B or Reset) will cause the execution of the
procedural statements in the always block if changes occur in A or B
or Reset.
◼ Edge-triggered (In synchronous sequential circuits, changes in
flip-flops must occur only in response to a transition of a clock
pulse.
always @(posedge clock or negedge reset)will cause the
execution of the procedural statements only if the clock goes
through a positive transition or if the reset goes through a negative
transition.
 Behavioral Modeling

 A procedural assignment is an assignment within an initial or

always statement.
 There are two kinds of procedural assignments: blocking and
non-blocking
◼ Blocking assignments (executed sequentially in the order they are
listed in a sequential block, blocks the execution of the next
statement). Most suitable for combinational circuits.
⚫ B=A
⚫ C=B+1
◼ Non-blocking assignments (evaluate the expressions on the right
hand side, but do not make the assignment to the left hand side until all
expressions are evaluated.) Most suitable for sequential circuits
⚫ B <= A
⚫ C <= B + 1
 Example

 Blocking assignment:
integer a,b,c;
Initial
begin
a=10; b=20; c=15;
a=b+c; a = 35
b=a+5; b = 40
c= a-b; c= -5
end
 Example

 Non-Blocking assignment:
integer a,b,c;
Initial
begin
a=10; b=20; c=15;
a<=b+c; a = 35
b<=a+5; b = 15
c<= a-b; c = -10
end
 Blocking assignment
module blocking (clk,a,c);
input clk, a;
output c;
reg c,b;
always @ (posedge clk )
begin
b = a;
c = b;
end
endmodule
 Non-Blocking assignment
module blocking (clk,a,c);
input clk, a;
output c;
reg c,b;
always @ (posedge clk )
begin
b< = a;
c< = b;
end
endmodule
Sequential System Design - Finite State Machine
– (Any sequential circuit that passes through finite number of states is a
FSM.)
 Types of FSM
 1. Mealy machine – Output depends on present state as well
as primary inputs

 2. Moore machine – Output depends on only the present

state
FSM

Mealy Machine
 Sequential System Design (2)
1. Obtain the state diagram from the statement of the
problem.
2. From step 1, obtain state table.
3. Assign binary codes to the states.
4. Derive the flip-flop input equations from the next-state
entries in the encoded state table.
5. Derive output equations from the output entries in the
state table.
6. Simplify the flip-flop input and output equations.
7. Draw the logic diagram with D flip-flops and
combinational gates, as specified by the flip-flop I/O
equations.
FSM
 Parameters

 Are like constants in Verilog

 E.g: In counter, parameter can be used
parameter N=3;
output [N:0] count;
reg [N:0] count;
.
.
 FSM

Mealy Machine
 Sequential Circuit (2)

//Mealy state diagram for the circuit

module Mealy_mdl (x,y,CLK,RST);
input x,CLK,RST;
output y;
reg y;
reg [1:0] Prstate,Nxtstate;
parameter S0=2'b00,S1=2'b01,S2=2'b10,S3=2'b11;
always@(posedge CLK or posedge RST)
if (RST==1) Prstate <= S0; //Initialize to
state S0
else Prstate <= Nxtstate; //Clock operations
 always @(Prstate or x) //Determine next state
case (Prstate)
S0: if (x) begin Nxtstate = S1; y = 1'b0;
end
else begin Nxtstate = S0; y = 1’b0;
end
S1: if (x) begin Nxtstate = S3; y = 1’b0;
end
else begin Nxtstate = S0; y = 1’b1;
end
S2: if (x) begin Nxtstate = S2; y = 1’b0;
end
else begin Nxtstate = S0; y = 1’b1;
end
S3: if (x) begin Nxtstate = S2; y = 1’b0;
end
else begin Nxtstate = S0; y = 1’b1;
end
endcase
endmodule
 FSM

Moore Machine
 FSM

BCD Counter
 Flip-Flops and Latches
 The D-latch is transparent and responds to a change in data
input with a change in output as long as control input is
enabled.
 It has two inputs, D and control, and one output Q. Since Q
is evaluated in a procedural statement it must be declared
as reg type.
 Latches respond to input signals so the two inputs are
listed without edge qualifiers in the event control
expression following the @ symbol in the always
statement.
 There is one blocking procedural assignment statement and
it specifies the transfer of input D to output Q if control is
true.
 Flip-Flops and Latches

module D_latch(Q,D,control);
output Q;
input D,control;
reg Q;
always @(control or D)
if(control) Q = D; //Same as: if(control=1)
endmodule
 Flip-Flops and Latches
//D flip-flop //D flip-flop with asynchronous reset.
module D_FF (Q,D,CLK); module DFF (Q,D,CLK,RST);
output Q; output Q;
input D,CLK,RST;
input D,CLK;
reg Q;
reg Q;
always @(posedge CLK or negedge RST)
always @(posedge CLK)
if (~RST) Q = 1'b0; // Same as: if (RST = 0)
Q = D; else Q = D;
endmodule endmodule
 Course : VLSI Design
TY BTech ECE

Manisha Ingle

Courtesy
Hardware modeling using verilog, IIT Kharagpur
Prof. Indranil Sengupta
 Course Title : VLSI Design
Course Code : ECE3008B
Course Category : Professional Core
Course Contents:
• Verilog HDL Design: Study of Verilog HDL, Design using Verilog basic gates,
arithmetic circuits, basic combination circuits, sequential circuit, flip flops,
memories, shift registers, FSMs using Verilog HDL.

• PLD Architectures and applications: Design Flow, CPLD Architecture,

Features, Specifications, Applications. FPGA Architecture, Features,
Specifications, Applications.

• Digital CMOS circuits: N-MOS, P-MOS and CMOS, MOSFET parasitic,

Technology scaling, CMOS Inverter, Device sizing, CMOS combinational
logic design.

• VLSI Testing and Analysis: Types of fault, Need of Design for Testability
(DFT), Testability, Fault models, Path sensitizing, Test pattern generation,
Built-in Self-Test, JTAG & Boundary scan.
Laboratory Exercises / Practicals:
PART: A
• To write Verilog HDL code, simulate with test bench, synthesize,
implement on PLD
• 4:1 Mux,
• D/T-Flip-flop
• Half adder and Full Adder
• 2-bit comparator

PART: B
• To prepare and simulate CMOS layout and schematic in selected
technology Inverter,
• NAND, NOR gates
• Half Adder
• 2:1 multiplexer using logic gates and transmission gates.

Project Base Learning (PBL) based on Part A/Part B

• Discussion and finalization of the topic for PBL
• Implementation of the project and report writing of PBL.
Learning Resources:
Text Books:
• 1. John F. Wakerly. Digital Design. Principles and Practices. Fourth
Edition, Pearson Publication, 2008.
• 2. Neil H. E. Weste, David Money Harris, “CMOS VLSI Design: A Circuit &
System Perspective”, Third Edition, Pearson Publication ,2005.
Reference Books:
• 1. S. Palnitkar, "Verilog HDL: A Guide to Digital Design and Synthesis",
Second Edition, Prentice Hall PTR Publications, 2003.
• 2.Steve Kilts,” Advanced FPGA Design Architecture, Implementation and
Optimization” Wiley publications, 2007.
Supplementary Reading:
Weblinks:
https://nptel.ac.in
Web Resources:
• https://www.tutorialspoint.com/vlsi_design/vlsi_design_digital_system.htm
https://www.javatpoint.com/vhdl
• MOOCs:
• VLSI Circuits, https://nptel.ac.in/courses/117/106/117106092/
 Introduction
Module 1
Objectives
• Learn about the Verilog hardware description language.
• Understand the difference between behavioural and
structural design styles.
• Learn to write test benches and analyse simulation
results.
• Learn to model combinational and sequential circuits.
• Distinguish between good and bad coding practices.
 VLSI Design Process
• Design complexity increasing rapidly
– Increased size and complexity
– Fabrication technology improving
– CAD tools are essential
– Conflicting requirements like area,speed, and energy
consumption
• The Present trend
– Standardize the design flow
– Emphasis on low power design , and increased
performance.
Intgrated Circuit(Then and Now)
 Moore’s Law
Every 18 months the number of transistors in a single chip will get doubled.

• Exponential growth , Design complexity increases rapidly

• Automated tools are essential , Must follow well defined design flow
• Because of semiconductor fabrication advances we are able to fabricate
bigger chips,
• We have been able to put more circuits in the chip
• Technologies that have made this possible are CMOS.
• CMOS is the most dominant technology today, CMOS transistors are
becoming smaller and smaller over the years.
 Moore’s Law will cease to exist….
• State of the art CMOS technology today can go down up to 22 nanometer, this is traditional
CMOS fabrication.
• Very innovative kind of CMOS designs also, called FinFET, where the gate drain and the
source they are staked vertically instead of horizontally as in the traditional case.
• This way you can pack transistors in a smaller area.
• FinFET state of the technology can go down to 14 nanometer.
• Modern chips that are coming in the market, they are actually manufactured using this
FinFET technology .
• Futuristic, this we do not have today, tomorrow quantum computer may come so we may
be having a new technology called quantum technology
 VLSI Design flow
• Standardized design procedure
• Starting from the design idea downto the actual
implementation
Encompasses many steps:
• Specification
• Synthesis
• Simulation
• Layout
• Testability analysis
• And many more…
 These steps have to be followed before we can actually get
a design fabricated, or manufactured.
 Without CAD tools, it is just beyond the capability of human
being to carry out the design in a manual way .
• Need to use CAD tools
• CAD tools are based on Hardware
Description Language(HDL).
• HDLs provide formats for representing
the outputs of various design steps.
• A CAD tool transforms its HDL inputs into
a HDL output that contains more
detailed information about the
hardware.
• Behavioural level to register transfer
level
• Register transfer level to gate level
• Gate level to transistor level
• Transistor level to the layout level

Once you have carried out sufficient analysis and simulation to find
out, that your design is meeting your requirements in terms of power
consumption and delay, you can send it for fabrication.
 HDLs
1. Verilog
2. VHDL
3. Some of the popular languages are like SystemC,
SystemVerilog and so on,

Designs are created typically using HDLs, which get

transformed from one level of abstraction to the next
as the design progresses.
 Design Flow

• Behavioural design- form of a

pseudo code in a HDL or some
kind of a flow graph notation.
• Data path design- register
transfer level design, where
the basic building blocks are
buses, registers, multiplexers,
adders, and so on.
• Logic design - gates and flip
flops
• Physical design – transistors ,
where the transistors are
finally laid out and they are
ready to be fabricated on
silicon.
 Steps in the Design Flow
• Behavioural design
– Specify the functionality of the design in terms of its
behaviour.
– Various ways of specifying:
• Boolean expression or truth table
• FSM
• In the form of a high-level algorithm.
– Needs to be synthesized (transformed) into more
detailed specifications for hardware realization.

Functionality of the design in terms of the behaviour is

specified . We do not say, how it is doing it, we just say
what we want.
 Steps in the Design Flow
• Data path Design
• Generate a netlist of register transfer level components,
like registers, adders, multipliers, multiplexers, decoders,
etc.
• A netlist is a directed graph, where the vertices indicate
components and edges indicate interconnections.
• A netlist specification is also referred to as structural
design.
• Netlist may be specified at various levels, where the
components may be functional modules, gates or
transistors.
• Systematically transformed from one level to the next.
 Steps in the Design Flow
• Logic Design
• Generate a netlist of gates/flip-flops or standard cells.
• A standard cell is a predesigned circuit module (gates, FFs,
Mux etc.) at the layout level.
• Various logic optimization techniques are used to obtain a
cost effective design.
• There may be conflicting requirements during optimization:
• Minimize no of gates
• Minimize no of gate levels (i.e. delay)
• Minimize signal transition activities (i.e. dynamic power)
 Steps in the Design Flow
• Physical Design and Manufacturing
• Generate the final layout that can be sent for fabrication.
• The layout contains a large number of regular geometric
shapes corresponding to the different fabrication layers
• Alternatively, the final target may be FPGA, where technology
mapping from the get level netlist is used.
• Can be programmed in field.
• Much greater flexibility but less speed.
• Simulation for verification
• At various levels: logic level, switch level, circuit level
• Formal verification
• Used to verify the designs through formal techniques
• Testability analysis and test pattern generation
• Required for testing the manufactured devices.
 Verilog Modules
• Several modules
• Each of this modules will be starting with the module
keyword and it will end with the endmodule.
• All the modules taken together will define complete
specification of the hardware;
• To create a full adder module add, multiple modules are
used a carry module and sum module
• Four copies of the add modules are used to create a ripple
carry adder module using instantiation.
• Invoking one module means invoking another module
(called instantiation) .
• It means create a copy.
 Verilog Modules
• A design description in a Verilog will be look
like as shown.
• There are some restrictions like a module cannot contain
definitions of other module.
• A module can be instantiated within another module.
 Verilog Module

• 2 copies of M2 will get embedded

• M3 will also be embedded
• This module M1 can contain other statements also.
 Verilog Module

t1 and t2 signals are continuously driven

 Behavioural Representation

• This is one way of expressing the behaviour of a full adder.

• It is not specified , what kind of gates to be used, how many gates to be used
and so on.
 Behavioural Representation

• This is one way of expressing the behaviour of a full adder.

• It is not specified , what kind of gates to be used, how many gates to be used
and so on.
• The syntax is similar to the language C, every statement ends with a
semicolon.
• Verilog program consist of one or more modulus.
• It starts with this keyword module, it ends with endmodule.
• Module is followed by the name of the module and the parameters.
• The parameters are the input and the output ports of that block.
• Input signals (A, B,C), Output signals (S, Cy).
• assign statement available in Verilog.
• Using assign, you can directly write down the Boolean expression.
• This hat (⋀) is the expression for Exclusive OR this indicates XOR.
• Ampersand (&) is AND, bar (|) is OR.
Structural Representation
Structural Representation
Structural Representation
Structural Representation
 FA structural

• Sum and carry can be described as above in a structural way.

Test Bench
 (Net- o/p of a gate or functional block)

It is Not hardware register (f/f)

Example of net sbar. Sbar changes as s changes

Declared a net but not initialized then it is z (high impedance or tristate)
 In these situations if you want to tie the outputs
together wor and wand are used implied AND gate
Output is well defined.

Prohibited , wrong design

 Simulation only

• reg X
• X= A + B will get assigned to X.
• This assignment will not be done using an assign statement; not continuous
assignment because, in an assign statement the left hand side must be a net
type variable, it cannot be a register type variable.
• A register type variable - actually storing a value, it is supposed to hold the value
till you use it again.
• Register is different from a net which is continuously driven and cannot hold any
value
• The net variable immediately changes, it cannot hold it, but this does not mean
that a register variable will always map to a hardware register.
 Register data type - reg
• Variable x and y : by default 1-bit
• reg [15:0] bus - a variable bus, 16 bits, 0 is the least significant bit, 15
is the most significant bit.
• A reg type variable , when used in an arithmetic expression, it is
treated as an unsigned number without any sign.
• When hardware required is register based design like counter, shift
register, etc. then, use reg always.
• Two kinds of assignments: ( = , <= )
- A reg type variable A
- for these kind of assignments the left hand side must be a reg type
variable
Main body of the counter description:
• a statement called always : always at positive edge of the clock
(@posedge clk).
• Whenever there is a positive edge of the clock coming, check , if the
reset signal is one , i.e high or not, if it is high, initialize count value 32’b0
• Count is initialized to 0.
• If reset =1, count is 0, else count = count + 1;
• Expression with equal to (=) sign : - Only a reg type value in the left hand
side .
• Hence output is defined as count and reg also as count.
Example with register
Integer data type:
• More general purpose type,
• Can be used to store any arbitrarily integer values mainly for counting some
situations like loop counting.
• reg may not be very convenient , because the count value may sometimes
become negative, in reg, a variable declared of type reg is always considered to
be an unsigned quantity, it cannot have a negative value,
• Integer data type another feature is that it cannot have a size defined to it
(default size is 32-bits)
• Synthesis tool try to determine the size by carrying out some data flow analysis
wherever possible
 (10-2 )

Real data types :

• Used to store floating point numbers; i.e numbers with fractional
parts.
• Just like in a high level language, Whenever a real value is assigned
to an integer, there is little difference.
• Normally in a high level language like C the number is truncated and
the integer part is stored, but here it is rounded off.
Individual access
 Integer-32 bit by
default matrix is
2D with 8 rows
and 16 columns

Content of register
No. 5
Similar to #define in C
Code becomes more readable
If inputs arbitrary coming on
t1 and t2 , what should be
the out of f ?
AND gate Flexibility on no of inputs
 Primitive gates
• Buf (buffer) – to isolate signals, the logic value does not change, but
the signal values are restored,
• tri-state version of buffers :
• Bufif1: a buffer selected by a control signal ctrl.
– Control is one then out will be equal to in, if control is 0 then
output will be tri-state, it will be in the high impedance state
• bufif0: Polarity of the control is negative.
• notif1 and notif0: Output will be in bar and there will be a control,
this is notif1 and notif0. These tristate control gates are also
available.
time scale directive: `timescale 10ns/1ns
10ns : Basic unit of time.
#5 (5 units of gate delay) : 5*10ns= 50ns
1ns: precision of simulation. it specifies the precision with which we
round off the delays during simulation;
This simulation will be accurate up to 1 nanosecond
Valid values are 1,10,100 only not 1,2,3 etc.
Examples showing reg declaration generates wire and latch in two
level circuits

• f1,f2 at LHS so reg

• f1 output of NAND
• f2 output of XOR
• No need of storage cell
F2 is at LHS and RHS hence Latch is
generated.
Latch will be enabled at any change
in A,B,C
Not recommended
Unary
Binary
• Arithmetic Operators : Operates on some numbers ( add, subtract, multiply,
divide) Logical Operators: Operates on Logic values (true or false) generated
result is again a logic value (true or false)
• Logical operators are used in conditional statements or control constructs
like if then else statement.
Relational operators : inputs are numbers, return a boolean value (true or false) are
used in if then else , while or for loop.
Bitwise Operators (operates on single bit inputs and result is single
bit).
• Bitwise Operators in Verilog are supposed to model a hardware.
• To model logic expressions at the bit level, we use bit level
operators.

Tilda symbol
Reduction operator
{cout,sum} is concatenation: 2, 8-bit nos. are added and result is 9-bit
MSB in cout and 8-bit in sum
Verilog Modeling
 MUX16_1
`timescale 1ns / 1ps
module testmux16();
reg[15:0] in;
0 in=xxxx, sel=x, out=x
reg[3:0] sel; 5 in=3f0a, sel=0, out=0
wire out; 10 in=3f0a, sel=1, out=1
Mux_161 M0(.in(in),.sel(sel),.out(out)); 15 in=3f0a, sel=6, out=0
initial 20 in=3f0a, sel=c, out=1
begin

$monitor($time,"in=%h,sel=%h,out=%b
", in,sel,out);
#5 in=16'h3f0a; sel=4'h0;
#5 sel=4'h1;
#5 sel=4'h6;
#5 sel=4'hc;
#5
$finish;
end
endmodule
16:1 Mux structural Modeling
reg

net
Vector with non constant index , synthesizer tool generates a mux
No mux is generated
Decoder or DMUX
En=0, Q=Q remembering the previous
state synthesizer generates
latch
 Always- insied TB or in ckt descreption

• Always block: a continuous loop, which never terminates.

• Models a hardware circuit in a more natural way, Designed hardware is
supposed to work as long as power is switched on.
• We cannot say that this circuit hardware circuit will be working for 10
seconds and then it will automatically stop.
• It will not stop unless you expressly send a single to stop it.
• always block is like a piece of hardware which is taking some input,
generating some output and continuously it is doing it in a repetitive
fashion.
Multiple statements inside begin end
is required
inside the initial or always block, only
reg type variables can appear on LHS.

When sensitivity list conditions are

not true a, d need to remember the
values hence reg
posedge, negedge concept
Procedural Assignment (Examples)
Procedural Assignment (Examples)
Procedural Assignment (Examples)
Procedural Assignment (Examples
Blocking assignment (=) Curr_state =2 , flag doesn’t change,
it memories the previous value , hence latch is generated
 PROCEDURAL ASSIGNMENT (EXAMPLES)

Conditional statement: a==0 is not specified, synthesis tool generates and gate
and latch.
 PROCEDURAL ASSIGNMENT (EXAMPLES)

Combinational circuit w/o latch

ALU (Behavioral)
Priority Encoder
PROCEDURAL ASSIGNMENT (EXAMPLES)
• Whenever there is a positive edge of a clock, computations happen as per
the expressions (RHS) and assign them to these variables (LHS)
concurrently.
• All assignments take place synchronously at the rising edge of a clock.
if a = 10 , d
b = 20.
Result
a=20
b=10,
• Variable (sel) can assume a value not only 0 and 1, but also x and z.
• The select line can have value x (1,0,x,z four logic levels)
• It won’t match with any one of 000 to 111.
• For those cases it will go to the default option.
• Output = undefined x.
• Blocking assignments are happening sequentially.
• Non-blocking, both of the statements are waiting for time 5 and RHS
expression are executed concurrently.
• b will be assigned after time 5 to a; a will be also assigned after time 5 to c.
At positive edge of the clock, assign a to q1, then assign q1 to q2.
 Verilog always block
• always block: procedural block in verilog.
• Statements inside an always block are executed sequentially
• It is executed at some particular event
• Event is defined by a sensitivity list.
• Sensitivity list : contain either one or a group of signals whose value change will
execute the always block.
• always block : used to realize combinational or sequential elements.
– Sequential element becomes active when it is provided with a clk, rst.
– Combinational block becomes active when one of its input value change.
• These hardware blocks work concurrently independent of each other.
• If the sensitivity list is absent, then
 Value Holders for Hardware Modelling
Basic value holders in h/w are:

• Wire
• Flip-flop (an edge-triggered storage element)
• Latch (a level-sensitive storage element)
• A variable in verilog can either be of net data type or register datatype
• Variable of net datatype generates H/W as wire.
• Variable of register datatype maps either to a wire or a storage element(FF or a
latch) depending on the context under which the variable is assigned a value.
• A register variable retains its value through the entire simulation run, thus inferring
memory
 Data Values and Signal Strengths
• Verilog supports this 4 logic values 0, 1, x and z.
– 0 is logic 0, 1 is logic 1, x is unknown which is not initialized it
can be 0, it can be 1, but z is high impedance state.
• When initialized, all unconnected nets, the wires they are
initialized to z.
• If variables are declared of type register, registers are
initialized to x.
• If 2 signals are connected together, and if first signal is
stronger, then the final output will be dominated by the
stronger signal that is the concept of signal strength.
• In Verilog, there are 8 signal strengths as shown in table.
 Simulation Features
• Simulation only features: make sense only during
simulation.
• During synthesis, those features does not mean
anything and the synthesis tool will be simply ignoring
them.
• Whenever we instantiate a gate, we specify some
delays of these gates, the synthesis tool ignore that.
• It is only for simulation purposes.
• Time is something that relates to the time of
simulation, it is never used during synthesis, such
variables will be ignored during synthesis.
 Verilog always block
• always block ( for behavior level )
• assign ( for RT level )
• Thumb Rule for always block in combinatorial block In order to create
Verilog code that can generate synthesizable circuit, all inputs to the
hardware must appear in the sensitivity list. If it does not, then a latch
will result in place of a combinatorial logic.
• Combinational logic with always block:
• Output signal called z of type reg gets updated whenever one of the
signals in the sensitivity list changes its value.
 Combinational ckt.

A ternary operator used to decide which input should be assigned to the output
 Sequential logic with always
• Always block is mainly used to implement sequential logic
which uses memory elements like flipflops that can hold the
values.
• DFF: with asynchronous active-low reset
DFF: with synchronous active-low reset
 initial Block
• A set of verilog statements are usually executed sequentially in a
simulation
• Statements are placed inside procedural block
• Procedural blocks in Verilog- initial and always

• An initial block is not synthesizable-No hardware schematic and

digital elements.
• It is used in simulations only.
• Primarily used to initialize variables and drive design ports with
specific values.
 Start and End of initial Block
• Initial block is started at the beginning of a simulation at time 0 unit.
• This block will be executed only once during the entire simulation.
• Execution of an initial block finishes once all the statements within the block are
executed.
• Only one statement inside initial block hence not necessary to place the
statement within begin and end
 Delay element in initial statement
• Additional statement that assigns some value
to the signal b.
• This happens only after 10 time units from
execution of previous statement
More Than one initial Blocks

• First block delay of 20 units, second block delay of 50 units total, last
block delay is 60 units.
• Total simulation time 60 units.
• $finish- tells the simulator to terminate the current simulation
 Case Statement
• Case statement checks if the given expression matches one of the other
expressions in the list and branches accordingly
• Typically used to implement a Mux.
• If-else construct may not be suitable if there are may conditions to be
checked and would synthesize into a priority encoder instead of mux.
• Verilog case statement starts with case keyword and ends with the
endcase keyword.
• A block of multiple statements must be grouped and be within begin and
end.
Mux using case
 Task
• Tasks used in all programming languages, generally known as
procedures or subroutines.
• The lines of code are enclosed in task....end task brackets.
• Data is passed to the task, the processing done, and the result
returned.
• They have to be specifically called, with data ins and outs.
• Included in the main body of code, they can be called many
times, reducing code repetition.
• Tasks are defined in the module in which they are used.
• It is possible to define a task in a separate file and use the
compile directive 'include to include the task in the file which
instantiates the task.
 Task
• tasks can include timing delays, like posedge, negedge, # delay
and wait.
• tasks can have any number of inputs and outputs.
• The variables declared within the task are local to that task.
• The order of declaration within the task defines how the
variables passed to the task by the caller are used.
• Tasks can take, drive and source global variables, when no local
variables are used.
• When local variables are used, basically output is assigned only
at the end of task execution.
• Tasks can call another task or function.
• Tasks can be used for modeling both combinational and
sequential logic.
• A task must be specifically called with a statement, it cannot be
used within an expression as a function can.
 Syntax
• A task begins with keyword task and ends with keyword endtask
• Inputs and outputs are declared after the keyword task.
• Local variables are declared after input and output declaration.

module simple_task();
task convert;
input [7:0] temp_in;
output [7:0] temp_out;
begin
temp_out = (9/5) *( temp_in + 32)
end
endtask
endmodule
 Task using Global Variables
module task_global();
reg [7:0] temp_out;
reg [7:0] temp_in;
task convert;
begin
temp_out = (9/5) *( temp_in + 32);
end
endtask
endmodule
 Calling a Task
Task stored in a separate file.
Advantage of coding a task in a separate file, is that it can be used in multiple
modules.

module task_calling (temp_a, temp_b, temp_c, temp_d);

input [7:0] temp_a, temp_c;
output [7:0] temp_b, temp_d;
reg [7:0] temp_b, temp_d;
`include "mytask.v"
always @ (temp_a)
begin
convert (temp_a, temp_b);
end
always @ (temp_c)
begin
convert (temp_c, temp_d);
end endmodule
 Function
• A Verilog HDL function is the same as a task, with very little differences,
like function cannot drive more than one output, can not contain delays.

• Functions are defined in the module in which they are used.

• It is possible to define functions in separate files and use compile directive
'include to include the function in the file which instantiates the task.
• functions can not include timing delays, like posedge, negedge, # delay,
which means that functions should be executed in "zero" time delay.
• Functions can have any number of inputs but only one output.
• The variables declared within the function are local to that function. The
order of declaration within the function defines how the variables passed
to the function by the caller are used.
• functions can take, drive, and source global variables, when no local
variables are used. When local variables are used, basically output is
assigned only at the end of function execution.
• Functions can be used for modeling combinational logic.
• Functions can call other functions, but can not call tasks.
 Syntax of Function and Example
• A function begins with keyword function and ends with keyword
endfunction
• inputs are declared after the keyword function.

Example - Simple Function

module simple_function();
function myfunction;
input a, b, c, d;
begin
myfunction = ((a+b) + (c-d));
end
endfunction
endmodule
 Calling a Function
module function_calling(a, b, c, d, e, f);
input a, b, c, d, e ;
output f;
wire f;
`include "myfunction.v"
assign f = (myfunction (a,b,c,d)) ? e :0;
endmodule
 FSM and Types of FSM
FSM
• FSM are the heart of any digital design;
• A counter is a simple form of FSM.
• State machine Types
• Moore State Machine: outputs are only a function of the present state,

• Mealy State Machine: one or more of the outputs are a function of the
present state and one or more of the inputs.
 Modeling State machines
• One thing that need to be kept in mind when coding
FSM is that combinational logic and sequence logic
should be in two different always blocks.
• In the above two figures, next state logic is always the
combinational logic.
• State Registers and Output logic are sequential logic.
• It is very important that any asynchronous signal to the
next state logic be synchronized before being fed to the
FSM.
• Always try to keep FSM in a separate Verilog file.
• Using constants declaration like parameter or `define
to define states of the FSM makes code more readable
and easy to manage.
Combinational design in synchronous circuit
• The output of these combinational designs can depend on
states only, or on the states along with external inputs.
• The former is known as Moore design and latter is known
as Mealy design
• Since, the sequential designs are sensitive to edge of the
clock, therefore the glitches can occur only at the edge of
the clock.
• Hence, the glitches at the edge can be removed by sending
the output signal through the D flip flop, as shown in Fig.
moore_regular_template2.v
next state logic : state_next
module moore_regular_template2 // This is combinational of the sequential design,
#( parameter // which contains the logic for next-state
param1 : <value>, // include all signals and input in sensitive-list except
param2 : <value> state_next
) // next state logic : state_next
( // This is combinational of the sequential design,
input wire clk, reset, // which contains the logic for next-state
input wire [<size>] input1, input2, ..., // include all signals and input in sensitive-list except
output reg [<size>] output1, output2 state_next
); always @(input1, input2, state_reg) begin
state_next = state_reg; // default state_next
localparam [<size_state>] // for 4 states : size_state = 1:0 case (state_reg)
s0 = 0, s0 : begin
s1 = 1, output1 = <value>;
s2 = 2, output2 = <value>;
... ; ...
reg[<size_state>] state_reg, state_next; if (<condition>) begin // if (input1 = 2'b01) then
// state register : state_reg state_next = s1;
// This process contains sequential part and all the D-FF are end
// included in this process. Hence, only 'clk' and 'reset' are else if (<condition>) begin // add all the required
// required for this process. conditionstion
always @(posedge clk, posedge reset) begin state_next = ...;
if (reset) begin end
state_reg <= s1; else begin // remain in current state
end state_next = s0;
else begin end
state_reg <= state_next; end
end s1 : begin
end output1 = <value>;
output2 = <value>;
• / optional D-FF to remove glitches
• always @(posedge clk, posedge reset)
• begin
• if (reset) begin
• new_output1 <= ... ;
• new_output2 <= ... ;
• end
• else begin
• new_output1 <= output1;
• new_output2 <= output2;
• end
• end

• endmodule
 Lexical Conventions
• The basic lexical conventions used by Verilog HDL are similar to those in the C
programming language.
• Verilog contains a stream of tokens.
• Tokens can be comments, delimiters, numbers, strings, identifiers, and keywords.
• Verilog HDL is a case-sensitive language.
• All keywords are in lowercase.
1. Whitespace
• Blank spaces (\b) , tabs (\t) and newlines (\n) comprise the whitespace.
• Whitespace is ignored by Verilog except when it separates tokens.
• Whitespace is not ignored in strings.
2. Comments
• Comments can be inserted in the code for readability and
documentation.
• Two ways to write comments.
• A one-line comment starts with "//". Verilog skips from that point
to the end of line.
• A multiple-line comment starts with "/*" and ends with "*/".
• Multiple-line comments cannot be nested.
• However, one-line comments can be embedded in multiple-line
comments.
• a = b && c; // This is a one-line comment
• /* This is a multiple line
comment */
• /* This is /* an illegal */ comment */
• /* This is //a legal comment */
3 Operators
• Operators are of three types: unary, binary, and
ternary.
• Unary operators precede the operand.
• Binary operators appear between two operands.
• Ternary operators have two separate operators
that separate three operands.
• a = ~ b; // ~ is a unary operator. b is the operand
• a = b && c; // && is a binary operator. b and c are
operands
• a = b ? c : d; // ?: is a ternary operator. b, c and d
are operands
4 Number Specification
• There are two types of number specification in Verilog: sized and
unsized.
• Sized numbers are represented as <size> '<base format> <number>.
• <size> is written only in decimal and specifies the number of bits in
the number.
• Legal base formats are decimal ('d or 'D), hexadecimal ('h or 'H),
binary ('b or 'B) and octal ('o or 'O). The number is specified as
consecutive digits from 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b,c, d, e, f.
• Only a subset of these digits is legal for a particular base.
• Uppercase letters are legal for number specification.
• 4'b1111 // This is a 4-bit binary number
• 12'habc // This is a 12-bit hexadecimal number
• 16'd255 // This is a 16-bit decimal number.
Unsized numbers
• Numbers that are specified without a <base format> specification are decimal
numbers by default.
• Numbers that are written without a <size> specification have a default
number of bits that is simulator- and machine-specific (must be at least 32).
• 23456 // This is a 32-bit decimal number by default
• 'hc3 // This is a 32-bit hexadecimal number
• 'o21 // This is a 32-bit octal number
X or Z values
• Verilog has two symbols for unknown and high impedance values.
• These values are very important for modeling real circuits. An unknown value
is denoted by an x.
• A high impedance value is denoted by z.
• 12'h13x // This is a 12-bit hex number; 4 least significant bits unknown
• 6'hx // This is a 6-bit hex number
• 32'bz // This is a 32-bit high impedance number
Negative numbers
• Negative numbers can be specified by putting a minus sign before the size for
a constant number.
• Size constants are always positive. It is illegal to have a minus sign between
<base format> and <number>.
• An optional signed specifier can be added for signed arithmetic.
• -6'd3 // 8-bit negative number stored as 2's complement of 3
• -6'sd3 // Used for performing signed integer math
• 4'd-2 // Illegal specification
• Underscore characters and question marks
• An underscore character "_" is allowed anywhere in a number except the first
character.
• Underscore characters are allowed only to improve readability of numbers and
are ignored by Verilog.
• A question mark "?" is the Verilog HDL alternative for z in the context of
numbers. The ?
• 12'b1111_0000_1010 // Use of underline characters for readability
• 4'b10?? // Equivalent of a 4'b10zz
5 Strings
• A string is a sequence of characters that are enclosed by double quotes.
• The restriction on a string is that it must be contained on a single line, that is,
without a carriage return.
• It cannot be on multiple lines. Strings are treated as a sequence of one-byte
ASCII values.
• "Hello Verilog World" // is a string
• "a / b" // is a string
6 Identifiers and Keywords
• Keywords are special identifiers reserved to define the language constructs.
• Keywords are in lowercase.
• Keywords, System Tasks, and Compiler Directives.
• Identifiers are names given to objects so that they can be referenced in the
design.
• Identifiers are made up of alphanumeric characters, the underscore ( _ ), or
the dollar sign ( $ ).
• They cannot start with a digit or a $ sign (The $ sign as the first character is
reserved for system tasks).
• reg value; // reg is a keyword; value is an identifier
• input clk; // input is a keyword, clk is an identifier
 System Tasks and Compiler Directives
• Two special concepts used in Verilog: system tasks and compiler directives.
1. System Tasks
• Verilog provides standard system tasks for certain routine operations.
• All system tasks appear in the form $<keyword>.
• Operations such as displaying on the screen, monitoring , values of nets,
stopping, and finishing are done by system tasks.
Most useful system tasks:
1. Displaying information
• $display is the main system task for displaying values of variables or strings or
expressions.
Usage: $display(p1, p2, p3,....., pn);
• p1, p2, p3,..., pn can be quoted strings or variables or expressions.
• The format of $display is very similar to printf in C.
• A $display inserts a newline at the end of the string by default.
• A $display without any arguments produces a newline.
Example 3-3 $display Task
• //Display the string in quotes
$display("Hello Verilog World");
-- Hello Verilog World
• //Display value of current simulation time 230
$display($time);
-- 230
• //Display value of 41-bit virtual address 1fe0000001c at time 200
reg [0:40] virtual_addr;
$display("At time %d virtual address is %h", $time, virtual_addr);
-- At time 200 virtual address is 1fe0000001c
• //Display value of port_id 5 in binary
reg [4:0] port_id;
$display("ID of the port is %b", port_id);
-- ID of the port is 00101
Monitoring information
• Verilog provides a mechanism to monitor a signal when its
value changes.
• This facility is provided by the $monitor task.
Usage: $monitor(p1,p2,p3,....,pn);
• The parameters p1, p2, ... , pn can be variables, signal names,
or quoted strings.
• A format similar to the $display task is used in the $monitor
task.
• $monitor continuously monitors the values of the variables or
signals specified in the parameter list and displays all
parameters in the list whenever the value of any one variable
or signal changes.
• Unlike $display, $monitor needs to be invoked only once.
• Only one monitoring list can be active at a time.
 Monitor Statement
//Monitor time and value of the signals clock and reset
//Clock toggles every 5 time units and reset goes down at 10
time units
initial
begin
$monitor($time," Value of signals clock = %b reset = %b",
clock,reset);
end
• Partial output of the monitor statement:
-- 0 Value of signals clock = 0 reset = 1
-- 5 Value of signals clock = 1 reset = 1
-- 10 Value of signals clock = 0 reset = 0
• The task $stop is provided to stop during a simulation.
Usage: $stop;
• The $finish task terminates the simulation.
Usage: $finish;
 Compiler Directives
• Compiler directives are provided in Verilog.
• All compiler directives are defined by using the `<keyword>
construct.
• Two most useful compiler directives.
• `define
• The `define directive is used to define text macros in Verilog.
• The Verilog compiler substitutes the text of the macro
wherever it encounters a `<macro_name>.
• This is similar to the #define construct in C.
• The defined constants or text macros are used in the Verilog
code by preceding them with a ` (back tick).
`define Directive
• //define a text macro that defines default word size
• //Used as 'WORD_SIZE in the code
'define WORD_SIZE 32
• //define an alias. A $stop will be substituted wherever 'S appears
'define S $stop;
• //define a frequently used text string
'define WORD_REG reg [31:0]
• // you can then define a 32-bit register as 'WORD_REG reg32;
`include
• The `include directive allows you to include entire contents of a Verilog source file in
another Verilog file during compilation.
• This works similarly to the #include in the C programming language.
• This directive is typically used to include header files, which typically contain global or
commonly used definitions.
`include Directive
• // Include the file header.v, which contains declarations in the
• // main verilog file design.v.
• 'include header.v
• ...
• ...
• <Verilog code in file design.v>
• (-) Means no input/colour (Moore machine)
• To represent three states we need 2-bits (binary encoding)
• State 11 is invalid
`timescale 1ns / 1ps
module cyclic_lamp (clk, light); s1: begin
input clk; light <= yellow;
state<= s2;
output reg [0:2] light;
end
parameter s0=0, s1=1, s2=2; s2: begin
parameter red=3'b100, light <= red;
green=3'b010, yellow=3'b001; state<= s0;
reg [0:1] state; end
default : begin
always @(posedge clk)
light <= red;
case (state) <=
state<= s0;
s0: begin end
light <= green; endcase
state<= s1; endmodule
end
• Nonblocking assignments (<=) are used
• Synthesis tool generates 2FFs for states because it has to remember it and
3FFs for light.
• This is because non blocking assignments are triggered by clock for both
state and light,
 Optimized Code
`timescale 1ns / 1ps
// blocking assignment
module cyclic_lamp(clk,light); always @(state)
input clk; case (state)
output reg [0:2] light; s0: light = red;
parameter s0=0,s1=1,s2=2; s1: light = green;
s2: light = yellow;
parameter red=3'b100,
default : light<= red;
green=3'b010,
endcase
yellow=3'b001;
endmodule
reg [0:1] state;
Two always blocks.
always @(posedge clk)
• First always block (non blocking assignments):
case (state) only the state change happens as soon as
s0: state <= s1; positive edge of the clock comes
s1: state <= s2; (S0,S1,S2 Sequential Circuit)
s2: state <= s0; • Second always block (blocking assignment) :
triggering is not by clock, but by state.
default : state<= s0;
• whenever state changes synthesis tool can
endcase actually find out that what will be the output just
from the state. So, it will be a combinational
circuit.
`timescale 1ns / 1ps
module Test_light();
reg clk;
wire [0:2] light;
cyclic_lamp L0(clk, light);
always #5 clk=~clk;
initial
begin
clk=1'b0;
$monitor($time,"RGY: %b", light);
#100 $finish;
end
endmodule
• n-bit word
• Parity - whether the number of 1s in that word is odd or even.
• Odd- it is odd parity
• Even - even parity.
`timescale 1ns / 1ps
always @(even_odd)
module Moore_parity(x,clk,z); case (even_odd)
input x,clk; EVEN: z=0;
output reg z; ODD: z=1;
reg even_odd; endcase
parameter EVEN=0, ODD=1; endmodule

always @ (posedge clk)

case (even_odd)
EVEN: even_odd <=x ? ODD : EVEN;
ODD: even_odd <=x ? EVEN : ODD;
default : even_odd <= EVEN;
endcase
`timescale 1ns / 1ps
s1: begin
// sequence detector "0110" z = x ? 0: 0;
module Seq_detect(x,clk,reset,z); NS = x ? s2 : s1;
input x,clk,reset; end
output reg z; s2: begin
z = x ? 0: 0;
parameter s0=0,s1=1,s2=2,s3=3;
NS = x ? s3 :s1;
reg [0:1] PS,NS; end
always @(posedge clk or posedge s3:
reset) begin
if (reset) z = x ? 0: 1;
PS <= s0; NS = x ? s0 : s1;
end
else PS <= NS;
endcase
always @(PS, x) endmodule
case (PS)
s0:
begin
z = x ? 0: 0;
NS = x ? s0 : s1;
end
 Example 4
• Sequence detector “101010”
Ex: To detect three consecutive 1’s

Need at list four states

A- initial state-reset
B- seen 1st – 1
C- seen two -1’s
D – seen three -1’s