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0% found this document useful (0 votes)
13 views23 pages

Display 16x2

The document appears to contain technical specifications and parameters related to electronic components, including cycle times and pulse widths. It includes various symbols and conditions for measurements, likely intended for engineers or technicians. The content is heavily encoded or formatted, making it difficult to interpret without additional context.

Uploaded by

Arturo May
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Read Cycle (VDD = 5.0V, GND = VEE = 0V, TA = 25qC)

Symbol Parameter Min. Typ. Max. Unit Conditions

tCYCE Enable Cycle Time 500 - - ns Figure 1

tWHE Enable "H" Level Pulse Width 300 - - ns Figure 1

tRE, tFE Enable Rise/Fall Time - - 25 ns Figure 1

1
60
tAS RS, R/W Setup Time - - ns Figure 1
2
100

tAH RS, R/W Address Hold Time 10 - - ns Figure 1

tRD Read Data Output Delay - - 190 ns Figure 1

tDHR Read Data Hold Time 20 - - ns Figure 1

Write Cycle (VDD = 5.0V, GND = VEE = 0V, TA = 25qC)

Symbol Parameter Min. Typ. Max. Unit Conditions

tCYCE Enable Cycle Time 500 - - ns Figure 2

tWHE Enable "H" Level Pulse Width 300 - - ns Figure 2

tRE, tFE Enable Rise/Fall Time - - 25 ns Figure 2

1
60
tAS RS, R/W Setup Time - - ns Figure 2
2
100

tAH RS, R/W Address Hold Time 10 - - ns Figure 2

tDS Data Output Delay 100 - - ns Figure 2

tDHR Data Hold Time 10 - - ns Figure 2

Notes: 1: 8-bit operation mode


2: 4-bit operation mode


Timing Waveforms

Read Operation

V IH1 V IH1
RS
V IL1 V IL1
tA S tA H

V IH1
R/W
tA H
tW E M

tF E
V IH1
E V IL1
V IL1 V IL1
tR E tD H R
tR D

V IH1 V IH1
DB0~DB7 VALD DATA
V IL1 V IL1
tC Y C E

Figure 1. Bus Read Operation Sequence


(Reading out data from NT3881D to MPU)

Write Operation

V IH1 V IH1
RS
V IL1 V IL1
tA S
tA H

R/W
V IL1 V IL1
tA H
tW E M
tFE
V IH1 V IH1
E V IL1
V IL1 V IL1
tR E
tD H W
tD S

V IH1 V IH1
DB0 ~ DB7 VALD DATA
V IL1 V IL1
tC Y C E

Figure 2. Bus Write Operation Sequence


(Writing data from MPU to NT3881D)


+(?  2

Execution
Instruction Code Function time (max)
(fOSC =
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
250KHz)
Clear entire display area, restore
Display Clear 0 0 0 0 0 0 0 0 0 1 display from shift, and load
address counter with DD RAM 1.64ms
address 00H.
Display/ Restore display from shift and
Cursor Home 0 0 0 0 0 0 0 0 1 * load address counter with DD 1.64ms
RAM address 00H.
Specify direction of cursor
Entry Mode movement and display shift
Set 0 0 0 0 0 0 0 1 I/D S mode. This operation takes 40Ps
place after each data transfer
(read/write).
Specify activation of display (D)
Display 0 0 0 0 0 0 1 D C B cursor (C) and blinking of 40Ps
ON/OFF character at cursor position (B).
Display/ 0 0 0 0 0 1 S/C R/L * * Shift display or move cursor. 40Ps
Cursor Shift
Set interface data length (DL),
Function Set 0 0 0 0 1 DL N F * * number of display line (N), and 40Ps
character font (F).
Load the address counter with a
RAM Address 0 0 0 1 ACG CG RAM address. Subsequent 40Ps
Set data access is for CG RAM
data.
Load the address counter with a
DD RAM 0 0 1 ADD DD RAM address. Subsequent 40Ps
Address Set data access is for DD RAM
data.
Busy Flag/ Read Busy Flag (BF) and
Address 0 1 AC contents of Address Counter 40Ps
Counter Read (AC).
CG RAM/ Write data to CG RAM or DD 40Ps
DD RAM 1 0 Write data RAM.
Data Write
CG RAM/ Read data from CG RAM or DD 40Ps
DD RAM 1 1 Read data RAM.
Data Read
I/D = 1 : Increment I/D = 0 : Decrement
S = 1 : Display Shift On DD RAM : Display Data RAM
D = 1 : Display On
C = 1 : Cursor Display On CG RAM : Character Generator
B = 1 : Cursor Blink On RAM
S/C = 1 : Shift Display S/C = 0 : Move Cursor ACG : Character Generator
R/L = 1 : Shift Right R/L = 0 : Shift Left RAM Address
DL = 1 : 8-Bit DL = 0 : 4-Bit ADD : Display Data RAM
N = 1 : Dual Line N = 0 : Signal Line Address
F = 1 : 5x10 dots F = 0 : 5x8 dots AC : Address Counter
BF = 1 : Internal Operation
BF = 1 : Ready for Instruction

Note 1: Symbol "*" signifies an insignificant bit (disregard).


Note 2: Correct input value for "N" is predetermined for each model.


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