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202217B2120 Digital Design Assignment-2

The document outlines the design of a Synchronous Mod-12 Counter using JK flip-flops, detailing the selection of four flip-flops and their connections to a common clock signal. It explains the state transition logic necessary for the counter to follow the decimal counting sequence from 0 to 11 and emphasizes the importance of a feedback loop for sequential counting. Additionally, it mentions the need for an initial state and the provision of a clock signal to control the counter's increments.

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Attupurath Dhanush
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10 views4 pages

202217B2120 Digital Design Assignment-2

The document outlines the design of a Synchronous Mod-12 Counter using JK flip-flops, detailing the selection of four flip-flops and their connections to a common clock signal. It explains the state transition logic necessary for the counter to follow the decimal counting sequence from 0 to 11 and emphasizes the importance of a feedback loop for sequential counting. Additionally, it mentions the need for an initial state and the provision of a clock signal to control the counter's increments.

Uploaded by

Attupurath Dhanush
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Digital Design

Assignment - 2
Design of a Synchronous Mod-12 Counter using clocked
JK flip-flops:

1. JK Flip-Flops Selection:
Choose four JK flip-flops for the counter. JK flip-flops are suitable for this
application because they can toggle their outputs based on the clock
signal and the current state.

2. Connections:
Connect the clock input (CLK) of all flip-flops to the same clock signal.
This ensures that all flip-flops change state simultaneously on each
clock pulse.
Connect the J and K inputs of each flip-flop based on the desired state
transitions. Since we are designing a Mod-12 counter, each flip-flop
should transition to the next state according to the decimal counting
sequence (0 to 11).

3. State Transition Logic:


Determine the state transition logic for each flip-flop to achieve the
Mod-12 counting sequence. This involves setting the J and K inputs of
each flip-flop based on the current state and the desired next state.
For example, to transition from state 0000 to 0001, the J and K inputs
of the least significant bit (LSB) flip-flop should be J=0, K=1. The J and
K inputs of the other flip-flops would be set accordingly to ensure
proper counting.

4. Feedback Loop:
Connect the outputs (Q) of each flip-flop to the appropriate inputs (J
and K) of the next flip-flop in sequence. This creates a feedback loop
that allows the counter to increment sequentially.

5. Initial State:
Decide on the initial state of the counter. This could be all zeros (0000)
or any other desired starting state depending on the specific
application requirements.

6. Clock Signal:
Provide a clock signal to the clock inputs of all flip-flops. The clock
signal determines when the counter increments to the next state. The

Dhanush.A.R
202217B2120
Digital Design
Assignment - 2
counter will advance on each rising or falling edge of the clock signal,
depending on the design.

Transition Table:

Dhanush.A.R
202217B2120
Digital Design
Assignment - 2

Gate Diagram:

Dhanush.A.R
202217B2120
Digital Design
Assignment - 2

Dhanush.A.R
202217B2120

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