18EC430 – CMOS VLSI Systems

Module I - CMOS Logic and Layout Design

Dr.N.B.BALAMURUGAN,
Associate Professor,
ECE Department
Thiagarajar College of Engineering
Madurai-15
Email : [email protected]
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Consistent Euler Path
X
PUN
A
j C C
B
X i VDD
X = C • (A + B)
C B j A
i PDN
A B GND A B C
A
B
C

May 13,2004 Optimal layout of CMOS Functional Arrays 73

 Example - Euler Path
• A path through all nodes in the graph such that each edge is visited once and
only once.

• The sequence of signals on the path is the signal ordering for the inputs.

• PUN and PDN Euler paths are (must be) consistent (same sequence)

• If you can define a Euler path then you can generate a layout with no diffusion
breaks

• ABC
• CAB
• B C A 🡪 no PDN
• BAC
• A C B -> no PDN
• CBA
Example - Euler Path

We consider the following logic

Circuit (a and b), the derived
Euler Path (c) and the
corresponding Layout. For our
Euler path the PUN- and the
PDN -----.

May 13,2004 Optimal layout of CMOS Functional Arrays 75

 Layout of Basic Structures
Basic Structure of nWell
❒ nWell technology
1. Start with p-type substrate
2. nWell
3. Active
4. Poly
5. pSelect
6. nSelect
7. Active contact Figure 5.2 Minimum line
8. Poly contact width and space

9. Metal1
10. Via ❒ Manhattan geometries
11. Metal2 » Where all turns are multiples of 90o
12. Overglass » If in an arbitrary manner, then must
be sure what the structures are
supported by the fabrication process
 nWell
• An n-well is required at every location where a pFET is to be made
– n-well must be connected to the power supply VDD when used for pFETs

Wnw = minimum width of an n-well mask feature

Snw-nw = minimum edge-to-edge spacing of adjacent n-wells

(a) Cross-section (b) Mask set

Figure 5.3 n-well structure and mask

 Active Areas
❒ Silicon devices are built on active areas of the substrate

Wa = minimum width of an Active feature

Sa-a = minimum edge-to-edge spacing of Active mask polygons

FOX = NOT (Active) (5.1)

FOX + Active = Surface (5.2)

(a) Cross-section (b) Active patterns

Figure 5.4 Active area definition

 Doped Silicon Regions
❒ Thermal technique called diffusion
» Create n+ (ndiff, [砷, As] or [磷, p] )
and p+ (pdiff, [硼, B] ) regions

n+ = (nSelect) (Active)
(5.3)
(a) Cross-section (b) Mask set
Wa = minimum width of an Active area
Sa-n = minimum Active-to-nSelect spacing Figure 5.5 Design of a n+ regions

p+ = (pSelect) (Active) (nWell)

(5.4)
Wa = minimum width of an Active area
Sa-p = minimum Active-to-pSelect spacing
Sp-nw = minimum pSelect-to-nSelect spacing
(a) Cross-section (b) Mask set

Figure 5.6 Design of a p+ regions

 MOSFETs (1/2)
❒ Physically, the poly line is deposited before
the ion implant, and acts to block dopants
from entering the silicon
❒ nFETs

Wp = minimum poly width (a) Cross-section (b) Layout view

Sp-p = minimum poly-to-poly spacing Figure 5.7 nFET structure
L = Wp = minimum width (length) of a Poly line
dpo = minimum extension of Poly beyond Active

nFET = (nSelect) (Active) (Poly) (5.5)

n+ = (nSelect) (Active) (NOT [Poly]) (5.6)

Figure 5.8 Masks for the nFET

 MOSFETs (2/2)
• pFETs
pFET = (pSelect) (Active) (Poly) (nWell) (5.7)
p+ = (pSelect) (Active) (nWell) (NOT [Poly] ) (5.8)

(a) Cross-section (b) Layout view

Figure 5.9 pFET structure Figure 5.10 Masks for the pFET
 Drawn and Effective in MOSFETs
• Draw and Effective Values in MOSFETs
– The critical dimensions of a MOSFET are the
channel length L and the channel width W
• The physical length is small than L due to
lateral doping during the implant annealing
step
– Leff: electrical or effective channel length (a) Drawn Layout
– Lo: overlap distance on both sides
Leff = L – 2Lo (5.9)
Leff = L - ΔL (5.10)
• The channel width is also small than the
drawn value due to reduction of active area
by the field oxide growth
(b) Finished view
Weff = W – ΔW (5.11)
Figure 5.11 Drawn and effective
dimensions of a MOSFET
(5.12)
 Active Contacts
• An active contact is a cut in the Ox1 that
allows the first layer of metal1 to contact an
active n+ or p+ region
Sa-ac = minimum spacing between Active and Active Contact
dac, v = vertical size of the contact
dac, h = horizontal size of the contact (a) Cross-section

• A square contact is obtained if, however, it is

not uncommon to have aspect rations other
than 1:1 (b) General mask set
dac, v = dac, h = dac
Figure 5.12 Active contact
formation
 Metal1 (1/3)
• Metal1 is used as interconnect for signals and power
supply distribution

(a) Cross-section
Wm1 = minimum width of a Metal1 line
Sm1-ac = minimum spacing from Metal1 to Active Contact

– Every contact is characterized by a resistance

Rc = contact resistance Ω (b) General mask set

Figure 5.13 Metal1 line with
– Since the contacts are all in parallel, the effective Active Contact
resistance of the Metal1-Active connection with N
contacts is reduced to

(5.14)

Figure 5.14 Multiple contacts

 Metal1 (2/3)
❒ Metal1 allows access to the active regions
of MOSFETs using the Active Contact
oxide cut as Figure 5.15

Sp-ac = minimum spacing from Poly to Active

Contact (a) Cross-section (b) Layout
Sa-p = minimum spacing from Active to Poly
Figure 5.15 Drain and source
FET terminals using Metal1

❒ A Poly Contact mask is used to allow

electrical connections between Metal1 and
the polysilicon gate as Figure 5.16

Sp-p = minimum Poly-to-Poly spacing

(a) Cross-section (b) Layout

Figure 5.16 Poly Contact

 Metal1 (3/3)
• Example: A pair of series-connected FETs
sharing the central n+ region as Figure 5.17

Sp-p = minimum Poly-to-Poly spacing

• Example: Parallel-connected FETs as Figure

(a) Cross-section (b) Layout
5.18
Figure 5.17 Series-connected FETs

Sg-g = dac + 2 Sp-ac (distance between the two gates)

• Example: allow for the size of the contact
itself, plus two units of poly-active spacing
as Figure 5.19
– Enforced twice Sp-a
Figure 5.18 Figure 5.19 Different
Parallel-connected channel widths using
nFETs the same active region
 Vias and Higher Level Metals
❒ Model CMOS processes add several additional
layers of metal that can be used for signal and
power distribution

Metal1 → Metal2 → Metal3 → Metal4

(a) Cross-section

dv = dimension of a Via (may be different for vertical direction)

wm2 = minimum width of Metal2 feature
sm2-m2 = minimum spacing between adjacent Metal2 features
sv-m1 = minimum spacing between Via and Metal1 edges
Sv-m2 = minimum spacing between Via and Metal2 edges
(b) Layout

Figure 5.20 Metal1-Metal2

connection using a Via mask
 CMOS Latchup

• There is one major downfall to the CMOS logic

gate – Latchup

• There are many safeguards that are done during

fabrication to suppress this, but it can still occur
under certain transient or fault conditions
 CMOS Latchup

• Latchup occurs due parasitic bipolar transistors

that exist in the basic inverter as shown below
CMOS Latchup
• The configuration of
these bipolar
transistors create a
positive feedback
loop, and will cause
the logic gate to
latchup as shown to
the left
• By using heavily
doped material
where Rn and Rp
exist, there
resistance will be
lowered thereby
reducing the chance
of latchup occurring
 CMOS Latchup

• Suppose a base current iBN begins to flow in the base of

the npn transistor. This base current is amplified by the
npn current gain βN an must be supplied from the base
of the pnp transistor. The pnp base current is then
amplified further by the current gain βP of the pnp
transistor, yielding a collector current equal to
• iCP = βPiBP = βP(βNiBN) (8.26)
 CMOS Latchup
• Once the circuit has entered the latchup state, both
transistors saturate, and the voltage across the structure
collapses to one diode drop plus one saturation voltage.
• V = VEB+VCESAT = VBE + VECSAT (8.27)
• After latch up happened, the current increases to
(VDD-0.8)/RC. The current level is only limited by the
external circuit components.
• Large currents and power dissipation can rapidly destroy
most CMOS structures. e.g. electro-migration will damage
the metal lines.
 CMOS Latchup

• Latchup would not occur in an ideal structure for which

Rn = 0 = Rp – modern CMOS technology uses special
substrates and processing to minimize the values of
these two resistors.
• A fault or transient occurs that causes one of the source
or drain diffusions to momentarily exceed the power
supply voltage levels, the latchup can be triggered.
• Ionizing radiation or intense optical illumination are
two other possible sources of latchup initiation.
 Latch-up Prevention

◆ Latchup resistant CMOS processes – reduce the

gain the the parasitic transistors.
◆ Layout techniques - Use substrate contact to
reduce Rn & Rp.
 Latch-up Prevention
❒ Latch-up: is a condition that can occur in a circuit
fabricated in a bulk CMOS technology
» The key to understanding latch-up is noting that the
bulk technology gives a 4-layers pnpn structure
between the power supply VDD and ground
» If VDD reaches the breakover voltage VBO, the Figure 5.21 Latch-up current
flow path
blocking is overwhelmed by internal electric fields

❒ Latch-up avoiding method

» to steer the current out of the “bad” path
Include and n-Well contact every time a pFET is connected
to the power supply VDD, and
Include a p-substrate contact every time and nFET is
connected to a ground rail
» Silicon-on-insulator, SOI
» Twintub: using two separate wells for FETs, an n-well (a) Structure (b) Behavior

for pFETs and a p-well for nFETs Figure 5.22 Characteristics of

4-layer pnpn device
 FET Sizing
• FET are specified by the aspect ratio (W/L)
– Combine with the processing parameters to give the
electrical characteristic of the transistor
– Given the gate area by AG = LW

CG = CoxWL (5.19)

– Since
(5.21, 5.22)

(5.24, 5.25) (r = 2 ~ 3) Figure 5.36 Basic geometry

– Since of a FET

(5.26) pFETs don’t conduct as well as nFETs

(5.27) (Since C is proportional to W)

 Unit Transistors
❒ Unit transistor is the minimum-size
MOSFET

(5.30) ( the aspect ratio )

(5.31) ( gate capacitance) Figure 5.37 Geometry of a

minimum-size FET

dc = dimension of the contact

sa-ac = spacing between Active and Active Contact

» As Figure 5.38, the minimum width is

now

W = dc + 2sa-ac (5.32) (a) Active contact (b) Small Wa

Figure 5.38 Minimum-size FETs

with Active Contact features
 Scaling Technology
• Once a unit FET has been selected, it’s useful to
allow it to be scaled in size
– Reference 1X 🡪 2X 🡪 4X
– However, Altering the size of the transistor
changes its resistance and capacitance
• Denote R1X and C1X be the R and C of the 1X
device Figure 5.39 Scaling of the unit transistor

(5.33) (S: Scaling factor)

(5.34) (S = 4)

(5.35) (decided by FET size)

(5.36) (S = 2)
Figure 5.40 Scaling of series-connected
FET chain
(5.37) (Figure 5.40)
 The Not Cell

(a) Schematic (a) Basic cell

(b) Cell layout (b) 2X cell

Figure 5.42 NOT gate width horizontal FETs Figure 5.43 Not layout using vertical FETs
 NAND2 and NOR2

(a) NAND2 (a) NAND2

(b) NOR2 (b) NOR2 Figure 5.47 Complex logic

gate example
Figure 5.45 NAND2 and NOR2 Figure 5.46 Alternate
layouts using vertical FETS NAND2 and NOR2 cells
 CMOS Layers
N-well Process
• CMOS fabrication process: In simplest terms, this refers to the sequence of
steps that we use to take a bare “wafer” of silicon to the finished form of
an electronic integrated circuit

■ p-substrate
■ n-well
■ n+ (nFET drain/source)
■ p+ (pFET drain/source)
■ gate oxide
■ gate (polysilicon)
Figure 3.23 MOSFET layers in an n-well process
 Fabrication Process
• Modern processes tend to allow for five or
more metal interconnect layers to ease the
problem of massive wiring in complex circuits

Figure 3.24 Top view FET patterning

Figure 3.26 Interconnect layout example Figure 3.25 Metal interconnect layers