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Module Prescaler(

The document contains Verilog code for a clock prescaler module that converts a 50 MHz input clock to a 1 Hz output clock. It also includes a top module that instantiates the prescaler and a blinker module, which toggles an LED output at the 1 Hz clock rate. The design utilizes a 26-bit counter to manage the clock division.

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oyenugathanksgiving
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5 views2 pages

Module Prescaler(

The document contains Verilog code for a clock prescaler module that converts a 50 MHz input clock to a 1 Hz output clock. It also includes a top module that instantiates the prescaler and a blinker module, which toggles an LED output at the 1 Hz clock rate. The design utilizes a 26-bit counter to manage the clock division.

Uploaded by

oyenugathanksgiving
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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module prescaler(

input clkin, // 50 MHz input clock


output reg clkout // 1 Hz output clock
);
reg [25:0] counter; // 26-bit counter

always @(posedge clkin) begin


if (counter == 0) begin
counter <= 24999999;
clkout <= ~clkout;
end else begin
counter <= counter - 1;
end
end
endmodule

2.
module top (
input wire clk_50mhz, // 50 MHz clock input
output wire led // LED output
);

wire clk_1hz; // Slow clock signal

// Instantiate the prescaler module


prescaler u1 (
.clkin(clk_50mhz),
.clkout(clk_1hz)
);

// Instantiate the blinker module


blinker u2 (
.clk(clk_1hz),
.led(led)
);
endmodule

3.
module blinker (
input wire clk, // Input clock (Slow Clock)
output reg led // Output LED signal
);
always @(posedge clk) begin
led <= ~led;
end
endmodule

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