UNIT I

BOOLEAN ALGEBRA AND LOGIC GATES

Number Systems - Arithmetic Operations - Binary Codes- Boolean Algebra and Logic Gates - Theorems and
Properties of Boolean Algebra - Boolean Functions - Canonical and Standard Forms - Simplification of Boolean
Functions using Karnaugh Map - Logic Gates – NAND and NOR Implementations.

Introduction
Basically there are two types of signals in electronics,
i) Analog
ii) Digital
Digital
systems
Advantages:
 The usual advantages of digital circuits when compared to analog circuits are:Digital systems
interface well with computers and are easy to control with software. New features can often be added
to a digital system without changing hardware.
 Often this can be done outside of the factory by updating the product's software. So, the product's
design errors can be corrected after the product is in a customer's hands.
 Information storage can be easier in digital systems than in analog ones. The noise- immunity of
digital systems permits data to be stored and retrieved without degradation.
 In an analog system, noise from aging and wear degrade the information stored.
 In a digital system, as long as the total noise is below a certain level, the information can be
recovered perfectly.

Disadvantages:
 In some cases, digital circuits use more energy than analog circuits to accomplish the same tasks, thus
producing more heat as well. In portable or battery-powered systems this can limit use of digital
systems.
 Digital circuits are sometimes more expensive, especially in small quantit ies.The sensed world is
analog, and signals from this world are analog quantities.
 Digital circuits are sometimes more expensive, especially in small quantities. The sensed world is
analog, and signals from this world are analog quantities.
 For example, light, temperature, sound, electrical conductivity, electric and magnetic fields are
analog.
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 REVIEW OFNUMBER SYSTEMS

Many number systems are in use in digital technology. The most common are the decimal,
binary, octal, and hexadecimal systems. The decimal system is clearly the most familiar to us because it
is tools that we use every day.

Types of Number Systems are

 Decimal Number system
 Binary Number system
 Octal Number system
 Hexadecimal Number system

Table: Types of Number Systems

DECIMAL BINARY OCTAL HEXADECIMAL

0 0000 0 0
1 0001 1 1
2 0010 2 2
3 0011 3 3
4 0100 4 4
5 0101 5 5
6 0110 6 6
7 0111 7 7
8 1000 10 8
9 1001 11 9
10 1010 12 A
11 1011 13 B
12 1100 14 C
13 1101 15 D
14 1110 16 E
15 1111 17 F

Table: Numbersystemandtheir Base value

Number Systems
System Base Digits
Binary 2 01
Octal 8 01234567
Decimal 10 0123456789
Hexadecimal 16 0123456789ABC DEF

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 Code Conversion:

 Convertingfromonecodeformtoanothercodeformiscalledcodeconversion,likeconvertingfrom binaryto
decimal orconverting from hexadecimal to decimal.

Binary-To-DecimalConversion:
Anybinarynumbercanbeconvertedtoitsdecimalequivalent simplybysummingtogether
theweights of the variouspositions in the binarynumber whichcontaina1.

Binary Decimal
110112
=24 3 1 1 0 =16+8+0+2+1
+2 +0 +2 +2
Result 2710

Decimal to binary Conversion:

Division Remainder Binary

25/2 =12+remainder of1 1 (LeastSignificantBit)
12/2 =6 +remainder of0 0
6/2 =3 +remainder of0 0
3/2 =1 +remainder of1 1
½ =0 +remainder of1 1 (MostSignificantBit)
Result 2510 =110012

Binary to octal:
Example: 100 1110102=(100)(111)(010)2=4 7 28

Octal to Binary:

Decimal to octal:
Division Result Binary
177/8 =22+remainder of1 1 (LeastSignificantBit)
22/ 8 =2 +remainder of6 6
2/8 =0 +remainder of2 2 (Most Significant Bit)
Result 17710 =2618
Binary =0101100012

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 Octal to Decimal:
Example:

Decimal to Hexadecimal:

Division Result Hexadecimal

378/16 =23+remainder of10 A(LeastSignificantBit)23
23/16 =1 +remainder of7 7
1/16 =0 +remainder of1 1 (Most Significant Bit)
Result 37810 =17A16
Binary =00010111 10102

Binary-To-Hexadecimal:
Example: 1011 0010 11112= (1011) (0010) (1111)2=B2F16

Hexadecimal to binary:

Octal-To-Hexadecimal / Hexadecimal-To-Octal Conversion:

 Convert Octal (Hexadecimal) to Binary first.
 Regroup the binary number by three bits per group starting from LSB if Octal is required.
 Regroup the binary number by four bits per group starting from LSB if Hexadecimal is required.

Octal to Hexadecimal: (May 2014)

Octal Hexadecimal
=2 6 5 0
= 010 110101000 =0101 1010 1000(Binary)
Result =(5A8)16

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 Hexadecimal to octal:

Hexadecimal Octal
(5A8)16 =0101 1010 1000(Binary)
=010 110101000(Binary)
Result =2 6 5 0(Octal)

1’s and2’s complement:

 Complements are used in digital computers to simplify the subtraction operation and for logical
manipulation.
 ThereareTWOtypesofcomplementsforeachbase-rsystem: theradixcomplementand the diminished
radix complement.
 The first is referred to as there’s complement and the second as the (r-
1)'scomplement,whenthevalueofthebaserissubstitutedinthename.Thetwo typesarereferredtoasthe
2's complement and 1's complement for binary numbers and the 10’s complement and 9's
complement for decimal numbers.

Note:
 The1 ’ scompl ement ofabinarynumberi sthenumbert hat result sw henw
echangeall 1 ’ s to zeros and the zeros t o ones.
 The2 ’ s complement is the bi nary number t hat result s whenweadd 1 t o the
1’ s compl ement .
 I t is used t o represent negati venumbers.

2’s complement=1’scomple ment+1

Example 1) : Find 1’s complement of (1101)2

Sol: 1101 Number
0010 1’s complement

Example 2) : Find 2’s complement of (1001)2

Sol: 1001 number

0110 1’s complement

+ 1

0111

Diminished Radix Complement:

Given a number N in base r having n digits, the (r - 1)’s complement of N, i.e., its
diminished radix complement, is defined as (rn- 1) - N.
The9’s comple mentof546700 is 999999-546700= 453299.
The9’s comple mentof012398 is 999999-012398= 987601.

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Radix Complement:
The r’s complement of an n-digit number N in base r is defined as rn- N for N≠0 and as
0 for N = 0.

For examples:
The10’scomplementof 012398 is 987602
The10’scomplementof246700 is 753300

Model 1: (Dec 2009)

Using10’scomple ment, subtract72532-3250.
M= 72532
10’s complement o fN = +96750
Sum = 169282
Discard endcarry105 = -100000
Answer = 69282

Model 2:
Using10’scomple ment, subtract3250-72532.
M = 03250
10>s complementofN = +27468
Sum = 30718

Model 3:
Given the two binary numbers X = 1010100andY= 1000011, performthesubtraction
(a)X-Y and (b) Y-Xbyusing2’scomple ments. [NOV – 2019]
(a) X= 1010100
2’s complementofY= + 0111101
Sum = 10010001
Discard endcarry27 = -10000000
Answer:X-Y= 0010001

(b) Y= 1000011

2’s complement of X= 0101100

Sum = 1101111
There is no end carry.Therefore, the answer isY- X=-(2 ’s complementof1101111) =
-0010001.

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Model 4:
Given the two binary numbers X=1010100 and Y= 1000011, perform the subtraction (a) X-Y and
(b) Y-X by using 1’s complements. (Dec 2009)

(a) X-Y= 1010100-1000011

X= 1010100
1’s complementofY= +0111100
Sum = 10010000
End around carry = + 1
Answer:X-Y= 0010001
(b) Y-X= 1000011-1010100
Y= 1000011
1’s complement of X= +0101011
Sum = 1101110
There is no end carry. Therefore ,the answer is Y- X=-(1’s complementof1101110)=
-0010001.

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ARITHMETIC OPERATIONS

Binary Addition:

Rules of Binary Addition

 0 +0 =0
 0 +1 =1
 1 +0 =1
 1 +1 =0,and carry1tothe next most significant bit

Example:

Add: 00011010+00001100=00100110

1 1

0 0 0 1 1 0 1 0
+0 0 0 0 1 1 0 0
0 0 1 0 0 1 1 0

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Binary Subtraction:

Rules of Binary Subtraction

 0 -0 =0
 0 -1 =1,and borrow 1fromthe nextmoresignificantbit
 1 -0 =1
 1 -1 =0

Example:
Sub: 00100101-00010001= 00010100
0 0 1 0 0 1 0 1
-0 0 0 1 0 0 0 1

0 0 0 1 0 1 0 0
Binary Multiplication:
RulesofBinaryMultiplication

 0 x 0 =0
 0 x 1 =0
 1 x 0 =0
 1 x 1 =1,andnocarryorborrowbits

Example:Multiply the following binary numbers:

(a) 0111 and 1101 (b) 1.011 and 10.01.

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Binary Division:
Binarydivisionisthe repeatedprocess ofsubtraction,justasindecimaldivision.
Example: Divide the following

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BINARYCODES
Explain the various codes used in digital systems with an example.(or)Explain in detail about Binary
codes with an example
 In digital systems a variety of codes are used to serve different purposes, such as data entry,
arithmetic operation, error detection and correction, etc.
 Selection of a particular codedepends on the requirement.
 Binarycodesarecodeswhicharerepresentedinbinarysystemwithmodification from the original ones.
 Codes can be broadly classified into five groups.
(i) Weighted Binary Codes
(ii) Non-weighted Codes
(iii) Error-detection Codes
(iv) Error-correcting Codes
(v) Alphanumeric Codes
Weighted Binary Codes
 If each position of a number represents a specific weight then the coding scheme is called weighted
binary code.
BCD Code or 8421 Code:
 The full form of BCD is ‘Binary-Coded Decimal’. Since this is a coding scheme relating decimal and
binary numbers, four bits are required to code each decimal number.
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  A decimal number in BCD (8421) is the same as its equivalent binary number only when the number
is between 0 and 9. A BCD number greater than 10 looks different from its equivalent binary
number, even though both contain 1’s and 0’s. Moreover,the binary combinations 1010 through 1111
are not used and have no meaning in BCD.
 Consider decimal 185 and its corresponding value in BCD and binary:

(185)10= (0001 1000 0101)BCD = (10111001)2

 For example, (35)10 is represented as 0011 0101 using BCD code, rather than (100011)2
 Example: Give the BCD equivalent for the decimal number 589.
The decimal number is 5 8 9
BCD code is 0101 1000 1001
Hence, (589)10 = (010110001001)BCD
2421 Code:
 Another weighted code is 2421 code. The weights assigned to the four digits are 2, 4,2, and 1.
 The 2421 code is the same as that in BCD from 0 to 4. However, it varies from5 to 9.
 For example, in this case the bit combination 0100 represents decimal 4; whereas the bit combination
1101 is interpreted as the decimal 7, as obtained from 2 × 1 + 1 × 4+ 0 × 2 + 1 × 1 = 7.
 This is also a self- complementary code.

BCD Addition:
Examples:
 Consider the addition of 184 + 576 = 760 in BCD:

 Add the following BCD numbers: (a) 1001 and 0100, (b) 00011001 and 00010100

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Non-weighted Codes
 It basically means that each position ofthe binary number is not assigned a fixed value.
 Excess-3 codes and Gray codes are such non-weighted codes.
Excess-3 code:
 Excess-3isanon- weightedcodeusedtoexpressdecimalnumbers.Thecodederivesitsnamefrom
thefactthateachbinarycodeisthecorresponding8421codeplus0011(3).

Example:1000of8421 (BCD)=1011in Excess-3

 Convert (367)10 into its Excess-3 code.

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 Graycode:
 Thegraycodebelongstoaclassofcodescalledminimumchangecodes,inwhichonlyonebitin
thecodechangeswhenmovingfrom onecodetothenext.
 TheGraycodeisnon-weightedcode,asthe positionofbitdoesnotcontainanyweight.In
digitalGraycodehasgot a specialplace.
Decimal BinaryCode GrayCode
Number
0 0000 0000
1 0001 0001
2 0010 0011
3 0011 0010
4 0100 0110
5 0101 0111
6 0110 0101
7 0111 0100
8 1000 1100
9 1001 1101
10 1010 1111
11 1011 1110
12 1100 1010
13 1101 1011
14 1110 1001
15 1111 1000

 Thegraycodeisareflective digitalcodewhichhas the special propertythat

anytwosubsequentnumberscodes differ byonlyonebit. This is also calledaunit-distance
code.
 Importantwhenananalogquantity mustbeconvertedtoadigitalrepresentation.Onlyonebitchanges
between two successiveintegers whicharebeing coded.

Example:
Binary toGray CodeConversion:
Any binary number can be converted into equivalent Gray code by the following steps:
i) the MSB of the Gray code is the same as the MSB of the binary number;
ii) the second bit next to the MSB of the Gray code equals the Ex-OR of the MSB and second bit of
the binary number; it will be 0 if there are same binary bits or it will be 1 for different binary
bits;
iii) the third bit for Gray code equals the exclusive-OR of the second and third bits of the binary
number, and similarly all the next lower order bits follow the same mechanism.

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 GrayCode to Binary Code Conversion:
Any Gray code can be converted into an equivalent binary number by the following steps:
i. The MSB of the binary number is the same as the MSB of the Gray code.
ii. the second bit next to the MSB of the binary number equals the Ex-OR of the MSB of the binary
number and second bit of the Gray code; it will be 0 if there are samebinary bits or it will be 1
for different binary bits;
iii. the third bit for the binary number equals the exclusive-OR of the second bit of the binary number
and third bit of the Gray code, and similarly all the next lower orderbits follow the same
mechanism.

Errordetectingcodes
 Whendataistransmittedfromonepointtoanother,likeinwirelesstransmission, or
itisjuststored, likeinharddisksandmemories,therearechancesthatdata maygetcorrupted.
 Todetectthesedata errors,weusespecialcodes,whichareerrordetection codes.

Twotypes ofparity
 Evenparity:Checksifthereisanevennumberofones;ifso,paritybitiszero.Whenthenumberof
one’sisoddthenparitybitissetto 1.
 OddParity:Checksifthereisanoddnumberofones;ifso,paritybitiszero. Whenthenumberof
one’siseventhenparitybitis set to 1.
Errorcorrectingcode
 Error-correctingcodesnotonlydetecterrors,butalsocorrectthem.
 Thisisused normallyinSatellite communication,whereturn-arounddelayisveryhighasisthe

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 probabilityofdata gettingcorrupt.

Hamming codes
 Hammingcodeaddsaminimumnumberofbitstothedatatransmitted inanoisychannel,tobeableto
correct everypossible one-bit error.
 It candetect(not correct)two-biterrorsandcannotdistinguish between1-bitand2-bits
inconsistencies. Itcan't- ingeneral-detect 3(ormore)-bits errors.

Alphanumeric Codes

 An alphanumeric code is a binary code of a group of elements consisting of ten decimal digits,
the 26 letters of the alphabet (both in uppercase and lowercase), and a certain number of special
symbols such as #, /, &, %, etc.

ASCII(AmericanStandardCode for InformationInterchange)

 It is actually a 7-bit code, where a character is represented with seven bits.
 The character is stored as one byte with one bit remainingunused.
 But often the extra bit is used to extend the ASCII to represent an additional128 characters.

EBCDIC codes
 EBCDICstandsforExtendedBinary CodedDecimalInterchange.
 It is also an alphanumeric code generally used in IBM equipment and in large computersfor
communicating alphanumeric data.
 For the different alphanumeric characters the code grouping in this code is different from the
ASCII code. It is actually an 8-bit code and a ninth bit is added as the parity bit.
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 Boolean Algebra and Theorems

Explain various theorems of Boolean algebra. (Nov – 2018)

Definition:
Boolean algebra is an algebraic structure defined by a set of elements B, together with two binary
operators. ‘+’ and ‘-‘, provided that the following (Huntington) postulates are satisfied;

Theorems of Boolean algebra:

The theorems of Boolean algebra can be used to simplify many a complex Boolean expression and also
to transform the given expression into a more useful and meaningful equivalent expression.

Postulates of Boolean algebra:

The postulates of a mathematical system form the basic assumptions from which itis possible to
deduce the rules, theorems, and properties of the system. The following are the important postulates of
Boolean algebra:
1. 1.1 = 1, 0+0 = 0.
2. 1.0 = 0.1 = 0, 0+1 = 1+0 = 1.
3. 0.0 = 0, 1+1 = 1
4. 1’ = 0 and 0’ = 1.
Many theorems of Boolean algebra are based on these postulates, which can be used to
simplifyBoolean expressions.
The operators and postulates have the following meanings:
 The binary operator + defines addition.
 The additive identity is 0.
 The additive inverse defines subtraction.
 The binary operator .(dot) defines multiplication.
 The multiplicative identity is 1.
 The only distributive law applicable is that of .(dot) over +:

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 a . (b + c) = (a . b) + (a . c)

Two‐Valued Boolean Algebra:

A two‐valued Boolean algebra is defined on a set of two elements, B = {0, 1}, with
rulesfor the two binary operators + and .(dot) as shown in the following operator tables.

Duality Principle:

The duality principle states that every algebraic expression deducible from the postulates of
Boolean algebra remains valid if the operators and identity elements are interchanged. If the dual of an
algebraic expression is desired, we simply interchange OR and AND operators and replace 1’s b y 0’s
and 0’s by 1’s.

DeMorgan’s theorem:
1. The complement of product is equal to the sum of their complements. (X.Y)’=X’+Y’
2. The complement of sum is equal to the product of their complements. (X+Y)’ = X’.Y’

Basic Theorems:
State and prove postulates and theorems of Boolean algebra.

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 Boolean Functions

 Boolean algebra is an algebra that deals with binary variables and logic operations. A Boolean
function described by an algebraic expression consists of binary variables, the constants 0 and 1, and
the logic operation symbols.
 For a given value of the binary variables, the function can be equal to either 1 or 0.

Example, consider the Boolean functionF1 = x + y’z

The function F1 is equal to 1 if x is equal to 1 or if both y’ and z are equal to 1. F1 is equalto 0 otherwise.
The complement operation dictates that when y’ = 1, y = 0. Therefore,F1 = 1 if x = 1 or if y = 0 and z =
1. A Boolean function expresses the logical relationshipbetween binary variables and is evaluated by
determining the binary value ofthe expression for all possible values of the variables. The gate
implementation of F1 is shown below.

Example: Consensus Law: (function 4)

Complement of a function:

The complement of a function F is obtained from an interchange of 0’s for 1’sand 1’s for 0’s in the
value of F.
Example:
1.

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 2. Find the complement of the functions F1 = x’yz’ + x’y’z and F2 = x(y’z’ + yz).
By applying DeMorgan’s theorems as many times as necessary, the complements areobtained as
follows:

3. Find the complement of the functions F1 = x’yz’ + x’y’z and F2 = x(y’z’ + yz) by taking their
duals and complementing each literals.
Solution:

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Canonical and Standard forms:
Explain canonical SOP & POS form with suitable example.

 Binary logic values obtained by the logical functions and logic variables are in binary form. An
arbitrary logic function can beexpressed in the following forms.
(i) Sum of the Products (SOP)
(ii) Product of the Sums (POS)
 Boolean functions expressed as a sum of minterms or product of maxterms are said to be in
canonical form.

Product term:
The AND function is referred to as a product. The variable in a product term can appear either in
complementary or uncomplimentary form. Example: ABC’
Sum term:
The OR function is referred to as a Sum. The variable in a sum term can appear either in
complementary or uncomplimentary form. Example: A+B+C’
Sum of Product (SOP):
The logical sum of two or more logical product terms is called sum of product expression. It is
basically an OR operation of AND operated variables. Example: Y=AB+BC+CA
Product of Sum (POS):
The logical product of two or more logical sum terms is called product of sum expression. It is
basically an AND operation of OR operated variables. Example: Y=(A+B).(B+C).(C+A)

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Minterm:
A product term containing all the K variables of the function in either complementary or
uncomplimentary form is called Minterm or standard product.

Maxterm:
A sum term containing all the K variables of the function in either complementary or
uncomplimentary form is called Maxterm or standard sum.

Canonical SOP Expression:

The minterms whosesum defines the Boolean function are those which give the 1’s of the
function in a truth table.
Procedure for obtaining Canonical SOP expression:
 Examine each term in a given logic function. Retain if it is a minterm, continue to examine the
next term in the same manner.
 Check for the variables that are missing in each product which is not minterm. Multiply the
product by (X+X’), for each variable X that is missing.
 Multiply all the products and omit the redundant terms.
Example:
Express the Boolean function F = A + B’C as a sum of minterms. (May -10)(Nov – 2018)
Solution:
The function hasthree variables: A, B, and C.
The first term A is missing two variables; therefore,
A = A(B + B’) = AB + AB’
This function is still missing one variable, so
A = AB(C + C’) + AB’(C + C’)
= ABC + ABC’ + AB’C + AB’C’
The second term B’C is missing one variable; hence,
B’C = B’C(A + A’) = AB’C + A’B’C

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 Combining all terms, we have
F = A + B’C =ABC + ABC’ + AB’C + AB’C’ + A’B’C
But AB’C appears twice, and according to theorem 1 (x + x = x), it is possible toremove one of
those occurrences. Rearranging the minterms in ascending order, wefinally obtain
F = A’B’C + AB’C’+ AB’C + ABC’ + ABC= m1 + m4 + m5 + m6 + m7
F(A, B, C) = ∑(1, 4, 5, 6, 7)

Example:Obtain the canonical sum of product form of the following function. (May 2014)

Canonical POS Expression:

The Maxterms whose product defines the Boolean function are those which give the 1’s of the
function in a truth table.
Procedure for obtaining Canonical POS expression:
 Examine each term in a given logic function. Retain if it is a maxterm, continue to e xamine the
next term in the same manner.
 Check for the variables that are missing in each sum which is not maxterm. Add (X.X’), for each
variable X that is missing.
 Expand the expression using distributive property eliminate the redundant terms.
Example:

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Example:
Obtain the canonical product of the sum form of the following function.
F (A, B, C) = (A + B′) (B + C) (A + C′) (Dec 2012)
Solution:

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Karnaugh Map (K-map):

 Using Boolean algebra to simplify Boolean expressions can be difficult. The Karnaugh map provides
a simple and straight- forward method of minimizing Boolean expressions which represent
combinational logic circuits.
 A Karnaugh map is a pictorial method of grouping together expressions with common factors and
then eliminating unwanted variables.
 A Karnaugh map is a two-dimensional truth-table. Note that the squares are numbered so that the
binary representations for the numbers of two adjacent squares differ in exactly one position.

Rules for Grouping together adjacent cells containing 1's:

 Groups must contain 1, 2, 4, 8, 16 (2n) cells.
 Groups must contain only 1 (and X if don't care is allowed).
 Groups may be horizontal or vertical, but not diagonal.
 Groups should be as large as possible.
 Each cell containing a 1 must be in at least one group.
 Groups may overlap.
 Groups may wrap around the table. The leftmost cell in a row may be grouped with the rightmost
cell and the top cell in a column may be grouped with the bottom cell.
 There should be as few groups as possible.

Obtaining Product Terms

 If A is a variable that has value 0 in all of the squares in the grouping, then the complemented
form A is in the product term.
 If A is a variable that has value 1 in all of the squares in the grouping, then the true form A is in
the product term.

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  If A is a variable that has value 0 for some squares in the grouping and value 1 for others, then it
is not in the product term

The Format of K-Maps:

K-Maps of 2 Variables:

K-Maps of 3 Variables:
 Simplify the boolean function F (x, y, z) =

 Simplify the boolean function F (x, y, z) =

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 K-Maps of 4 Variables:

 Simplify the boolean function F(w,x,y, z) =

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Note:

Karnaugh Maps - Rules of Simplification

The Karnaugh map uses the following rules for the simplification of expressions by grouping
together adjacent cells containing ones

 Groups may not include any cell containing a zero

 Groups may be horizontal or vertical, but not diagonal.

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  Groups must contain 1, 2, 4, 8, or in general 2n cells. That is if n = 1, a group will
contain two 1's since 21 = 2. If n = 2, a group will contain four 1's since 22 = 4.

 Each group should be as large as possible.

 Each cell containing a one must be in at least one group.

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  Groups may overlap.

 There should be as few groups as possible, as long as this does not contradict any of
the previous rules.

Summmary:

1. No zeros allowed.
2. No diagonals.
3. Only power of 2 numbers of cells in each group.
4. Groups should be as large as possible.
5. Everyone must be in at least one group.
6. Overlapping allowed.
7. Wrap around allowed.
8. Fewest numbers of groups possible.

Don’t care combination:

In certain digital systems, some input combinations never occur during the process of normal
operation because those input conditions are guaranteed never to occur. Such input combinations are
don’t care conditions.

B.ARUNKUMAR, Asst. Prof.,/ECE Page 29

Completely specified functions:

If a function is completely specified, it assumes the value 1 for some input combinations and the
value 0 for others.

Incompletely specified functions:

There are functions which assume the value 1 for some combinations and 0 for some other and
either 0 or 1 for the remaining combinations. Such a functions are called incompletely specified .

Prime Implicants:

A primeimplicant is a product term obtained by combining the maximum possible number

ofadjacent squares in the map. If a minterm in a square is covered by only one primeimplicant, that prime
implicant is said to be essential.

**************************************

Quine-McCluskey (or) Tabulation Method

Minimization of Logic functions:

Steps:

 A set of all prime implicants of the function must be obtained.

 From the set of prime implicants, a set of essential implicants must be determined by
preparing a prime implicant chart.

 The minterm which are not covered by the essentia l implicants are taken into
consideration and a minimum cover is obtained from the remaining prime implicants.

Example: (Nov-06,07,10,May- 10,08)

Simplify the boolean function F(A,B,C,D)= ∑m (1,3,6,7,8,9,10,12,14,15) + ∑d (11,13) using

Quine McClusky method. (Apr 2017)

Step:1

B.ARUNKUMAR, Asst. Prof.,/ECE Page 30

Step:2

B.ARUNKUMAR, Asst. Prof.,/ECE Page 31

Step:3

Step:4

*************************************************

Logic gates

Explain about different types of logic gates.(OR) What are Universal gates? Construct any four
basic gates using only NOR gates and using only NAND gates. (May 2011)[NOV – 2019]

 A logic gate is an idealized or physical device implementing a Boolean function; that is, it performs
a logical operation on one or more logical inputs, and produces a single logical output.

Positive and Negative Logic

 The binary variables two states, i.e. the logic ‘0’ state or the logic ‘1’ state. These logic states in
digital systems such as computers.
 These are represented by two different voltage levels or two different current levels.
 If the more positive of the two voltage or current levels represents a logic ‘1’ and the less posit ive
of the two levels represents a logic ‘0’, then the logic system is referred to as a positive logic system.
 If the more positive of the two voltage or current levels represents a logic ‘0’ and the less positive of
the two levels represents a logic ‘1’, then the logic system is referred to as a negative logic system.

B.ARUNKUMAR, Asst. Prof.,/ECE Page 32

Truth Table
A truth table lists all possible combinations of input binary variables and the corresponding
outputs ofa logic system.

Universal Gates
 The OR, AND and NOT gates are the three basic logic gates as they together can be used to
construct the logic circuit for any given Boolean expression.
 The NOR and NAND gates have the property that they individually can be used to hardware-
implement a logic circuit corresponding to any given Boolean expression.
 That is, it is possible to use either only NAND gates or only NOR gates to implement any
Boolean expression. This is so because a combination of NAND gates or a combination of NOR
gates can be used to perform functions of any of the basic logic gates. It is for this reason that
NAND and NOR gates are universal gates.

B.ARUNKUMAR, Asst. Prof.,/ECE Page 33

 NAND gatesandNOR gatesarecalleduniversalgates or universalbuildingblocks, as any
type of gates or logic functions can be implemented by these gates. Figures
Symbolshowshow variouslogic functionscan be realizedby NAND gatesandFigures
Symbolshow therealizationofvariouslogic gatesby NOR gates.

NOT function:F =A′AND function: F =AB

 Implementation of basic gates using NAND gate:

(convert AND gate to NAND gate)

 Implementation of basic gates using NOR gate:

(convert OR gate to NOR gate)

NAND–NOR implementations:

Implementation of basic gates using NAND gate:

Inverter (NOT gate):

AND gate:

B.ARUNKUMAR, Asst. Prof.,/ECE Page 34

 OR gate:

Implementation of basic gates using NOR gate:

Inverter (NOT gate):

AND gate:

OR gate:

NAND–NOR implementations:

 Digital circuits are frequently constructed with NAND or NOR gates rather than with AND and
OR gates.
 NAND and NOR gates are easier to fabricate with electronic components and are the basic gates
used in all IC digital logic families.
 Because of the prominence of NAND and NOR gates in the design of digital c ircuits, rules and
procedures have been developed for the conversion from Boolean functions given in terms of
AND, OR, and NOT into equivalent NAND and NOR logic diagrams.

Only NAND/NOR gate circuit:

 A convenient way to implement a Boolean function with NAND/NOR gates is to obtain the
simplified Boolean function in terms of Boolean operators and then convert the function to
NAND/NOR logic.
 The conversion of an algebraic expression from AND, OR, and complement to NAND/NOR can
be done by simple circuit manipulation techniques that change AND–OR diagrams to
NAND/NOR diagrams.

B.ARUNKUMAR, Asst. Prof.,/ECE Page 35

NAND Implementation Procedure:
 Draw the AOI logic of given Boolean expression.
 Add bubble on input of OR gate & output of AND gate.
 Add an Inverter on each line that received bubbles.
 Eliminate double inversions
 Replace all by NAND gates
Example:
1. Implement F = AB + CD using only NAND gate.

2. Implement the following Boolean function with NAND gates:F (x, y, z) = (1, 2, 3, 4, 5, 7) (Apr
2018)

B.ARUNKUMAR, Asst. Prof.,/ECE Page 36

 3. Implement the function F = (AB’ + A’B)(C + D’) using only NAND gate.

B.ARUNKUMAR, Asst. Prof.,/ECE Page 37

B.ARUNKUMAR, Asst. Prof.,/ECE Page 38
B.ARUNKUMAR, Asst. Prof.,/ECE Page 39
NOR Implementation Procedure:
B.ARUNKUMAR, Asst. Prof.,/ECE Page 40
  Draw the AOI logic of given Boolean expression.
 Add bubble on input of AND gate & output of OR gate.
 Add an Inverter on each line that received bubbles.
 Eliminate double inversions
 Replace all by NOR gates
Example:
1. Implement F = (A + B)(C + D)E using only NOR gate. (Apr 2018)

2. Implement F = (AB’ + A’B)(C + D’) using only NOR gate.

B.ARUNKUMAR, Asst. Prof.,/ECE Page 41

B.ARUNKUMAR, Asst. Prof.,/ECE Page 42
B.ARUNKUMAR, Asst. Prof.,/ECE Page 43
B.ARUNKUMAR, Asst. Prof.,/ECE Page 44
 UNIT II
COMBINATIONAL LOGIC
Combinational Circuits – Analysis and Design Procedures - Binary Adder- Subtractor -Decimal Adder -
Binary Multiplier - Magnitude Comparator - Decoders – Encoders – Multiplexers - Introduction to HDL –
HDL Models of Combinational circuits.

COMBINATIONAL CIRCUITS
 A combinational circuit consists of logic gates whose outputs at any time are determined from only the
present combination of inputs.
 A combinational circuit performs an operation that can be specified logically by a set of Boolean
functions.

Sequential circuits:
 Sequential circuits employ storage elements in addition to logic gates. Their outputs are a function of
the inputs and the state of the storage elements.
 Because the state of the storage elements is a function of previous inputs, the outputs of a sequential
circuit depend not only on present values of inputs, but also on past inputs, and the circuit behavior must
be specified by a time sequence of inputs and internal states.

ANALYSIS PROCEDURE

Explain the analysis procedure. Analyze the combinational circuit the following logic diagram.
(May 2015)

 The analysis of a combinational c ircuit requires that we determine the function that
the c ircuit implements.
 The analysis can be performed manua lly by f inding the Boolean functions or t ruth
table or by using a computer s imulation program.
 The f irs t step in the analys is is to make that the g iven c ircuit is combinational or
sequential.
 Once the logic d iagram is verified to be combinational, one can proceed to obtain the
output Boolean functions or the t ruth table.
 To obtain the output Boolean functions from a logic diagram,
 Label all gate outputs that are a function of input variables with arbitrary symbols or names.
Determine the Boolean functions for each gate output.
 Label the gates that are a function of input variables and previously labeled gates with other
arbitrary symbols or names. Find the Boolean functions for these gates.
 Repeat the process in step 2 until the outputs of the circuit are obtained.
 By repeated substitution of previously defined functions, obtain the output Boolean functions in
terms of input variables.

Page 1
 Logic diagram for analysis example

The Boolean functions for the above outputs are,

 Proceed to obtain the truth table for the outputs of those gates which are a function of previously
defined values until the columns for all outputs are determined.

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 DESIGNPROCEDURE
Explain the procedure involved in designing combinational circuits.
 The design of combinational circuits starts from the specification of the design objective and
culminates in a logic circuit diagram or a set of Boolean functions from which the logic diagram can be
obtained.
 The procedure involved involves the following steps,
 From the specifications of the circuit, determine the required number of inputs and outputs and assign
a symbol to each.
 Derive the truth table that defines the required relationship between inputs and outputs.
 Obtain the simplified Boolean functions for each output as a function of the input variables.
 Draw the logic diagram and verify the correctness of the design.

**************************************************

CIRCUITS FOR ARITHMETIC OPERATIONS

Half adder:
Construct a half adder with necessary diagrams. (Nov-06,May- 07)

 A half-adder is an arithmetic circuit block that can be used to add two bits and produce two outputs
SUM and CARRY.
 The Boolean expressions for the SUM and CARRY outputs are given by the equations

Truth Table:

Logic Diagram: Half adder using NAND gate:

*************************

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Page 4
 Full adder:
Design a full adder using NAND and NOR gates respectively. (Nov -10)

 A Full-adder is an arithmetic circuit block that can be used to add three bits and produce two outputs
SUM and CARRY.
 The Boolean expressions for the SUM and CARRY outputs are given by the equations

Truth table:

Karnaugh map:

K-Map for Sum K-Map for Carry

 The simplified Boolean expressions of the outputs are
S = X′A′B + X′AB′ + XA′B′ + XAB
C = AB + BX + AX

Logic diagram:

Page 5
 The Boolean expressions of S and C are modified as follows

Full adder using Two half adder:

 Logic diagram according to the modified expression is shown Figure.

****************************

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 Half subtractor:
Design a half subtractor circuit. (Nov-2009)

 A half-subtractor is a combinational circuit that can be used to subtract one binary digit from anotherto
produce a DIFFERENCE output and a BORROW output.
 The BORROW output here specifies whether a ‘1 ’ has been borrowed to perform the subtraction. The
Boolean expression for difference and borrow is:

Logic diagram:

*************************************

Full subtractor:

Design a full subtractor. (Nov-2009,07)

 A full subtractor performs subtraction operation on two bits, a minuend and a subtrahend, and also takes
into consideration whether a ‘1’ has already been borrowed by the previous adjacent lower minuend bit
or not.
 As a result, there are three bits to be handled at the input of a full subtractor, namely the two bits to be
subtracted and a borrow bit designated as Bin .
 There are two outputs, namely the DIFFERENCE output D and the BORROW output Bo. The
BORROW output bit tells whether the minuend bit needs to borrow a ‘1’ from the next possible higher
minuend bit. The Boolean expression for difference and barrow is:

Page 7
 K-Map:

Full subtractor using two half subtractor:

*************************************

Page 8
 Parallel Binary Adder: (Ripple Carry Adder):
Explain about four bit adder. (or) Design of 4 bit binary adder – subtractor circuit. (Apr – 2019)
 A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
constructed with full adders connected in cascade, with the output carry from each full adder connected
to the input carry of the next full adder in the chain.
 Addition of n-bit numbers requires a chain of n- full adders or a chain of one-half adder and n-1 full
adders. In the former case, the input carry to the least significant position is fixed at 0.
 Figure shows the interconnection of four full-adder (FA) circuits to provide a four-bit binary ripple carry
adder.
 The carries are connected in a chain through the full adders. The input carry to the adder is C0, and it
ripples through the full adders to the output carry C4. The S outputs generate the required sum bits.
Example: Consider the two binary numbers A = 1011and B = 0011. Their sum S = 1110 is formed with
the four-bit adder as follows:

 The carry output of lower order stage is connected to the carry input of the next higher order stage.
Hence this type of adder is called ripple carry adder.
 In a 4-bit binary adder, where each full adder has a propagation delay of tp ns, the output in the fourth
stage will be generated only after 4tp ns.
 The magnitude of such delay is prohibitive for high speed computers.
 One method of speeding up this process is look-ahead carry addition which eliminates ripple carry
delay.

**********************************
Complement of a number:
1’s comple ment:
The 1’s complement of a binary number is formed bychanging 1 to 0 and 0 to 1.
Example:
1. The 1’s complement of 1011000 is 0100111.
2. The 1’s complement of 0101101 is 1010010.

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 2’s comple ment:
The 2’s complement of a binary number is formed by adding 1 with 1’s complement of a binary
number.
Example:
1. The 2’s complement of 1101100 is 0010100
2. The 2’s complement of 0110111 is 1001001

Subtraction using 2’s complement addition:

 The subtraction of unsigned binary number can be done by means of complements.
 Subtraction of A-B can be done by taking 2’s complement of B and adding it to A.
 Check the resulting number. If carry present, the number is positive and remove the carry.
 If no carry present, the resulting number is negative, take the 2’s complement of result and put
negative sign.
Example:
Given the two binary numbers X = 1010100 and Y = 1000011, perform the subtraction
(a) X - Y and (b) Y - X by using 2’s complements.
Solution:
(a) X = 1010100
2’s complement of Y = + 0111101
Sum= 10010001
Discard end carry. Answer: X - Y = 0010001
(b) Y = 1000011
2’s complement of X= + 0101100
Sum= 1101111
There is no end carry. Therefore, the answer is Y - X = -(2’s complement of 1101111) =-0010001.

****************************

Parallel Binary Subtractor:

 The subtraction of unsigned binary numbers can be done most conveniently by meansof compleme nts.
The subtraction A - B canbe done by taking the 2’s complement of B and adding it to A . The 2’s
complement canbe obtained by taking the 1’s complement and adding 1 to the least significant pair

Page 10
 ofbits. The 1’s complement can be implemented with inverters, and a 1 can be added tothe sum through
the input carry.
 The circuit for subtracting A - B consists of an adder with inverters placed betweeneach data input B and
the corresponding input of the full adder. The input carry C in mustbe equal to 1 when subtraction is
performed. The operation thus performed becomes A,plus the 1’s complement of B , plus 1. This is equal
to Aplus the 2’s complement of B.
 For unsigned numbers, that gives A-B if A>=B or the 2’s complement of B - Aif A <B. For signed
numbers, the result is A - B, provided that there is no overflow.

****************************

Fast adder (or) Carry Look Ahead adder:

Design a carry look ahead adder circuit. (Nov-2010)
 The carry look ahead adder is based on the principle of looking at the lower order bits of the augend
and addend to see if a higher order carry is to be generated.
 It uses two functions carry generate and carry propagate.

Consider the circuit of the full adder shown in Fig. If we define two new binaryvariables

the output sum and carry can respectively be expressed as

Gi is called a carry generate, and it produces a carry of 1 when both Ai and Bi are 1,regardless of
the input carry Ci. Pi is called a carry propagate, because it determines whether a carry into stage i will
propagate into stage i + 1 (i.e., whether an assertion of Ci will propagate to an assertion of Ci+1 ).

We now write the Boolean functions for the carry outputs of each stage and substitutethe value
of each Ci from the previous equations:

Page 11
 The construction of a four-bit adder with a carry lookahead scheme is shown in Fig.
 Each sum output requires two exclusive-OR gates.
 The output of the first exclusive-OR gate generates the Pi variable, and the AND gate generates the Gi
variable.
 The carries are propagated through the carry look ahead generator and applied as inputs to the second
exclusive-OR gate.
 All output carries are generated after a delay through two levels of gates.
 Thus, outputs S1 through S3 have equal propagation delay times. The two- level circuit for the output
carry C4 is not shown. This circuit can easily be derived by the equation-substitution method.

Page 12
 ******************************

4 bit-Parallel adder/subtractor:
Explain about binary parallel / adder subtractor. [NOV – 2019]
 The addition and subtraction operations can be combined into one circuit with one common binary adder
by including an exclusive-OR gate with each full adder. A four-bit adder–subtractor circuit is shown in
Fig.
 The mode input M controls the operation. When M = 0, the circuit is an adder, and when M = 1, the
circuit becomes a subtractor.

Page 13
 It performs the operations of both addition and subtraction.
 It has two 4bit inputs A3A2A1A0 and B3B2B1B0.
 The mode input M controls the operation when M=0 the circuit is an adder and when M=1 the circuits
become subtractor.
 Each exclusive-OR gate receives input M and one of the inputs of B .
 When M = 0, we have B xor0 = B. The full adders receive the value of B , the input carry is 0, and the
circuit performs A plus B . This results in sum S3S2S1S0and carry C4.
 When M = 1, we have B xor 1 = B’ and C0 = 1. The B inputs are all complemented and a 1 is added
through the input carry thus producing 2’s complement of B.
 Now the data A3A2A1A0will be added with 2’s complement of B3B2B1B0to produce the sum i.e., A-B if
A≥B or the 2’s complement of B-A if A<B.

*************************

Comparators
Design a 2 bit magnitude comparator. (May 2006)

It is a combinational circuit that compares two numbers and determines their relative magnitude. The
output of comparator is usually 3 binary variables indicating:
A<B, A=B, A>B

1-bitcomparator: Let’s begin with 1bit comparator and from the name we can easily make out that this
circuit would be used to compare 1bit binary numbers.

Page 14
 A B A>B A=B A<B
0 0 0 1 0
1 0 1 0 0
0 1 0 0 1
1 1 0 1 0

For a 2-bit comparator we have four inputs A1 A0 and B1 B0 and three output E (is 1 if two numbers are
equal) G (is 1 when A>B) and L (is 1 when A<B) If we use truth table and K-map the result is

Design of 2 – bit Magnitude Comparator.

The truth table of 2-bit comparator is given in table below

Page 15
Truth table:

K-Map:

Page 16
Logic Diagram:

********************

4 bit magnitude comparator:

Design a 4 bit magnitude comparators. (Apr – 2019)

Input

Page 17
Function Equation

*************************

Page 18
 BCD Adder:
Design to perform BCD addition.(or) What is BCD adder? Design an adder to perform arithmetic
addition of two decimal bits in BCD. (May -08)(Apr 2017,2018)[Nov – 2019]
 Consider the arithmetic addition of two decimal digits in BCD, together with an input carry from a
previous stage. Since each input digit does not exceed 9, the output sum cannot be greater than 9 + 9 + 1
= 19, the 1 in the sum being an input carry.
 Suppose we apply two BCD digits to a four-bit binary adder. The adder will form the sum in binary and
produce a result that ranges from 0 through 19. These binary numbers are listed in Table and are labeled
by symbols K, Z8, Z4, Z2, and Z1. K is the carry, and the subscripts under the letter Z represent the
weights 8, 4, 2, and 1 that can be assigned to the four bits in the BCD code.

Page 19
 A BCD adder that adds two BCD digits and produces a sum digit in BCD is shown in Fig. The two
decimal digits, together with the input carry, are first added in the top four-bit adder to produce the
binary sum.
 When the output carry is equal to 0, nothing is added to the binary sum. When it is equal to 1, binary
0110 is added to the binary sum through the bottom four-bit adder.
 The condition for a correction and an output carry can be expressed by the Boolean function
C = K + Z8Z4 + Z8Z2
 The output carry generated from the bottom adder can be ignored, since it supplies information already
available at the output carry terminal.
 A decimal parallel adder that adds n decimal digits needs n BCD adder stages. The output carry from
one stage must be connected to the input carry of the next higher order stage.

******************************
Binary Multiplier:
Explain about binary Multiplier.
 Multiplication of binary numbers is performed in the same way as multiplication of decimal numbers.
The multiplicand is multiplied by each bit of the multiplier, starting from the least significant bit. Each
such multiplication forms a partial product.
 Successive partial products are shifted one position to the left. The final product is obtained from the
sum of the partial products.

 A combinational circuit binary multiplier with more bits can be constructed in a similar fashion.
 A bit of the multiplier is ANDed with each bit of the multiplicand in as many levels as there are bits in
the multiplier.
 The binary output in each level of AND gates is added with the partial product of the previous level to
form a new partial product. The last level produces the product.

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*************************************

Page 21
 CODE CONVERSION
Design a binary to gray converter. (Nov-2009)(Nov
2017) Binary to Grayconverter

Gray code is unit distance code.

Input code: Binary [B3 B2 B1 B0]
output code: Gray [G3 G2 G1 G0]

Truth Table

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

K-MAP FORG3: K-MAP FORG2:

G3=B3 G2=B3’B2+B3B2’=B3 B2

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K-MAP FORG1: K-MAP FORG0:

G1=B1’B2+B1B2’=B1 B2 G0=B1’ B0+B1B0’=B1 B0

Logic diagram:

Gray to Binary converter:

Design a gray to binary converter.(OR) Design a combinational circuit that converts a four bit gray
code to a four bit binary number using exclusive – OR gates. (Nov-2009) [NOV – 2019]
Gray code is unit distance code.
Input code: Gray [G3 G2 G1 G0]
output code: Binary [B3 B2 B1 B0]

Page 23
Truth Table:

K-Map:

Page 24
 Logic Diagram:

BCD to Excess -3 converter:

Design a combinational circuits to convert binary coded decimal number into an excess-3 code.

 Excess-3 code is modified form of BCD code. (Nov-06,09,10, May-08,10)

 Excess -3 code is derived from BCD code by adding 3to each coded number.

Page 25
 Truth table:

K-Map:

Page 26
Logic Diagram

Excess -3 to BCD converter:

Design a combinational circuit to convert Excess-3 to BCD code. (May 2007)

Truth table:

Page 27
Page 28
Page 29
Design Binary to BCD converter.
Truth table:

K-map:

Page 30
Logic diagram:

******************************

Page 31
 DECODERS AND ENCODERS
Decoder:
Explain about decoders with necessary diagrams. (Apr 2018)(Nov 2018)

 A decoder is a combinational circuit that converts binary information from n input lines to a maximum
of 2n unique output lines. If the n -bit coded information has unused combinations, the decoder may
have fewer than 2n outputs.
 The purpose of a decoder is to generate the 2n (or fewer) minterms of n input variables, shown below for
two input variables.

2 to 4 decoder:

3 to 8 Decoder:
Design 3 to 8 line decoder with necessary diagram. May -10)
Truth table:

Page 32
 Logic diagram:

Design for 3 to 8 decoder with 2 to 4 decoder:

 Not that the two to four decoder design shown earlier, with its enable inputs can be used to build a
three to eight decoder as follows.

Page 33
 Implementation of Boolean function using decoder:

 Since the three to eight decoder provides all the minterms of three variables, the realisation of a
function in terms of the sum of products can be achieved using a decoder and OR gates as follows.

Example: Implement full adder using decoder.

Sum is given by ∑m(1, 2, 4, 7) while Carry is given by ∑m(3, 5, 6, 7) as given by the minterms
each of the OR gates are connected to.

Design for 4 to 16 decoder using 3 to 8 decoder: Design 5 to 32 decoder using 3 to 8 and 2 to 4 decoder:

**********************************

BCD to seven segment decoder

Design a BCD to seven segment code converter. (May-06,10, Nov- 09)

Page 34
Truth table:

K-Map:

Page 35
 Logic Diagram:

 The specification above requires that the output be zeroes (none of the segments are lighted up) when
the input is not a BCD digit.
 In practical implementations, this may defer to allow representation of hexadecimal digits using the
seven segments.
**************************

Page 36
 Encoder:
Explain about encoders. (Nov 2018)
 An encoder is a digital circuit that performs the inverse operation of a decoder. An encoder has 2 n (or
fewer) input lines and n output lines. The output lines, as an aggregate, generate the binary code
corresponding to the input value.

Octal to Binary Encoder:

 The encoder can be implemented with OR gates whose inputs are determined directly from the truth
table. Output z is equal to 1 when the input octal digit is 1, 3, 5, or 7.
 Output y is 1 for octal digits 2, 3, 6, or 7, and output x is 1 for digits 4, 5, 6, or 7. These conditions can
be expressed by the following Boolean output functions:

The encoder can be implemented with three OR gates.

Truth table:

 Another ambiguity in the octal-to-binary encoder is that an output with all 0’s is generated when all the
inputs are 0; but this output is the same as when D0 is equal to 1. The discrepancy can be resolved by
providing one more output to indicate whether at least one input is equal to 1.

Page 37
Logic Diagram:

************************

Priority Encoder:
Design a priority encoder with logic diagram.(or) Explain the logic diagram of a 4 – input priority
encoder. (Apr – 2019)
A priority encoder is an encoder circuit that includes the priority function. The operationof the
priority encoder is such that if two or more inputs are equal to 1 at the same time,the input having the
highest priority will take precedence.
Truth table:

Modified Truth table:

Page 38
K-Map:

Logic Equations:

Logic diagram:

*******************************************

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 MULTIPLEXERS AND DEMULTIPLEXERS

Multiplexer: (MUX)
Design a 2:1 and 4:1 multiplexer.

 A multiplexer is a combinational circuit that selects binary information from one of many input lines
and directs it to a single output line. The selection of a particular input line is controlled by a set of
selection lines.
 Normally, there are 2n input lines and n selection lines whose bit combinations determine which input is
selected.

2 to 1 MUX:

A 2 to 1 line multiplexer is shown in figure below, each 2 input lines A to B is applied to one input of an
AND gate. Selection lines S are decoded to select a particular AND gate. The truth table for the 2:1 mux
is given in the table below.

 To derive the gate level implementation of 2:1 mux we need to have truth table as shown in figure. And
once we have the truth table, we can draw the K- map as shown in figure for all the cases when Y is
equal to '1'.
Truth table:

Logic Diagram:

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 4 to 1 MUX:
 A 4 to 1 line multiplexer is shown in figure below, each of 4 input lines I0 to I3 is applied to one input
of an AND gate.
 Selection lines S0 and S1 are decoded to select a particular AND gate.
 The truth table for the 4:1 mux is given in the table below.

Logic Diagram:

Truth Table:
SELECT OUTPUT
INPUT
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3

Problems :
Example: Implement the Boolean expression using MUX
F(A,B,C,D) = ∑m(0,1,5,6,8,10,12,15) (Apr 2017, Nov 2017)

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Example: Implement the boolean function using Multiplexer. [NOV – 2019]

F (x, y, z) = Σm (1, 2, 6, 7)

Solution:
Implementation table:

Multiplexer Implementation:

Example: 32:1 Multiplexer using 8:1 Mux (Nov 2018) (Apr – 2019)

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 DEMULTIPLEXERS:
Explain about demultiplexers.

 The de- multiplexer performs the inverse function of a multiplexer, that is it receives information on
one line and transmits its onto one of 2n possible output lines.
 The selection is by n input select lines. Example: 1-to-4 De- multiplexer

Logic Diagram: Truth Table:

INPUT OUTPUT

E D S0 S1 Y0 Y1 Y2 Y3

1 1 0 0 1 0 0 0

1 1 0 1 0 1 0 0

1 1 1 0 0 0 1 0

1 1 1 1 0 0 0 1

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 Example:
1. Implement full adder using De-multiplexer.

2. Implement the following functions using de-multiplexer.

f1 (A,B,C) = ∑m(1,5,7), f2 (A,B,C) = ∑m(3,6,7)
Solution:

***************************

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Parity Checker / Generator:

 A parity bit is an extra bit included with a binary message to make the number of 1’s either odd or
even. The message, including the parity bit, is transmitted and then checked at the receiving end for
errors. An error is detected if the checked parity does not correspond with the one transmitted.
 The circuit that generates the parity bit in the transmitter is called a parity generator. The circuit that
checks the parity in the receiver is called a parity checker.
 In even parity system, the parity bit is ‘0’ if there are even number of 1s in the data and the parity bit
is ‘1’ if there are odd number of 1s in the data.
 In odd parity system, the parity bit is ‘1’ if there are even number of 1s in the data and the parity bit
is ‘0’ if there are odd number of 1s in the data.

3- bit Even Parity

generator: Truth Table:

Logic Diagram:

Page 45
 4- bit Even parity checker:
Truth Table:

Logic Diagram:

INTRODUCTION TO HDL

 In electronics, a hardware description language or HDL is any language from a class of computer
languages and/or programming languages for formal description of digital logic and electronic circuits.
 HDLs are used to write executable specifications of some piece of hardware.
 A simulation program, designed to implement the underlying semantics of the language statements,
coupled with simulating the progress of time, provides the hardware designer with the ability to model a
piece of hardware before it is created physically.
 Logic synthesis is the process of deriving a list of components and their interconnection (called net list)
from the model of a digital system.
 Logic Simulation is the representation of the structure and behavior of a digital logic synthesis through
the use of a computer.
 The standard HDLs that supported by IEEE.
 VHDL (very High Speed Integrated Circuit HDL)
 Verilog HDL

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 HDL MODELS OF COMBINATIONAL CIRCUITS

The Verilog HDL model of a combinational circuit can be described in any one of the following
modeling styles,

 Gate level modeling- using instantiations of predefined and user defined primitive gates.
 Dataflow modeling using continuous assignment with the keyword assign.
 Behavioral modeling using procedural assignment statements with the keyword always.

Gate level modeling

In this type, a circuit is specified by its logic gates and their interconnections. Gate level modeling
provides a textual description of a schematic diagram. The verilog HDL includes 12basic gates as
predefined primitives. They are and, nand, or, nor, xor, xnor, not &buf.

Data flow modeling

Data flow modeling of combinational logic uses a number of operators that act on operands to produce
desired results. Verilog HDL provides about 30 different operators. Data flow modeling uses continuous
assignments and the keyword assign. A continuous assignment is a statement that assigns a value to a
net. The data type family net is used to represent a physical connection between circuit elements.

HDL for2-to-4 line decoder

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 Behavioral modeling

 Behavioral modeling represents digital circuits at a functional and algorithmic level. It is used mostly to
describe sequential circuits, but can also be used to describe combinational circuits.
 Behavioral descriptions use the keyword always, followed by an optional event control expression and a
list of procedural assignment statements.

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 UNIT III
SYN CHRONOUS SEQUENTIAL LOGIC

Sequential Circuits - Storage Elements: Latches , Flip-Flops - Analysis of Clocked Sequential Circuits - State
Reduction and Assignment - Design Procedure - Registers and Counters - HDL Models of Sequential
Circuits

SEQUENTIAL CIRCUITS
Sequential circuits:
 Sequential circuits employ storage elements in addition to logic gates. Their outputs are a function of
the inputs and the state of the storage elements.
 Because the state of the storage elements is a function of previous inputs, the outputs of a sequential
circuit depend not only on present values of inputs, but also on past inputs, and the circuit behavior
must be specified by a time sequence of inputs and internal states.

Types of sequential circuits:

There are two main types of sequential circuits, and their classification is a function ofthe timing
of their signals.
1. Synchronous sequential circuit:
It is a system whose behaviorcan be defined from the knowledge of its signals at discrete
instants of time.
2. Asynchronous sequential circuits:
The behaviorof an asynchronous sequential circuit depends upon the input signals at any
instant of timeand the order in which the inputs change. The storage elements commonly used
in asynchronoussequential circuits are time-delay devices.

LATCHES AND FLIP FLOPS

Flip-Flop:
 The storage elements (memory) used in clocked sequential circuits are called flipflops. A flip-flop is
a binary storage device capable of storing one bit of information. In a stable state, the output of a flip-
flop is either 0 or 1.
 A sequential circuit may use many flip- flops to store as many bits as necessary. The block diagram of
a synchronous clocked sequential circuit is shown in Fig.

Page 1
 A storage element in a digital circuit can maintain a binary state indefinitely (as long as power is
delivered to the circuit), until directed by an input signal to switch states.
 The major differences among various types of storage elements are in the number of inputs they
possess and in the manner in which the inputs affect the binary state.
Latch:
 The storage elements that operate with signal levels (rather than signal transitions) are referred to as
latches; those controlled by a clock transition are flip-flops.Latches are said to be level sensitive
devices; flip-flops are edge-sensitive devices.

SR Latch: Using NOR gate

Realize SR Latch using NOR and NAND gates and explain its operation.
 The SR latch is a circuit with two cross-coupled NOR gates or two cross-coupled NAND gates, and
two inputs labeled S for set and R for reset.
 The SR latch constructed with two cross-coupled NOR gates is shown in Fig.

 The latch has two useful states. When output Q = 1 and Q‟= 0, the latch is said to be in the set state .
When Q = 0 and Q‟ = 1, it is in the reset state . Outputs Q and Q‟ are normally the complement of
each other.
 However, when both inputs are equal to 1 at the same time, a condition in which both outputs are
equal to 0 (rather than be mutually complementary) occurs.
 If both inputs are then switched to 0 simultaneously, the device will enter an unpredictable or
undefined state or a metastable state. Consequently, in practical applications, setting both inputs to 1
is forbidden.
Page 2
 FLIP FLOPS
Triggering of Flip Flops:
Explain about triggering of flip flops in detail.
 The state of a latch or flip-flop is switched by a change in the control input. This momentary change
is called a trigger, and the transition it causes is said to trigger the flip-flop.

Level Triggering:
 SR, D, JK and T latches are having enable input.
 Latches are controlled by enable signal, and they are level triggered, either positive level triggered or
negative level triggered as shown in figure (a).
 The output is free to change according to the input values, when active level is maintained at the
enable input.

Edge Triggering:
 A clock pulse goes through two transitions: from 0 to 1 and the return from 1 to 0.
 As shown in above Fig (b) and (c)., the positive transition is defined as the positive edge and the
negative transition as the negative edge.

*******************************
Explain the operation of flipflops.(Nov 2017)

FLIP FLOP CONVERSIONS

The purpose is to convert a given type A FF to a desired type B FF using some conversion logic.

Page 3
The key here is to use the excitation table, which shows the necessary triggering signal (S,R, J,K, D

and T) for a desired flipflop state transition :

Excitation table for all flip flops:

1. SR Flip Flop to JK Flip Flop

The truth tables for the flip flop conversion are given below. The present state is represented by
Qp and Qp+1 is the next state to be obtained when the J and K inputs are applied.
For two inputs J and K, there will be eight possible combinations. For each combination of J, K and Qp,
the corresponding Qp+1 states are found. Qp+1 simply suggests the future values to be obtained by the
JK flip flop after the value of Qp.

The table is then completed by writing the values of S and R required to get each Qp+1 from the
corresponding Qp. That is, the values of S and R that are required to change the state of the flip flop from
Qp to Qp+1 are written.

Page 4
2. JK Flip Flop to SR Flip Flop
This will be the reverse process of the above explained conversion. S and R will be the external
inputs to J and K. As shown in the logic diagram below, J and K will be the outputs of the combinational
circuit. Thus, the values of J and K have to be obtained in terms of S, R a nd Qp. The logic diagram is
shown below.

A conversion table is to be written using S, R, Qp, Qp+1, J and K. For two inputs, S and R, eight
combinations are made. For each combination, the corresponding Qp+1 outputs are found. The outputs
for the combinations of S=1 and R=1 are not permitted for an SR flip flop. Thus the outputs are
considered invalid and the J and K values are taken as “don‟t cares”.

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3. SR Flip Flop to D Flip Flop
As shown in the figure, S and R are the actual inputs of the flip flop and D is the external input of
the flip flop. The four combinations, the logic diagram, conversion table, and the K-map for S and R in
terms of D and Qp are shown below.

4. D Flip Flop to SR Flip Flop

D is the actual input of the flip flop and S and R are the external inputs. Eight possible
combinations are achieved from the external inputs S, R and Qp. But, since the combination of S=1 and
R=1 are invalid, the values of Qp+1 and D are considered as “don‟t cares”. The logic diagram showing
the conversion from D to SR, and the K- map for D in terms of S, R and Qp are shown below.

Page 6
5. JK Flip Flop to T Flip Flop
J and K are the actual inputs of the flip flop and T is taken as the external input for conversion.
Four combinations are produced with T and Qp. J and K are expressed in terms of T and Qp. The
conversion table, K- maps, and the logic diagram are given below.

6. JK Flip Flop to D Flip Flop

D is the external input and J and K are the actual inputs of the flip flop. D and Qp make four
combinations. J and K are expressed in terms of D and Qp. The four combination conversion table, the
K-maps for J and K in terms of D and Qp, and the logic diagram showing the conversion from JK to
D are given below.

7. D Flip Flop to JK Flip Flop

AUQ: How will you convert a D flip-flop into JK flip-flop? (AUQ: Dec 2009,11,Apr 2017)
In this conversion, D is the actual input to the flip flop and J and K are the external inputs. J, K
and Qp make eight possible combinations, as shown in the conversion table below. D is expressed in
terms of J, K and Qp.The conversion table, the K- map for D in terms of J, K and Qp and the logic
diagram showing the conversion from D to JK are given in the figure below.

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 *******************************************
MEALY AND MOORE MODELS

Write short notes on Mealy and Moore models in sequential circuits.

 In synchronous sequential circuit the outputs depend upon the order in which its input variables
change and can be affected at discrete instances of time.
General Models:
 There are two models in sequential circuits. They are:
1. Mealy model
2. Moore model

Moore machine:
 In the Moore model, the outputs are a function of present state only.

Mealy machine:
 In the Mealy model, the outputs are a function of present state and external inputs.

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Difference between Moore model and Mealy model.

Example:
A sequential circuit with two ‘D’ Flip-Flops A and B, one input (x) and one output (y).
The Flip-Flop input functions are:
DA= Ax+ Bx
DB= A’xand
the circuit output function is, Y= (A+ B) x’.
(a) Draw the logic diagram of the circuit, (b) Tabulate the state table, (c) Draw the state diagram.

Solution:

Page 9
State table:

State diagram:

***************************************

*****************************************
COUNTERS
Counter:
 A counter is a register (group of Flip-Flop) capable of counting the number of clock pulse
arriving at its clock input.
 A counter that follows the binary number sequence is called a binary counter.
 Counter are classified into two types,
1. Asynchronous (Ripple) counters.
2. Synchronous counters.

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  In ripple counter, a flip- flop output transition serves as clock to next flip-flop.
o With an asynchronous circuit, all the bits in the count do not all change at the same time.
 In a synchronous counter, all flip-flops receive common clock.
o With a synchronous circuit, all the bits in the count change synchronously with the
assertion of the clock
 A counter may count up or count down or count up and down depending on the input control.

Uses of Counters:
The most typical uses of counters are
 To count the number of times that a certain event takes place; the occurrence of event to be
counted is represented by the input signal to the counter
 To control a fixed sequence of actions in a digital system
 To generate timing signals
 To generate clocks of different frequencies

Modulo 16 ripple /Asynchronous Up Counter

Explain the operation of a 4-bit binary ripple counter.
 The output of up-counter is incremented by one for each clock transition.
 A 4-bit asynchronous up-counter consists of 4JK Flip-Flops.
 The external clock signal is connected to the clock input of the first FlipFlop.
 The clock inputs of the remaining Flip-Flops are triggered by the Q output of the previous stage.
 We know that in JK Flip-Flop, if J=1 , K=1 and clock is triggered the past output will be
complemented.
 Initially, the register is cleared, QDQCQBQA =0000.
 During the first clock pulse, F lip-Flop A triggers, therefore QA=1, QB=QC=QD=0.
QDQCQBQA=0001
 At the second clock pulse FLipFlop A triggers, therefore Q A changes from 1 to 0, which triggers
FlipFlop B, therefore QB=1,QA=QC=QD=0
QDQCQBQA=0010
 At the third clock pulse FlipFlop A triggers, therefore QA changes from 0 to 1, This never triggers
FlipFlop B because 0 to 1 transition gives a positive edge triggering,but here the FlipFlops are
triggered only at negative edge( 1 to 0 transition) therefore QA=QB=1, QC=QD=0.
QDQCQBQA=0011

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  At the fourth clock pulse Flip-Flop A triggers, therefore QA changes from 1 to 0, This triggers
FlipFlop B therefore QB changes from 1 to 0. The change in QB from 1 to 0 triggers C Flip-Flop,
 Therefore QC changes from 0 to 1. Therefore QA=QB=QD=0, QC=1.
QDQCQBQA=0100

Truth table:

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Timing diagram:

**********************************
Modulo 16 /4 bit Ripple Down counter/ Asynchronous Down counter
Explain about Modulo 16 /4 bit Ripple Down counter.
 The output of down-counter is decremented by one for each clock transition.
 A 4-bit asynchronous down-counter consists of 4JK Flip-Flops.
 The external clock signal is connected to the clock input of the first Flip-Flop.
 The clock inputs of the remaining Flip-Flops are triggered by the Q output of the previous stage.
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 We know that in JK Flip-Flop, if J=1 , K=1 and clock is triggered the past output will be
complemented.

 Initially, the register is cleared, QDQCQBQA =0000.

 During the first clock pulse, Flip-Flop A triggers, therefore QA changes from 0 to 1 also QA
changes from 1 to 0.This triggers Flip-Flop B, therefore QB changes from 0 to 1, also QB changes
from 1 to 0which triggers Flip-FlopC. Hence QC changes from 0 to 1 and QC changes from 1 to
0, which further triggers, Flip-Flop D.
QDQCQBQA=1111
QD QC QB QA=0000

 During the second clock pulse Flip-Flop A triggers, therefore QA changes from 1 to 0 also QA
changes from 0 to 1 which never triggers B Flip-Flop. Therefore C and D Flip-Flop are not
triggered.
QDQCQBQA =1110
 The same procedure repeats until the counter decrements upto 0000.

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Page 15
***************************

Page 16
Asynchronous Up/Down Counter:
Explain about Asynchronous Up/Down counter.
 The up-down counter has the capability of counting upwards as well as downwards. It is also
called multimode counter.
 In asynchronous up-counter, each flip-flop is triggered by the normal output Q of the preceding
flip- flop.
 In asynchronous down counter, each flip-flop is triggered by the complement output Q of the
preceding flip- flop.
 In both the counters, the first flip- flop is triggered by the clock output.

 If Up/Down =1, the 3-bit asynchronous up/down counter will perform up-counting. It will count
from 000 to 111. If Up/Down =1 gates G2 and G4 are disabled and gates G1 and G3 are enabled.
So that the circuit behaves as an up-counter circuit.
 If Up/Down =0, the 3-bit asynchronous up/down counter will perform down-counting. It will
count from 111 to 000. If Up/Down =0 gates G 2 and G4 are enabled and gates G1 and G3 are
disabled. So that the circuit behaves as an down-counter circuit.

******************************
Page 17
Page 18
4- bitSynchronous up-counter:
Explain about 4-bit Synchronous up-counter.

 In JK Flip-Flop, If J=0, K=0 and clock is triggered, the output never changes. If J=1 and K=1 and
the clock is triggered, the past outpit will be complemented.
Initially the register is cleared QDQCQBQA= 0000.
During the first clock pulse, JA= KA = 1, QA becomes 1, QB, QC, QD remains 0.
QDQCQBQA= 0001.
During second clock pulse, JA= KA = 1, QA=0.
JB= KB = 1, QB =1, QC, QD remains 0.
QDQCQBQA= 0010.
During third clock pulse, JA= KA = 1, QA=1.
JB= KB = 0, QB =1, QC, QD remains 0.
QDQCQBQA= 0011.
During fourth clock pulse, JA= KA = 1, QA=0.
JB= KB = 1, QB =0
JC= KC = 1, QC=1
QD remains 0
QDQCQBQA= 0100.
The same procedure repeats until the counter counts up to 1111.

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*******************************************

Page 20
4- bit Synchronous down-counter:
Explain about 4-Bit Synchronous down counter.

In JK Flip-Flop, If J=0, K=0 and clock is triggered, the output never changes. If J=1 and K=1 and the
clock is triggered, the past outpit will be complemented.
Initially the register is cleared QDQCQBQA= 0000
QDQCQBQA= 1111

During the first clock pulse, JA= KA = 1, QA=1

JB= KB = 1, QB =1
JC= KC = 1, QC =1
JD= KD = 1, QD =1
QDQCQBQA= 1111
QDQCQBQA= 0000

During the second clock pulse, JA= KA = 1, QA =0

JB= KB = 0, QB =1
JC= KC = 0, QC =1
JD= KD = 0, QD =1
QDQCQBQA= 1110
Q
D QCQBQA= 0001
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Page 22
During the second clock pulse, JA= KA = 1, QA =1
JB= KB = 1, QB =0
JC= KC = 0, QC =1
JD= KD = 0, QD =1
QDQCQBQA= 1101
The process repeats until the counter down-counts up to 0000.

************************************

Page 23
Modulo 8 Synchronous Up/Down Counter:
Explain about Modulo 8 Synchronous Up/Down Counter.

In synchronous up-counter the QA output is given to JB, KBand QA. QB is given to JC, KC. But in
synchronous down –counter QAoutput is given toJB, KB and QA. QB is given to JC, KC.

A control input Up/Down is used to select the mode of operation.

If Up/Down =1, the 3-bit asynchronous up/down counter will perform up-counting. It will count from
000 to 111. If Up/Down =1 gates G2 and G4 are disabled and gates G 1 and G3 are enabled. So that the
circuit behaves as an up-counter circuit.

If Up/Down =0, the 3-bit asynchronous up/down counter will perform down-counting. It will count from
111 to 000. If Up/Down =0 gates G2 and G4 are enabled and gates G1 and G3 are disabled. So that the
circuit behaves as an down-counter circuit.

*******************************************
Page 24
Page 25
 ******************************************
DESIGN OF RIPPLE COUNTERS
3-Bit Asynchronous Binary Counter/ modulo -7 ripple counter:
Design a 3-bit binary counter using T-flip flops. [NOV – 2019]
Explain about 3-Bit Asynchronous binary counter. (Nov -2009)
The following is a three-bit asynchronous binary counter and its timingdiagram for one cycle. It
works exactly the same way as a two-bitasynchronous binary counter mentioned above, except it has
eight statesdue to the third flip- flop.

Asynchronous counters are commonly referred to as ripple counters forthe following reason: The
effect of the input clock pulse is first “felt” byFFO. This effect cannot get to FF1 immediately because of
thepropagation delay through FF0. Then there is the propagation delaythrough FF1 before FF2 can be

Page 26
triggered. Thus, the effect of an inputclock pulse “ripples” through the counter, taking some time, due
topropagation delays, to reach the last flip- flop.
**********************************
ANALYSIS OF CLOCKED SEQUENTIAL CIRCUIT
Design and analyze of clocked sequential circuit with an example.
The analysis of a sequential circuit consists of obtaining a table or a diagram for the time sequence of
inputs, outputs and internal states.

Fig: Example of sequential circuit

Consider the sequential circuit is shown in figure. It consists of two D flip- flops A and B, an input x and
an output y.
A state equation specifies the next state as function of the present state and inputs.
A(n +1)= A(n )x (n )+B(n )x (n )
B(n +1)= A (n )x (n)
They can be written in simplified form
as, A(n+1) = Ax +Bx
B(n +1) = Ax

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The present state value of the output can be expressed algebraically as,

y(n) =(A+ B) x

DESIGN OF SYNCHRONOUS COUNTERS

Design and analyze of clocked sequential circuit with an example.
The procedure for designing synchronous sequential circuit is given below,
1. From the given specification, Draw the state diagram.
2. Plot the state table.
3. Reduce the number of states if possible.
4. Assign binary values to the states and plot the transition table by choosing the type of Flip-Flop.
5. Derive the Flip flop input equations and output equations by using K-map.
6. Draw the logic diagram.

State Diagram:
 State diagram is the graphical representation of the information available in a state table.
 In state diagram, a state is represented by a circle and the transitions between states are indicated by
directed lines connecting the circles.
State Table:
 A state table gives the time sequence of inputs, outputs ad flip flops states. The table consists of
four sections labeled present state, next state, input and output.
 The present state section shows the states of flip flops A and B at any given time „n‟. The
input section gives a value of x for each possible present state.
 The next state section shows the states of flip flops one clock cycle later, at time n+1.

The state table for the circuit is shown. This is derived using state equations.

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The above state table can also be expressed in different forms as follows.

The state diagram for the logic circuit in below figure.

Flip-Flop Input Equations:

The part of the circuit that generates the inputs to flip flops is described algebraically by a set of Boolean
functions called flip flop input equations.

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The flip flop input equations for the circuit is given by,
DA =Ax +Bx
DB =A x

**************************************

****************************************

Design of a Synchronous Decade Counter Using JK Flip- Flop (Apr 2018, Nov 2018)
A synchronous decade counter will count from zero to nine and repeat thesequence.
State diagram:
The state diagram of this counter is shown in Fig.

Excitation table:

K-Map:

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Page 31
Logic Diagram:

*************************************

Design of an Asynchronous Decade Counter Using JK Flip- Flop.

An asynchronous decade counter will count from zero to nine and repeat thesequence. Since the
JK inputs are fed from the output of previous flip- flop,therefore, the design will not be as complicated as
the synchronous version.
At the ninth count, the counter is reset to begin counting at zero. The NAND gateis used to reset
the counter at the ninth count. At the ninth count the outputs offlip- flop Q3 and Q1 will be high
simultaneously. This will cause the output ofNAND to go to logic “0” that would reset the flip- flip. The
logic design of thecounter is shown in Fig.

Page 32
 **************************************

Design of a Synchronous Modulus-Six Counter Using SR Flip-Flop(Nov 2017)

The modulus six counters will count 0, 2, 3, 6, 5, and 1 and repeat the sequence.This modulus six
counter requires three SR flip- flops for the design.
State diagram:

Truth table:

K-Map:

Page 33
Logic Diagram:

SHIFT REGISTERS
Explain various types of shift registers. (or) Explain the operation of a 4-bit bidirectional shift
register. (Or) What are registers? Construct a 4 bit register using D-flip flops and explain the
operations on the register.(or) With diagram explain how two binary numbers are added serially using
shift registers. (Apr – 2019)[NOV – 2019]
 A register is simply a group of Flip-Flops that can be used to store a binary number.
 There must be one Flip-Flop for each bit in the binary number.
 For instance, a register used to store an 8-bit binary number must have 8 Flip-Flops.

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  The Flip-Flops must be connected such that the binary number can be entered (shifted) into the
register and possibly shifted out.
 A group of Flip-Flops connected to provide either or both of these functions is called a shift register.
 A register capable of shifting the binary information held in each cell to its neighboring cell in
a selected direction is called a shift register.

 There are four types of shift registers namely:

1. Serial In Serial Out Shift Register,
2. Serial In Parallel Out Shift Register
3. Parallel In Serial Out Shift Register
4. Parallel In Parallel Out Shift Register

1. SerialIn Serial Out Shift Register

 The block diagram of a serial out shift register is as below.

 As seen, it accepts data serially .i.e., one bit at a time on a single input line. It produces the stored
information on its single output also in serial form.
 Data may be shifted left using shift left register or shifted right using shift right register.

Shift Right Register

The circuit diagram using D flip-fops is shown in figure

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  As shown in above figure,the clock pulse is applied to all the flip-flops simultaneously.
 The output of each flip-flop is connected to D input of the flip- flop at its right.
 Each clock pulse shifts the contents of the register one bit position to the right.
 New data is entered into stage A whereas the data presented in stage D are shifted out.
 For example, consider that all stages are reset and a steady logical 1 is applied to the serial input
line.
 When the first clock pulse is applied, flip- flop A is set and all other flip-flops are reset.
 When the second clock pulse is applied,the „1‟ on the data input is shifted into flip-flop A and
„1‟ that was in flip flop A is shifted to flip- flop B.
 This continues till all flip-flop sets.
 The data in each stage after each clock pulse is shown in table below

Shift Left Register

The figure below shows the shift left register using D flip- flops.

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  The clock is applied to all the flip- flops simultaneously. The output of each flip-flop is connected
to D input of the flip- flop at its left.
 Each clock pulse shifts the contents of the register one bit position to the left.
 Let us illustrate the entry of the 4-bit binary number 1111 into the register beginning with the
right most bit.
 When the first clock pulse is applied, flip flop A is set and all other flip- flops are reset.
 When second clock pulse is applied, ‟1‟ on the data input is shifted into flip-flop A and „1‟ that
was in flip flop A is shiftedtoflip- flop B. This continues fill all flip- flop are set.
 The data in each stage after each clock pulse is shown in table below.

2. Serial in Parallel out shift register:

A 4 bit serial in parallel out shift register is shown in figure.

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  It consists of one serial input and outputs are taken from all the flip- flops simultaneously.
 The output of each flip- flop is connected to D input of the flip- flop at its right. Each clock pulse
shifts the contents of the register one bit position to the right.
 For example, consider that all stages are reset and a steady logical „1‟ is applied to the serial
input line.
 When the first clock pulse is applied flip flop A is set and all other flip- flops are reset.
 When the second pulse is applied the „1‟ on the data input is shifted into flip flop A and „1‟ that
was in flip flop A is shifted into flip- flop B. This continues till all flip- flops are set. The data in
each stage after each clock pulse is shown in table below.

3. Parallel In Serial Out Shift register:

 For register with parallel data inputs, register the bits are entered simultaneously into their
respective stages on parallel lines.
 A four bit parallel in serial out shift register is shown in figure. Let A,B,C and D be the four
parallel data input lines and SHIFT/LOAD is a control input that allows the four bits of data to be
entered in parallel or shift the serially.

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  When SHIFTS/LOAD is low, gates G1 through G3 are enabled, allowing the data at parallel
inputs to the D input of its respective flip- flop. When the clock pulse is applied the flip- flops
with D=1 will set and those with D=0 will reset, thereby storing all four bits simultaneously.

 When SHIFT/LOADis high. AND gates G1 through G3 are disabled and gates G4 through G6are
enabled, allowing the data bits to shifts right from one stage to next. The OR gates allow either
the normal shifting operation or the parallel data entry operation, depending on which AND gates
are enabled by the level on the SHIFT/LOAD input.

Parallel In Parallel OutShift Register:

 In parallel in parallel out shift register, data inputs can be shifted either in or out of the register in
parallel.
 A four bit parallel in parallel out shift register is shown in figure.Let A, B, C, D be the four
parallel data input lines and Q A,QB,QC and QD be four parallel data output lines. The
SHIFT/LOAD is the control input that allows the four bits data to enter in parallel or shift the
serially.

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Page 40
  When SHIFT/LOAD is low, gates G1 through G3 are enabled, allowing the data at parallel inputs
to the D input of its respective flip- flop. When the clock pulse is applied, the flip- flops with D
=1 willset those with D=0 will reset thereby storing all four bits simultaneously. These are
immediately available at the outputs QA,QB,QC and QD.

 When SHIFT/LOAD is high, gates G1, through G3 are disabled and gates G4 through G6 are
enabled allowing the data bits to shift right from one stage to another. The OR gates allow either
the normal shifting operation or the parallel data entry operation, depending on which AND gates
are enabled by the level on the SHIFT/LOAD input.
**************************************

Universal Shift Register:

Explain about universal shift register.( Apr -2018)
 A register that can shift data to right and left and also has parallel load capabilities is called
universal shift register.
 It has the following capabilities.
1. A clear control to clear the register to 0.
2. A clock input to synchronize the operations.

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Page 42
 3. A shift right control to enable the shift right operation and the associated serial input
and output lines.
4. A shift left control to enable the shift left operation and the associated serial input and
output lines.
5. A parallel load control to enable a parallel transfer and the n input lines.
6. n parallel output lines.
7. A control state that leaves the information in the register unchanged in the presence of
the clock.

 The diagram of 4-bit universal shift register that has all that capabilities listed above is shown in
figure. It consists of four D flip-flop and four multiplexers.Allthe multiplexers have two common
selection inputs S1 and S0. Input 0 is selected when S1S0=00, input 1 is selected when S1S0=01
and similarly for other two inputs.

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  The selection inputs control the mode of operation of the register. When S1S0=00, the present
value of the register is applied to the D inputs of the flip- flop. The next clock pulse transfers
into each flip-flop the binary value it held previously, and no change of state occurs.
 When S1S0=01,terminal 1 of the multiplexer inputs has a path to be the D inputs of the flip- flops.
This causes a shift right operation, with the serial input transferred into flip-flop A3.
 When S1S0=10, a shift left operation results with the other serial input going into flip- flop A0.
Finally, when S1 S0 = 11, the binary information on the parallel input lines is transferred into the
register simultaneously during the next clock edge. The function table is shown below.

****************************************
SHIFT REGISTER COUNTERS:
Explain about Johnson and Ring counter. (Nov 2018)
Most common shift register counters are Johnson counter and ring counter.
Johnson counter:
 A 4 bit Johnson counter using D flip- flop is shown in figure. It is also called shift counter or
twisted counter.

 The output of each flip-flop is connected to D input of the next stage. The inverted output of last
flip- flop QDis connected to the D input of the first flip-flop A.
 Initially, assume that the counter is reset to 0. i.e., Q A QB QC QD =0000. The value at DB =
DC=DD=0, whereas DA =1 since QD.
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Page 45
  When the first clock pulse is applied, the first flip- flop A is set and the other flip- flops are reset.
i.e., QA QB QC QD =1000.
 When the second clock pulse is applies, the counter is QA QB QC QD = 1100. This continues and
the counter will fill up with 1‟s from left to right and then it will fill up with 0‟s again.
 The sequence of states is shown in the table. As observed from the table, a 4-bit shift counter has
8 states. In general, an n-flip-flop Johnson counter will result in 2n states.

The timing diagram of Johnson counter is as follows:

Ring Counter:

A 4- bit ring counter using D Flip-Flop is shown in figure.

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 As shown in figure, the true output of flip- flop D. i.e., QD is connected back to serial input of flip-
flop A.
 Initially, 1 preset into the first flip-flop and the rest of the flip- flops are cleared i.e.,
QAQBQCQD=1000.
 When the first clock pulse is applied, the second flip- flop is set to 1while the other three flip
flops are reset to 0.
 When the second clock pulse is applied, the „1‟ in the second flip-flop is shifted to the third flip-
flop and so on.
 The truth table which describes the operation of the ring counter is shown below.

 As seen a 4-bit ring counter has 4 states. In general, an n-bit ring counter has n states. Since a
single „1‟ in the register is made to circulate around the register, it is called a ring counter. The
timing diagram of the ring counter is shown in figure.

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 ***********************************

HDL FOR SEQUENTIAL CIRCUITS

Write coding in HDL for various flip-flops.

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Page 53
Test Bench:

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Write the VHDL Code for 4-Bit Binary Up Counter and explain. (Apr 2019)
VHDL Code for 4-Bit Binary Up Counter

The clock inputs of all the flip-flops are connected together and are triggered by the input pulses. Thus,
all the flip-flops change state simultaneously (in parallel).

libraryieee;
use ieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityvhdl_binary_counter is
port(C, CLR : in std_logic;
Q : out std_logic_vector(3 downto 0));
endvhdl_binary_counter;
architecturebhv of vhdl_binary_counter
is signaltmp: std_logic_vector(3 downto
0); begin
process (C,
CLR) begin
if (CLR=‟1′) then
tmp<= "0000";
elsif (C‟event and C=‟1′) then
tmp<= tmp + 1;

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end if;
end process;
Q <= tmp;

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 UNIT IV
ASYNCHRONOUS SEQUENTIAL LOGIC
Analysis and Design of Asynchronous Sequential Circuits – Reduction of State and FlowTables – Race-free State
Assignment – Hazards.

Draw the block diagram of a typical asynchronous sequential circuit and explain. Also write the
procedure for obtaining transition table from circuit diagram of an asynchronous sequential circuit.
[Nov – 2019]
Sequential circuits without clock pulses are called Asynchronous Sequential Circuits. They are
classified into 2 types:
1. Fundamental mode circuits
2. Pulse mode circuits
Fundamental Mode Circuits:
It assumes that:
 The input variables should change only when the circuit is stable.
 Only one input variable can change at a given instant of time.
 Inputs and outputs are represented by levels

Pulse Mode Circuits:

It assumes that:
 Inputs and outputs are represented by pulses.
 The width of the pulse is long enough for the circuit to respond to the input.
 The pulse width must not be so long that it is still present after the new state is reached.
Explain about Asynchronous Sequential circuits. (Apr 2017, Nov 2017)
Block diagram of Asynchronous Sequential circuits

. Page1
 The communication oftwo units, with each unithavingits own independent clock, must be donewith
asynchronous circuits.
Stable state:
If the circuit reaches a steady state condition with present state yi = next state Yi for i=1,2,3…K
then the circuit is said to be stable state. A transition from one stable to another occurs only in response
to a change in an input variable.
Unstable state:
In a circuit,ifpresent state yi ≠ next state Yi for i=1,2,3…K then the circuit is said to be unstable
state. The circuit will be in continuous transition till it reached a stable state.

**************************************
ANALYSISPROCEDURE OF FUNDAMENTAL MODE SEQUENTIAL CIRCUITS
Explain in detail about analysis procedure of fundamental mode sequential circuits. (or) Outline the
procedure for analyzing asynchronous sequential circuits. (Apr 2019) (Dec2011)
 The analysis of asynchronous sequential circuits consists of obtaining a table or a diagram that
described the sequence of internal states and outputs as a function of changes in the input
variables.
 Let us consider the asynchronous sequential circuit is shown in figure.

 The analysis of the circuit starts by considering the excitation variables (Y1 and Y2) as outputs and
the secondary variables (y1 and y2) as inputs.
Step1:
 The Boolean expressions
are, Y1= xy1 +xꞌy2
Y2= x y1ꞌ+xꞌy2

Step 2:
 Thenext step is to plottheY1and Y2 functions in amap

. Page2
  Combiningthe binaryvalues in correspondingsquares, the followingtransition table is obtained.
 ThetransitiontableshowsthevalueofY=Y1Y2insideeachsquare.ThoseentrieswhereY=yarecircled to
indicateastable condition.
 The circuit has four stable total states, y1y2 x=000,011,110, and 101 and four unstable total
states- 001, 010, 111 and 100.
 The state table of the circuit is shown below:

 This table provides thesame information as the transition table.

Step 3:
Transition table
 The transition table is obtained by combining the maps for Y1and Y2.

 The transition table is a table which gives the relation between present state, input and next

. Page3
 state. If the secondary variables y1 y2 is same as excitation variables Y1 Y2, the state is said to be stable.
 The stable states are indicated by circles. An uncircled entry represents an unstable state.
 In a transition table, usually there will be at least one stable state in each row. Otherwise,
all the states in that row will be unstable.

Step 4:
Primitive Flowtable
 Ina flow table thestatesarenamed bylettersymbols. Examples of flow tables areas follows:

 In order to obtain thecircuitdescribed bya flow table, it is necessaryto assign to each

stateadistinct value.
****************************
Explain the problems in asynchronous circuits with examples. (Dec 2010,Dec 2012, Dec
2013) Cycles

 A cycle occurs when an asynchronous circuit makes a transition through a series of unstable state.
 When a state assignment is made so that it introduces cycles, care must be taken that it
terminates with a stable state.
 Otherwise, the circuit will go from one unstable state to another, until the inputs are changed.
 Examples of cycles are:

Fig: Examples ofcycles

. Page4
RaceConditions
 Araceconditionexistsinanasynchronouscircuitwhentwoormorebinary state variableschangevalue
inresponsetoachangeinaninputvariable.
 Whenunequaldelaysare encountered,araceconditionmay cause thestatevariableto changein an
unpredictable manner.
 Ifthe final stable statethat the circuitreachesdoes not depend on the orderin which
thestatevariables change, theraceis calledanoncritical race.
 Ifthe final stable statethat the circuitreachesdepends on the orderin which thestatevariables
change, theraceis calleda critical race.
 Examples of noncritical racesareillustratedin the transition tables below:

 Initial stable state is y1y2x = 000 and then input changes from 0 to 1.
 The state variables y1y2 must change from 00 to 11,(race
condition). Possible transitions are
00 11
00 01(y2 faster) 11
00 10(y1 faster) 11

 In all cases final stable state is same, which results in a non-critical race condition.
 Examples of critical racesareillustratedin the transition tables below:

. Page5
 Fig: Examples ofcritical races
 The initial stable state is y1y2 x=000 and let us consider that the input changes from 0 to 1. Then ,
the state variables must change from 00 to 11.
 If they change simultaneously, the final total state is 111.
 Due to unequal propagation delay, if y2 changes to 1 before y1 does, then the circuit goes to total
stable state y1y2 x=011 and remains there.
 If y1 changes first, then the circuit will be in total stable state is y1y2 x=101.

 Hence the race is critical because the circuit goes to different stable states depending on the order
in which the state variables change.
**************************
CIRCUITSWITH SRLATCHES

 TheSRlatchisusedasatime-delayelementinasynchronoussequentialcircuits.TheNORgateSRlatch and
its truth table are:

Fig: SR latchwith NORgates

 The feedback is morevisible when the circuitisredrawn as:

. Page6
  TheBoolean function ofthe output is:

The reduced excitation function,

and the transition table for the circuitis

 The behavior of the SR latch can be investigated from the transition table. The condition to
be avoided is that both S and R inputs must not be 1 simultaneously.
 This condition is avoided when SR = 0 (i.e., ANDing of S and R must always result in 0). When
SR = 0 holds at all times, the excitation function derived previously:

can beexpressed as:

 The NAND gate SR latch and its truth table are:

. Page7
 Fig: SR latchwith NAND gates

 TheconditiontobeavoidedhereisthatbothSandRnotbe0simultaneouslywhichissatisfiedwhenS′R′=0.
 The excitation functionforthe circuitis:

Difference between Synchronous and Asynchronous Sequential Circuit (Apr 2019)

Synchronous Sequential Circuit Asynchronous Sequential Circuit

 It is easy to design.  It is difficult to design.

 A clocked flip flop acts as memory  An unclocked flip flop or time delay
element. is used as memory element.
 They are comparatively faster as no clock
 They are slower as clock is involved.
is used here.
 The states of memory element is  The states of memory element will
affected only at active edge of change any time as soon as input
clock, if input is changed. is changed.
*************************************************
ANALYSISEXAMPLE
Analyze the Asynchronous sequential circuit with suitable example.

Consider the following circuit:

. Page8
 Fig: Example ofa circuit with SR latches

The first step is to obtain the Booleanfunctions forthe S and R inputs in each latch:

The next step is to check if SR = 0 is satisfied:

The result is 0 because

The next step is to derive the transition table of the circuit. The excitation functions are derived from the
relation Y = S + R′y as:

Next a composite map for Y = Y1Y2 is developed

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  Investigation of the transition table reveals that the circuit is stable.
 There is a critical race condition when the circuit is initially in total state y1y2x1x2 = 1101 and x2
changes from 1 to 0.
 If Y1 changes to 0 before Y2, the circuit goes to total state 0100 instead of 0000.
***************************

ImplementationExample of Asynchronous sequential circuits. (Nov 2018)

Consider the followingtransition table:

SR LatchExcitationTable:

UsefulforobtainingtheBooleanfunctionsforSandRandthecircuit’slogicdiagramfromagiven transition table.

FromtheinformationgiveninthetransitiontableandtheSRlatchexcitationtable,wecanobtainmaps forthe S
and R inputs of thelatch:

. Page10
  X represents a don’tcarecondition.
 Themaps arethen used to derivethe simplifiedBoolean functions:

 ThelogicdiagramconsistsofanSRlatchandgatesrequiredtoimplementtheSandRBoolean functions.
 The circuitwhen aNOR SR latch is usedis as shown below:

With a NANDSR latch the complemented valuesforSand R mustbeused.

**************************************

DESIGNPROCEDURE
Explain in detail about design procedure. May
2011 Thereareanumberofstepsthatmustbecarriedoutinordertominimizethecircuitcomplexityandto
produceastable circuitwithoutcritical races.Briefly, thedesign steps areas follows:
 Obtain a primitive flow table from thegivenspecification.
 Reducethe flow table bymerging rows inthe primitive flow table.

 Assign binarystates variables to eachrowof the reduced flowtable to obtain thetransition table.
 Assign outputvalues to thedashes associated with the unstable states to obtainthe output maps.
 Simplifythe Boolean functions of the excitation and output variables and draw the
logic diagram.
 Thedesign process will be demonstrated bygoingthrough aspecificexample:

Designagatedlatchcircuitwithtwoinputs,G(gate)andD(data),andoneoutputQ.Thegatedlatchis amemory

. Page11
 elementthatacceptsthevalueofDwhenG=1andretainsthisvalueafterGgoesto0.Once G =0, a change in D
does notchangethe valueofthe output Q.
(Or)
Design an asynchronous sequential circuit with two inputs D and G with one output Z. Whenever G is
1, input D is transferred to Z. When G is 0, the output does not change for any change in D. Use SR
latch for implementation of the circuit.
PrimitiveFlowTable
 Aprimitiveflowtableisaflowtablewithonlyonestabletotalstateineachrow.Thetotalstateconsists ofthe
internal statecombined with the input.
 To derivethe primitive flow table, first a tablewithallpossible total states in thesystem is
needed:

 Eachrowintheabovetablespecifiesatotalstate;theresulting primitivetableforthegatedlatchis shown

below:

 First,wefillinonesquareineachrowbelonging tothestablestateinthatrow.Nextrecallingthat both

inputsarenotallowedtochangeatthesametime,weenterdashmarksineachrowthatdiffersintwo
ormorevariablesfromtheinputvariablesassociatedwiththestablestate.

. Page12
. Page13
Reduction of primitive flow table:
 Two or more rows in the primitive flow table can be merged into one row if there are non-
conflicting states and outputs on each of the columns.
 This can be done by implication table and merger diagram.
 The implication table has all states except the first vertically and all states except the last across
bottom horizontally.
 The tick (  ) mark denotes that the pair (rows) is compatible.
 Two states are compatible, if the states are identical with non-conflicting outputs.
 The cross (x) mark implies non-compatible.

 The compatible pairs are

(a,b), (a,c), (a,d), (b,e), (b,f), (c,d), (e,f)

Merger Diagram:
 The maximum compatible sets can be obtained from merger diagram as shown in figure.
 The merger diagram is a graph in which each state is represented by a dot placed along the
circumference of a circle.
 Lines are drawn between any two corresponding dot that form a compatible pair.
 Based on the geometrical patterns formed by the lines, all the possible compatibilities can be
obtained.

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  An isolated dot represents a state that is not compatible with any other state.
 A line represents a compatible pair.
 A triangle constitutes a compatible with three states.
 An n-state compatible is represented in the merger diagram by an n-sided polygon with all its
diagonal connected.
 So, the maximal compatibilities are
(a,b) , (a,c,d) , (b,e,f)

Closed covering condition:

 In the above, if only (a,c,d) and (b,e,f) are selected, all the six states
are incuded.
 This set satisfies the covering condition.
 Thus, the rowsa,c,d can be merged as one row and b,e,f states can
be merged as another row.

 Consider a,c,d =a and b,e,f =b

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  A race free binary assignment is made and transition table and
output map is obtained.
a -> 0, b-> 1

Logic Diagram using SR Latch:

. Page16
 ************************
Design an asynchronous sequential circuit that has two inputs X2 and X1 and one output Z. the output
is to remain a 0 as long as X1 is 0. The first change in X2 that occurs while X1 is a 1 will cause output Z
to be 1. The output Z will remain 1 until Xreturns to 0. (Apr 2018)
Step 1:

Step 2: Primitive Flow Table

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Step 3: A reduced flow table is obtained using implication table and merger diagram.

The compatible pairs are (a,b) (a,c) (b,d) (e,f).

The merger diagram is used to find more compatible pairs.

We obtain 4 separate lines.

Therefore, the compatible pairs are again (a,b) (a,c) (b,d) (e,f).
If we remove (a,b), then the remaining pairs (a,c) (b,d) (e,f) covers all the 6 states.
Therefore the reduced flow table is as follows:

Step 4: In order to avoid critical race, one more stable state is added and values are assigned for states.

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Step 5: The transition table and output maps are as follows:

. Page19
 ***********************************

Design an asynchronous sequential circuit with inputs X1 and X2 and one output Z. Initially and at
any time if both the inputs are 0, output is equal to 0. When X 1 and X2 becomes 1, Z becomes 1.
When second input also becomes 1, Z = 0; The output stays at 0 until circuit goes back to initial
state.
Step 1:

Step 2: Primitive Flow Table

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Step 3: A reduced flow table is obtained using Implication table and merger diagram.

The compatible pairs are (a,b) (a,c) (b,c) (b,e) (c,f) (d,e) (d,f) (e,f).
Merger Diagram:

The Maximal Compatibles are (a,b,c) (d,e,f) (c,f) (b,e).

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(c,f) and (b,e) can be removed. Since the remaining terms themselves cover all six states.

Step 4 : State Assignment

Step 5: Logic Diagram

**********************************
Practice Problems:
. Page22
Design a sequential circuit with two D flip flops A and B and one input X. When X = 0, the state
of the circuit remains the same. When X = 1, the circuit goes through the state transitions from 00
to 10 to 11 to 01, back to 00 and then repeats. (Apr 2019)

*************************************
REDUCTION OFSTATE AND FLOW TABLES
Explain in detail about reduction of state and flow tables. Dec.2012
The procedure for reducing the number of internal states in an asynchronous sequential circuit
resembles the procedurethat is used forsynchronous circuits.

Implication Table andImplied State

 The state-reduction procedure for completely specified state tables is based on an algorithm that
combinestwostatesinastatetableintooneaslongastheycanbeshowntobeequivalent.
 Twostates areequivalentif,foreachpossibleinput,theygiveexactlythesameoutputandgotothesamenext
states or to equivalent next states.

 Considerfor examplethestatetableshowninabovetable.
 Thepresentstatesaandbhavethesame outputforthesameinput.
 Theirnextstatesarec anddforx=0andband aforx=1.
 Ifwe canshow thatthe pair of states(c,d) are equivalent,thenthe pair ofstates(a
,b) willalsobeequivalent,because they willhavethesameorequivalentnextstates.
 Whenthisrelationshipexists,wesaythat(a.b)imply (c,d)inthesensethatifaandbare
equivalentthenranddhavetobeequivalent.
 Similarly,fromthe lasttworowsofabovetable,wefindthatthepairofstales(c,d)implies
thepairofstates(a,b).
 The characteristicofequivalentstatesisthatif(a,b)imply (c,d)and(c,d)imply (a,b),thenbothpairsof
statesare equivalentthatis,aandbare equivalent,andsoare candd.
 Asaconsequence,thefour rows oftable can bereduced to tworows bycombining a and b into onestate

. Page23
 and c and d into asecond state.

 The implicationtableisshowninFig.Ontheleftsidealongtheverticalarelistedallthestates
definedinthestatetableexceptthefirstandacrossthebottomhorizontallyarelistedallthestates exceptthelast.
 Theresultisadisplayofallpossiblecombinationsoftwostareswithasquareplacedin
theintersectionofarowandacolumnwhere thetwostatescanbetestedfor equivalence.Twostates
havingdifferent outputs forthe same input arenot equivalent.

Fig: Implication table

 Twostatesthatarenotequivalentaremarkedwithacross[X]inthecorrespondingsquarewhereas
theirequivalenceisrecordedwithacheckmark( ').Someofthesquareshaveentriesofimplied
statesthatmustbeinvestigatedfurthertodeterminewhetherthey areequivalent.
 Thustablecanbe reducedfromsevenstatestofour onefor eachmember ofthe
precedingpartition.Thereducedstate tableis obtained byreplacingstateb bya and states e
andgbydand it is shown below,

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Merging oftheFlowTable
 Incompletelyspecifiedstatescanbecombinedtoreducethenumberofstateintheflowtable.Such stares
cannotbe called equivalentbecause theformaldefinitionof equivalencerequiresthatalloutputs and
nextstatesbe specified forallinputs.
 Instead, twoincompletely specified states that can be
combinedaresaidtobeCompatible.Theprocessthatmustbeappliedinordertofindasuitablegroup of
compatibles forthe purpose ofmerging a flow table can bedivided into threesteps:
1. Determine allcompatible pairs byusingthe implication table.
2. Find themaximal compatibles with the useof amergerdiagram.
3. Find a minimal collection of compatibles that covers allthe states andis closed.

CompatiblePairs-
 Theentriesineachsquareofprimitiveflowtablerepresentthenextstate
andoutputThedashesrepresenttheunspecifiedstatesoroutputs.
 Theimplicationtable
isusedtofmdcompatiblestatesjustasitisusedtofindequivalentstalesinthecompletely
specifiedcase.Theonly
differenceisthat,whencomparingrows,weareatlibertytoadjustthedashestofitany desired condition.

. Page25
 The compatiblepairsare,

MaximalCompatibles

 Themaximal compatibleisagroupofcompatiblesthatcontainsallthe possiblecombinations of

compatible states. The maximal compatiblecanbeobtained from a merger diagram.
 The merger diagramisagraphinwhicheachstateisrepresented by adotplacedalongthecircumferenceofa
circle. Linesaredrawnbetweenany twocorrespondingdotsthatformacompatiblepair.
 Allpossible compatiblescanbeobtainedfromthemergerdiagramby
observingthegeometricalpatternsinwhich
statesareconnectedtoeachother.Anisolateddotrepresentsastatethatisnotcompatiblewithany
otherstate. A line representsa compatiblepair.Atriangleconstitutes a compatiblewith threestates.

. Page26
 Themaximal compatiblesof fig (a)are

Themaximal compatiblesof fig

(b)are

Closed-Covering Condition
 Theconditionthatmustbesatisfiedformergingrowsisthatthesetofchosencompatiblesmustcover
allthestatesandmustbeclosed.
 Thesetwillcoverallthestatesifitincludesallthestatesofthe originalstatetable.The closureconditionis
satisfiedifthereare noimpliedstatesorif theimplied states are
includedwithintheset.Aclosedsetofcompatiblesthatcoversallthestatesiscalledaclosed covering.

***********************************

RACE -FREE STATE ASSIGNMENT

Explain in detail about race -free state assignment. May 2012,Dec. 2014
 Once areducedflow tablehasbeenderivedfor anasynchronoussequentialcircuit,thenextstepinthe
designistoassignbinary variablestoeachstablestate.
 Thisassignmentresultsinthetransformationof
theflowtableintoitsequivalenttransitiontable.Theprimaryobjectiveinchoosing aproperbinary state
assignmentisthepreventionofcriticalraces.

. Page27
  Criticalracescanbeavoidedbymakingabinarystate assignmentinsuchawaythatonly
onevariablechangesatanygiventimewhenastatetransitionoccurs in the flow table.

. Page28
Three-RowFlow-Table Example

Fig: Three rowflowtable example

 Toavoidcriticalraces,wemustfindabinarystateassignmentsuchthatonly onebinaryvariable
changesduring eachstatetransition.
 Anattempttofindsuchanassignmentisshowninthetransition diagram.Statea isassignedbinary
00,andstatecisassignedbinary 11.
 Thisassignmentwillcausea
criticalraceduringthetransitionfromatocbecausetherearetwochangesinthebinary statevariables
andthetransitionfromatocmay occurdirectlyorpassthroughb.
 Notethatthetransitionfromctoaalsocausesaracecondition,butitisnoncriticalbecausethetransitiondoesn
otpassthroughother states

Fig:Flowtable with an extrarow

 Arace- freeassignmentcanbeobtainedifweaddanextra rowtotheflow table.Theuseofa fourthrow
doesnotincreasethenumberofbinarystatevariables,butitallowstheformationof cycles betweentwo
stablestates.
 Thetransitiontablecorrespondingtotheflowtablewiththeindicatedbinarystateassignmentisshown
inFig.
. Page29
  Thetwodashesinrowdrepresentunspecifiedstatesthatcanbeconsidereddon't-care conditions.
 However,caremustbetakennottoassign10tothesesquares,inordertoavoidthepossibility ofan unwanted
stablestatebeingestablishedin thefourth row.

Fig: Transitiontable

Four-RowFlow-Table Example
 A flow tablewith four rows requiresaminimum of two statevariables.
 Although arace- freeassignment issometimespossiblewithonly twobinary
statevariables,inmany casestherequirementofextrarows to avoid critical races willdictate
theuse of threebinarystate variables

Fig:Four-rowflow-table example
 Thefollowing figureshowsastateassignmentmapthatissuitableforany four-
rowflowtable.Statesa, b,canddaretheoriginalstatesande,fandgareextrastates.
 Thetransitionfromatodmustbe directedthroughtheextrastateetoproduceacyclesothatonly
onebinaryvariablechangesatatime.
Similarly,thetransitionfromctoaisdirectedthroughgandthetransitionfromdtocgoesthroughf.
 Byusingtheassignmentgivenby themap,thefour-rowtablecanbeexpandedtoaseven-rowtablethat is
freeofcritical races.

. Page30
 Fig: Choosing extrarowsfor theflowtable
 Notethatalthoughtheflowtablehas sevenrowsthereareonlyfourstablestates.
 Theuncircledstatesin the three extra rowsaretheremerelyto providearace- freetransition between
thestablestates.

Fig: Stateassignment to modified flowtable

Multiple-RowMethod
 Themethodformakingrace- freestaleassignmentsbyaddingextrarowsintheflowtableisreferredto asthe
shared-rowmethod.
 A second methodcalled themultiple-rowmethodisnotasefficient, butis easiertoapply.Inmultiple-
rowassignmenteachstateintheoriginalrowtableisreplacedby twoor more combinationsofstate
variables.

. Page31
 Fig:Multiple rowassignment
 Therearetwobinary statevariablesforeachstablestate,eachvariablebeingthelogicalcomplementof the
other.
 Forexample,the originalstatea is replacedwithtwoequivalentstates a1=000anda2=111.
Theoutputvalues,notshownheremustbethesameina1anda2.
 Notethata1 isadjacenttob1,c2and d1,anda2 isadjacenttoc1,
b2andd2,andsimilarlyeachstateisadjacenttothreestateswithdifferent letterdesignations.
 Theexpandedtableisformedbyreplacingeachrowoftheoriginaltablewithtworows.Inthemultiple-
rowassignment,thechange fromonestablestate10another willalwayscauseachangeofonly one
binarystate variable.
 Each stable stalehastwo binaryassignmentswith exactlythe sameoutput.
***********************************


Practice Problems:
A sequential Circuit with two D flip flops A and B, two inputs X and Y, and one output Z is
specified by the following input equations:
A( t + 1) = x’y + xA
B( t + 1) = x’B + xA
Z=B
Draw the logic diagram of the circuit. Derive the state table and state diagram and state whether it
is a Mealy or a Moore machine. (Apr 2019)
***************************

HAZARDS
Discuss about the possible hazards and methods to avoid them in combinational circuits. (or) Explain
in detail about hazards. May 2011, Dec. 2013, Apr 2017, Nov 2017, Apr 2018, Nov 2018, Apr 2019

. Page32
  Hazardsareunwantedswitchingtransientsthatmay appearattheoutputofacircuitbecausedifferent
pathsexhibitdifferentpropagationdelays.
 Hazardsoccurincombinationalcircuits,wheretheymay causeatemporary falseoutputvalue.But
inasynchronous sequentialcircuits hazardsmay resultin a transitionto awrongstable state.

Types of Hazards
 Static Hazard
 Dynamic Hazard
 Essential Hazard

Static Hazard
 Static Hazard is a condition which results in a single momentary incorrect output due to change in
a single input variable when the output is expected to remain in the same state.
 The static hazard may be either static-0 or Static -1.

Hazards inCombinational Circuits

 Ahazardisaconditioninwhichachangeinasinglevariableproducesamomentary changeinoutput
when no changein output should occur.

Fig: Circuits with Hazards

 Assumethatallthreeinputsareinitially equalto1.Thiscausestheoutputofgate110be1,thatofgate
2tobe0andthatofthecircuittobe1.Nowconsiderachangeinx2from1to0.

 Thentheoutputof gate1changesto0and thatofgate2changesto1,leaving theoutputat

1.However,theoutputmay

. Page33
 momentarilygoto0ifthepropagationdelaythroughtheinverteristakenintoconsideration.
 Thedelay in theinvertermaycausetheoutput ofgate1 to changeto 0 beforethe output of gate2
changes to1.
 Thetwo circuits shown in Figimplement theBoolean function in sum-of-products form:

 This type of implementation may cause the output to go to 0 when it should remain a 1. If however,
theCircuit is implemented instead in product-of-sums form namely,

then the output may momentarily go to 1 when it should remain 0. The first case is referred to a
static1-hazard and the second case as static 0-hazard.
 Athirdtypeofhazard,knownasdynamichazard,causestheoutputtochangethreeormoretimes
when itshould changefrom1 to 0 or from 0 to 1.

Fig: Types ofhazards

 The change in x2from1to0movesthecircuitfromminterm111tominterm101.The hazard exists
because the changein input results in a different product term coveringthe twominterm.

Fig: Illustrates hazardandits removal

 Minterm111iscoveredby theproducttermimplementedingate1andminterm101iscoveredbythe
producttermimplementedingate2.
 The remedy for eliminating a hazard is to enclose the two min terms
withanotherproducttermthatoverlapsbothgroupings. Thehazard-freecircuitobtainedbysucha
configurationisshowninfigure below.
 The extra gate inthecircuitgeneratesthe producttermx1x3.In

. Page34
. Page35
 general,hazardsincombinationalcircuitscanberemoved by coveringany twomintermsthatmay
producea hazardwithaproducttermcommontoboth.
 Theremovalofhazardsrequirestheadditionof redundantgates to thecircuit.

Hazards in SequentialCircuits
 Innormalcombinational-circuitdesignassociatedwithsynchronoussequentialcircuits,hazardsareof
noconcern,sincemomentaryerroneoussignalsare notgenerallytroublesome.
 However,ifamomentary incorrectsignalisfed backinanasynchronoussequentialcircuit,itmay
causethecircuittogotothe wrongstable state.

Fig: HazardinanAsynchronous sequential circuit

 Ifthe circuitis in total stable stateyx1x2=111 and inputx2 changesfromIto0, the next total stablestate
shouldbe110.However,because ofthehazard,outputYmay goto0momentarily.
 Ifthisfalsesignal
feedsbackintogate2beforetheoutputoftheinvertergoesto1,theoutputofgate2willremainat0

. Page36
 andthecircuitwillswitchtotheincorrecttotalstablestate 010.
 Thismalfunctioncanbe eliminatedby adding an extragate.

Essential Hazards
 Essentialhazardiscausedby unequaldelaysalongtwoormorepathsthatoriginatefromthesame input.
 Anexcessivedelaythroughaninvertercircuitincomparisontothedelayassociatedwiththe feedback path
maycausesuchahazard.
 Essentialhazards cannotbecorrectedby addingredundantgatesasinstatichazards.The problemthat they
imposecanbecorrectedbyadjustingtheamountofdelay intheaffectedpath.
 Toavoidessential
hazards,eachfeedbackloopmustbehandledwithindividualcaretoensurethatthedelayinthe
feedbackpathislongenoughcomparedwithdelaysofothersignalsthatoriginate fromtheinput terminals.

***********************************

. Page37
. Page38
. Page39
 *********************

. Page40
Problems on hazards: (Nov 2018)

. Page41
. Page42
. Page43
. Page44
. Page45
UNIT V MEMORY AND PROGRAMMABLE LOGIC 12

RAM – Memory Decoding – Error Detection and Correction - ROM -Programmable

Logic Array – Programmable Array Logic – Sequential Programmable Devices.

51 INTRODUCTION
A memory unit is a collection of storage cells with associated circuits needed
to transfer information in and out of the device The binary information is transferred
for storage and from which information is available when needed for processing
When data processing takes place, information from the memory is transferred to
selected registers in the processing unit Intermediate and final results obtained in the
processing unit are transferred back to be stored in memory

52 Units of Binary Data: Bits, Bytes, Nibbles and Words

As a rule, memories store data in units that have from one to eight bits The
smallest unit of binary data is the bit In many applications, data are handled in an 8-
bit unit called a byte or in multiples of 8-bit units The byte can be split into two 4-
bit units that are called nibbles A complete unit of information is called a word and
generally consists of one or more bytes Some memories store data in 9-bit groups; a
9-bit group consists of a byte plus a parity bit

53 Basic Semiconductor Memory Array

Each storage element in a memory can retain either a 1 or a 0 and is called a
cell Memories are made up of arrays of cells, as illustrated in Figure below using 64
cells as an example Each block in the memory array represents one storage cell, and
its location can be identified by specifying a row and a column

1
Programmable Logic Devices, Memory

A 64-cell memory array organized in three different ways

54 Memory Address and Capacity

The location of a unit of data in a memory array is called its address For
example, in Figure (a), the address of a bit in the 3-dimensional array is specified by
the row and column In Figure (b), the address of a byte is specified only by the row
in the 2-dimensional array So, as you can see, the address depends on how the
memory is organized into units of data Personal computers have random-access
memories organized in bytes This means that the smallest group of bits that can be
addressed is eight

Examples of memory address

2
Programmable Logic Devices, Memory

The capacity of a memory is the total number of data units that can be stored
For example, in the bit-organized memory array in Figure (a), the capacity is 64 bits
In the byte-organized memory array in Figure (b), the capacity is 8 bytes, which is
also 64 bits Computer memories typically have 256 MB (megabyte) or more of
internal memory

55 Basic Memory Operations

Since a memory stores binary data, data must be put into the memory and
data must be copied from the memory when needed The write operation puts data
into a specified address in the memory, and the read operation copies data out of a
specified address in the memory The addressing operation, which is part of both the
write and the read operations, selects the specified memory address

Data units go into the memory during a write operation and come out of the
memory during a read operation on a set of lines called the data bus As indicated
in Figure, the data bus is bidirectional, which means that data can go in either
directional (into the memory or out of the memory)

Block diagram of memory operation

For a write or a read operation, an address is selected by placing a binary code

representing the desired address on a set of lines called the address bus The address
code is decoded internally and the appropriate address is selected The number of
lines in the address bus depends on the capacity of the memory For example, a 15-bit
address code can select 32,768 locations (215) in the memory; a 16-bit address code
can select 65,536 locations (216) in the memory and so on

3
Programmable Logic Devices, Memory

In personal computers a 32-bit address bus can select 4,294,967,296 locations

(232), expressed as 4GB

551 Write Operation

To store a byte of data in the memory, a code held in the address register is
placed on the address bus Once the address code is on the bus, the address decoder
decodes the address and selects the specified location in the memory The memory
then gets a write command, and the data byte held in the data register is placed on
the data bus and stored in the selected memory address, thus completing the write
operation When a new data byte is written into a memory address, the current data
byte stored at that address is overwritten (replaced with a new data byte)

Illustration of the Write operation

552 Read Operation

A code held in the address register is placed on the address bus Once the
address code is on the bus, the address decoder decodes the address and selects the
specified location in the memory The memory then gets a read command, and a
"copy" of the data byte that is stored in the selected memory address is placed on the
data bus and loaded into the data register, thus completing the read operation When
a data byte is read from a memory address, it also remains stored at that address
This is called nondestructive read

4
Programmable Logic Devices, Memory

Illustration of the Read operation

56 Classification of Memories

There are two types of memories that are used in digital systems:

Random-Access Memory (RAM),

Read-Only Memory (ROM)

RAM (random-access memory) is a type of memory in which all addresses are

accessible in an equal amount of time and can be selected in any order for a read or
write operation All RAMs have both read and write capability Because RAMs lose
stored data when the power is turned off, they are volatile memories

ROM (read-only memory) is a type of memory in which data are stored

permanently or semi permanently Data can be read from a ROM, but there is no
write operation as in the RAM The ROM, like the RAM, is a random-access memory
but the term RAM traditionally means a random-access read/write memory
Because ROMs retain stored data even if power is turned off, they are
nonvolatile memories

5
Programmable Logic Devices, Memory

Classification of memories

561 RANDOM-ACCESS MEMORIES (RAMS)

RAMs are read/write memories in which data can be written into or read
from any selected address in any sequence When a data unit is written into a given
address in the RAM, the data unit previously stored at that address is replaced by
the new data unit When a data unit is read from a given address in the RAM, the
data unit remains stored and is not erased by the read operation This nondestructive
read operation can be viewed as copying the content of an address while leaving the
content intact

A RAM is typically used for short-term data storage because it cannot retain
stored data when power is turned off

The two categories of RAM are the static RAM (SRAM) and the dynamic
RAM (DRAM) Static RAMs generally use flip-flops as storage elements and can
therefore store data indefinitely as long as dc power is applied Dynamic
RAMs use capacitors as storage elements and cannot retain data very long without
the capacitors being recharged by a process called refreshing Both SRAMs and
DRAMs
will lose stored data when dc power is removed and, therefore, are classified as
volatile memories

Data can be read much faster from SRAMs than from DRAMs However,
DRAMs can store much more data than SRAMs for a given physical size and cost
because the DRAM cell is much simpler, and more cells can be crammed into a given
chip area than in the SRAM

6
Programmable Logic Devices, Memory

5611 Static RAM (SRAM)

Storage Cell:

All static RAMs are characterized by flip-flop memory cells As long as dc

power is applied to a static memory cell, it can retain a 1 or 0 state indefinitely If
power is removed, the stored data bit is lost

The cell is selected by an active level on the Select line and a data bit (l or 0) is
written into the cell by placing it on the Data in line A data bit is read by taking it
off the Data out line

Basic SRAM Organization:

Basic Static Memory Cell Array

The memory cells in a SRAM are organized in rows and columns All the cells
in a row share the same Row Select line Each set of Data in and Data out lines go to
each cell in a given column and are connected to a single data line that serves as
both an input and output (Data I/O) through the data input and data output buffers

SRAM chips can be organized in single bits, nibbles (4 bits), bytes (8 bits), or
multiple bytes (16, 24, 32 bits, etc) The memory cell array is arranged in 256 rows
and
128 columns, each with 8 bits as shown below There are actually 215 = 32,768
addresses and each address contains 8 bits The capacity of this example memory is
32,768 bytes (typically expressed as 32 Kbytes)

Memory array configuration

7
Programmable Logic Devices, Memory

Operation:

The SRAM works as follows First, the chip select, CS, must be LOW for the
memory to operate Eight of the fifteen address lines are decoded by the row decoder
to select one of the 256 rows Seven of the fifteen address lines are decoded by the
column decoder to select one of the 128 8-bit columns

Memory block diagram

Read:

In the READ mode, the write enable input, WE‘ is HIGH and the output
enable, OE‗ is LOW The input tri state buffers are disabled by gate G1, and the
column output tristate buffers are enabled by gate G2 Therefore, the eight data bits
from the selected address are routed through the column I/O to the data lines (I/O 1
through I/O7), which are acting as data output lines

Write:
In the WRITE mode, WE‘ is LOW and OE‘ is HIGH The input buffers are
enabled by gate G1, and the output buffers are disabled by gate G2 Therefore the
eight input data bits on the data lines are routed through the input data control and
the column I/O to the selected address and stored

8
Programmable Logic Devices, Memory

Read and Write Cycles:

For the read cycle shown in part (a), a valid address code is applied to the
address lines for a specified time interval called the read cycle time, tWC Next,
the chip select (CS) and the output enable (DE) inputs go LOW One time interval
after the DE input goes LOW; a valid data byte from the selected address appears
on the
data lines This time interval is called the output enable access time, tGQ Two
other access times for the read cycle are the address access time, tAQ, measured
from the beginning of a valid address to the appearance of valid data on the data
lines and the
chip enable access time, tEQ, measured from the HIGH-to-LOW transition of CS to
the appearance of valid data on the data lines

During each read cycle, one unit of data, a byte in this case is read from
the memory

For the write cycle shown in Figure (b), a valid address code is applied to the
address lines for a specified time interval called the write cycle time, tWE Next,
the chip select (CS) and the write enable (WE) in puts go LOW The required time
interval from the beginning of a valid address until the WE input goes LOW is called
the address setup time, t s(A) The time that the WE input must be LOW is the
write pulse width The time that the input WE must remain LOW after valid data are
applied to the data inputs is designated t WD; the time that the valid input data must
remain on the data lines after the WE input goes HIGH is the data hold time, t h(D)

During each write cycle, one unit of data is written into the memory

9
Programmable Logic Devices, Memory

562 READ- ONLY MEMORIES (ROMS)

A ROM contains permanently or semi-permanently stored data, which can

be read from the memory but either cannot be changed at all or cannot be changed
without specialization equipment A ROM stores data that are used repeatedly in
system applications, such as tables, conversions, or programmed instructions for
system initialization and operation ROMs retain stored data when the power is
OFF and are therefore nonvolatile memories

The ROMs are classified as follows:

i. Masked ROM (ROM)

ii. Programmed ROM (PROM)

iii. Erasable PROM (EPROM)

iv. Electrically Erasable PROM (EEPROM)

5621 Masked ROM

The mask ROM is usually referred to simply as a ROM It is permanently

programmed during the manufacturing process to provide widely used standard
functions, such as popular conversions, or to provide user-specified functions Once
the memory is programmed, it cannot be changed

Most IC ROMs utilize the presence or absence of a transistor connection at a

row/column junction to represent a 1 or a 0 The presence of a connection from a row
line to the gate of a transistor represents a 1 at that location because when the row
line is taken HIGH; all transistors with a gate connection to that row line turn on

10
Programmable Logic Devices, Memory 511
and connect the HIGH (1) to the associated column lines

ROM Cells

At row/column junctions where there are no gate connections, the column lines
remain LOW (0) when the row is addressed
5622 PROM (Programmable Read-Only Memory)

The PROM (Programmable Read-only memory), comes from the

manufacturer unprogrammed and are custom programmed in the field to meet the
user‘s needs

A PROM uses some type of fusing process to store bits, in which a memory
link is burned open or left intact to represent a 0 or a 1 The fusing process is
irreversible; once a PROM is programmed, it cannot be changed

The fusible links are manufactured into the PROM between the source of
each cell's transistor and its column line In the programming process, a sufficient
current is injected through the fusible link to bum it open to create a stored O The
link is left intact for a stored 1 All drains are commonly connected to VDD

PROM array with fusible links

11
Programmable Logic Devices, Memory

Three basic fuse technologies used in PROMs are metal links, silicon
links, and pn junctions A brief description of each of these follows

1. Metal links are made of a material such as nichrome Each bit in the memory
array is represented by a separate link During programming, the link is either
"blown" open or left intact This is done basically by first addressing a given cell
and then forcing a sufficient amount of current through the link to cause it to
open When the fuse is intact, the memory cell is configured as a logic 1 and
when fuse is blown (open circuit) the memory cell is logic 0

2. Silicon links are formed by narrow, notched strips of polycrystalline silicon

Programming of these fuses requires melting of the links by passing a sufficient
amount of current through them This amount of current causes a high
temperature at the fuse location that oxidizes the silicon and forms insulation
around the now-open link

3. Shorted junction, or avalanche-induced migration, technology consists

basically of two pn junctions arranged back-to-back During programming, one of
the diode junctions is avalanched, and the resulting voltage and heat cause
aluminum ions to migrate and short the junction The remaining junction is then
used as a forward- biased diode to represent a data bit

5623 EPROM (Erasable Programmable ROM)

An EPROM is an erasable PROM Unlike an ordinary PROM, an EPROM can
be reprogrammed if an existing program in the memory array is erased first

An EPROM uses an NMOSFET array with an isolated-gate structure The

isolated transistor gate has no electrical connections and can store an electrical
charge for indefinite periods of time The data bits in this type of array are
represented by the presence or absence of a stored gate charge Erasure of a data bit is
a process that removes the gate charge

12
Programmable Logic Devices, Memory
Two basic types of erasable PROMs are the ultraviolet erasable PROM (UV
EPROM) and the electrically erasable PROM (EEPROM)

x UV EPROM:
You can recognize the UV EPROM device by the transparent quartz lid on the
package, as shown in Figure below The isolated gate in the FET of an ultraviolet
EPROM is "floating" within an oxide insulating material The programming process
causes electrons to be removed from the floating gate Erasure is done by exposure
of the memory array chip to high-intensity ultraviolet radiation through the quartz
window on top of the package

The positive charge stored on the gate is neutralized after several minutes to an
hour of exposure time In EPROM‘s, it is not possible to erase selective information,
when erased the entire information is lost The chip can be reprogrammed

It is ideally suited for product development, college laboratories, etc

Ultraviolet Erasable PROM

During programming, address and datas are applied to address and data pins
of the EPROM The program pulse is applied to the program input of the EPROM
The program pulse duration is around 50msec and its amplitude depends on
EPROM IC It is typically 115V to 25V

In EPROM, it is possible to program any location at any time- either

individually, sequentially or at random
5624 EEPROM (Electrically Erasable PROM)

The EEPROM (Electrically Erasable PROM), also uses MOS circuitry Data is
stored as charge or no charge on an insulating layer, which is made very thin (<
200Å) Therefore a voltage as low as 20- 25V can be used to move charges across the
thin barrier in either direction for programming or erasing ROM

13
Programmable Logic Devices, Memory

An electrically erasable PROM can be both erased and programmed with

electrical pulses Since it can be both electrically written into and electrically erased,
the EEPROM can be rapidly programmed and erased in-circuit for reprogramming
It allows selective erasing at the register level rather than erasing all the
information, since the information can be changed by using electrical signals
It has chip erase mode by which the entire chip can be erased in 10
msec Hence EEPROM‘s are most expensive
Advantages of RAM:

1. Fast operating speed (< 150 nsec),

2. Low power dissipation (< 1mW),
3. Economy,
4. Compatibility,
5. Non-destructive read-out

Advantages of ROM:

1. Ease and speed of design,

2. Faster than MSI devices (PLD and FPGA)
3. The program that generates the ROM contents can easily be structured to
handle unusual or undefined cases,
4. A ROM‘s function is easily modified just by changing the stored
pattern, usually without changing any external connections,
5. More economical

14
Programmable Logic Devices, Memory

Disadvantages of ROM:

1. For functions more than 20 inputs, a ROM based circuit is

impractical because of the limit on ROM sizes that are available
2. For simple to moderately complex functions, ROM based circuit may be
costly: consume more power; run slower
Comparison between RAM and ROM:

SNo RAM RO M
RAMs have both read and write
1 ROMs have only read operation capability

RAMs are volatile memories ROMs are non-volatile memories

They lose stored data when the They retain stored data even if power is
3
power is turned OFF turned off
RAMs are available in both RAMs are available in both bipolar and
4
bipolar and MOS technologies MOS technologies
Types: SRAM, DRAM, EEPROM Types: PROM, EPROM

Comparison between SRAM and DRAM:

SNo Static RAM Dynamic RAM

1 It contains less memory cells It contains more memory cells per unit area
per unit area
2 Its access time is less, hence Its access time is greater than static RAM
faster memories
3 It consists of number of flip- It stores the data as a charge on the capacitor
flops Each flip-flop stores It consists of MOSFET and capacitor for each
one bit cell
4 Refreshing circuitry is not Refreshing circuitry is required to maintain
required the charge on the capacitors every time after
every few milliseconds Extra hardware is
required to control refreshing
5 Cost is more Cost is less

15
Programmable Logic Devices, Memory

Comparison of Types of Memories:

Memory O ne- Tra nsistor In-s yste m

N on- Volatile High Density
type cell writability
SRAM No No No Yes
DRAM No Yes Yes Yes
ROM Yes Yes Yes No
EPROM Yes Yes Yes No
EEPROM Yes No No Yes

58 PROGRAMMABLE LOGIC DEVICES:

581 INTRODUCTION:
A combinational PLD is an integrated circuit with programmable gates
divided into an AND array and an OR array to provide an AND-OR sum of product
implementation The PLD‘s can be reprogrammed in few seconds and hence gives
more flexibility to experiment with designs Reprogramming feature of PLDs also
makes it possible to accept changes/modifications in the previously design circuits

The advantages of using programmable logic devices are:

1. Reduced space requirements

2. Reduced power requirements
3. Design security
4. Compact circuitry
5. Short design cycle
6. Low development cost
7. Higher switching speed
8. Low production cost for large-quantity production

16
Programmable Logic Devices, Memory

According to architecture, complexity and flexibility in programming in PLD‘s

are classified as—

PROMs : Programmable Read Only memories,

PLAs Programmable Logic Arrays,
PAL Programmable Logic Array,
FPGA : Field Programmable Gate Arrays,
CPLDs Complex Pro gra mma ble Lo gic Devices

Programmable Arrays:

All PLDs consists of programmable arrays A programmable array is

essentially a grid of conductors that form rows and columns with a fusible link at
each cross point Arrays can be either fixed or programmable

The OR Array:
It consists of an array of OR gates connected to a programmable matrix with
fusible links at each cross point of a row and column, as shown in the figure below
The array can be programmed by blowing fuses to eliminate selected variables from
the output functions For each input to an OR gate, only one fuse is left intact in
order to connect the desired variable to the gate input Once the fuse is blown, it
cannot be reconnected
Another method of programming a PLD is the antifuse, which is the opposite of the fuse
Instead of a fusible link being broken or opened to program a variable, a normally
open contact is shorted by ―melting‖ the antifuse material to form a connection

17
Programmable Logic Devices, Memory

An example of a basic programmable OR array

The AND Array:

This type of array consists of AND gates connected to a programmable matrix
with fusible links at each cross points, as shown in the figure below Like the OR
array, the AND array can be programmed by blowing fuses to eliminate selected
variables from the output functions For each input to an AND gate, only one fuse is
left intact in order to connect the desired variable to the gate input Also, like the OR
array, the AND array with fusible links or with antifuses is one-time programmable

An example of a basic programmable AND array

18
Programmable Logic Devices, Memory

582 Classification of PLDs

There are three major types of combinational PLDs and they differ
in the placement of the programmable connections in the AND-OR array
The configuration of the three PLDs is shown below

1 Programmable Read-Only Memory (PROM):

A PROM consists of a set of fixed (non-programmable) AND array

constructed
as a decoder and a programmable OR array The programmable OR
gates implement the Boolean functions in sum of minterms

(a) Programmable read- only memory (PROM)

2. Programmable Logic Array (PLA):

A PLA consists of a programmable AND array and a programmable OR

array
The product terms in the AND array may be shared by any OR gate to
provide the required sum of product implementation
The PLA is developed to overcome some of the limitations of the PROM The
PLA is also called an FPLA (Field Programmable Logic Array) because the user in
the field, not the manufacturer, programs it

Programmable Logic Array (PLA)

19
Programmable Logic Devices, Memory

3 Programmable Array Logic (PAL):

The basic PAL consists of a programmable AND array and a fixed OR array
The AND gates are programmed to provide the product terms for the
Boolean functions, which are logically summed in each OR gate
It is developed to overcome certain disadvantages of the PLA, such as
longer delays due to the additional fusible links that result from using two
programmable arrays and more circuit complexity

Programmable Array Logic (PAL)

Array logic Symbols:

PLDs have hundreds of gates interconnected through hundreds of

electronic fuses It is sometimes convenient to draw the internal logic of such
device in a compact form referred to as array logic

20
Programmable Logic Devices, Memory

583 PROGRAMMABLE ROM:

PROMs are used for code conversions, generating bit patterns for characters
and as look-up tables for arithmetic functions

As a PLD, PROM consists of a fixed AND-array and a programmable OR

array The AND array is an n-to-2n decoder and the OR array is simply a collection of
programmable OR gates The OR array is also called the memory array The decoder
serves as a minterm generator The n-variable minterms appear on the 2n lines at
the decoder output The 2n outputs are connected to each of the ‗m‘ gates in the OR
array via programmable fusible links

2n x m PROM

584 Implementation of Combinational Logic Circuit using PROM

1. Using PROM realize the following expression
F1 (A, B, C) = ∑m (0, 1, 3, 5, 7)

F2 (A, B, C) = ∑m (1, 2, 5, 6)

Step1: Truth table for the given function

A B C F1 F2

0 0 0 1 0
0 0 1 1 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 0
1 0 1 1 1
1 1 0 0 1
1 1 1 1 0

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Programmable Logic Devices, Memory

Step 2: PROM diagram

2. Design a combinational circuit using PROM The circuit accepts 3-bit binary and
generates its equivalent Excess-3 code

Step1: Truth table for the given function

B2 B1 B0 E3 E2 E1 E0

0 0 0 0 0 1 1
0 0 1 0 1 0 0
0 1 0 0 1 0 1
0 1 1 0 1 1 0
1 0 0 0 1 1 1
1 0 1 1 0 0 0
1 1 0 1 0 0 1
1 1 1 1 0 1 0

22
Programmable Logic Devices, Memory

Step 2: PROM diagram

585 PROGRAMMABLE LOGIC ARRAY: (PLA)

The PLA is similar to the PROM in concept except that the PLA does not
provide full coding of the variables and does not generate all the minterms
The decoder is replaced by an array of AND gates that can be programmed to
generate any product term of the input variables The product term are then
connected to OR gates to provide the sum of products for the required Boolean
functions The AND gates and OR gates inside the PLA are initially fabricated with
fuses among them The specific boolean functions are implemented in sum of
products form by blowing the appropriate fuses and leaving the desired
connections

23
Programmable Logic Devices, Memory

PLA block diagram

The block diagram of the PLA is shown above It consists of ‗n‘ inputs, ‗m‘
outputs, ‗k‘ product terms and ‗m‘ sum terms The product terms constitute a group of ‗k‘
AND gates and the sum terms constitute a group of ‗m‘ OR gates Fuses are inserted
between all ‗n‘ inputs and their complement values to each of the AND gates Fuses are
also provided between the outputs of the AND gate and the inputs of the OR gates

Another set of fuses in the output inverters allow the output function to be
generated either in the AND-OR form or in the AND-OR-INVERT form With the inverter fuse
in place, the inverter is bypassed, giving an AND-OR implementation With the fuse blown,
the inverter becomes part of the circuit and the function is implemented in the AND -OR-
INVERT form

586 Implementation of Combinational Logic Circuit using PLA

1. Implement the combinational circuit with a PLA having 3 inputs,

4 product terms and 2 outputs for the functions
F1 (A, B, C) = ∑m (0, 1, 2, 4)
F2 (A, B, C) = ∑m (0, 5, 6, 7)
Solution:

Step 1: Truth table for the given functions

A B C F1 F2
0 0 0 1 1
0 0 1 1 0
0 1 0 1 0
0 1 1 0 0

24
Programmable Logic Devices, Memory

1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 0 1

Step 2: K-map Simplification

With this simplification, total number of product term is 6 But we require

only 4 product terms Therefore find out F1‘ and F2‘

Now select, F1‘ and F2, the product terms are AC, AB, BC and A‘B‘C‘

Step 3: PLA Program table:

Input
Product s Outputs
term A B C F1 (C) F2 (T)
AB 1 1 1 - 1 1
AC 2 1 - 1 1 1
BC 3 - 1 1 1 -
A‘B‘C‘ 4 0 0 0 - 1

25
Programmable Logic Devices, Memory

In the PLA program table, first column lists the product terms numerically as
1, 2, 3, and 5 The second column (Inputs) specifies the required paths between the
AND gates and the inputs For each product term, the inputs are marked with 1, 0, or
- (dash) If a variable in the product form appears in its normal form, the
corresponding input variable is marked with a 1 If it appears complemented, the
corresponding input variable is marked with a 0 If the variable is absent in the
product term, it is marked with a dash ( - ) The third column (output) specifies the
path between the AND gates and the OR gates The output variables are marked with
1‘s for all those product terms that formulate the required

function Step 4: PLA Diagram

The PLA diagram uses the array logic symbols for complex symbols Each
input and its complement is connected to the inputs of each AND gate as indicated
by the intersections between the vertical and horizontal lines The output of the AND
gate are connected to the inputs of each OR gate The output of the OR gate goes to
an EX-OR gate where the other input can be programmed to receive a signal equal to
either logic 1 or 0

26
Programmable Logic Devices, Memory

The output is inverted when the EX-OR input is connected to 1 ie, (x †1= x’)
The output does not change when the EX-OR input is connected to 0 ie, (x †0= x)

2. Implement the combinational circuit with a PLA having 3 inputs,

4 product terms and 2 outputs for the functions
F1 (A, B, C) = ∑m (3, 5, 6, 7)

F2 (A, B, C) = ∑m (0, 2, 4, 7)

Solution:

Step 1: Truth table for the given functions

A B C F1 F2
0 0 0 0 1
0 0 1 0 0
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

Step 2: K-map Simplification

With this simplification, total number of product term is 6 But we require

only 4 product terms Therefore find out F1‘ and F2‘

27
Programmable Logic Devices, Memory

Now select, F1‘ and F2, the product terms are B’C’, A’C’, A’B’ and ABC
Step 3: PLA Program table
Inpu t
Prod uct s Outputs
term A B C F1 (C) F2 (T)
B‘C‘ 1 - 0 0 1 1
A‘C‘ 2 0 - 0 1 1
A‘B‘ 3 0 0 - 1 -
ABC 4 1 1 1 - 1

Step 4: PLA Diagram

28
Programmable Logic Devices, Memory

3. Implement the following functions using PLA

F1 (A, B, C) = ∑m (1, 2, 4, 6)

F2 (A, B, C) = ∑m (0, 1, 6, 7)

F3 (A, B, C) = ∑m (2, 6)

Solution:

Step 1: Truth table for the given functions

A B C F1 F2 F3
0 0 0 0 1 0
0 0 1 1 1 0
0 1 0 1 0 1
0 1 1 0 0 0
1 0 0 1 0 0
1 0 1 0 0 0
1 1 0 1 1 1
1 1 1 0 1 0

Step 2: K-map Simplification

29
Programmable Logic Devices, Memory

Step 3: PLA Program table

Inpu t
Prod uct s O utpu ts
term A B C F1 (T) F2 (T) F3 (T)
A‘B‘C 1 0 0 1 1 - -
AC‘ 2 1 - 0 1 - -
BC‘ 3 - 1 0 1 - 1
A‘B‘ 4 0 0 - - 1 -
AB 5 1 1 - - 1 -

Step 4: PLA Diagram

4. A combinational circuit is designed by the

function F1 (A, B, C) = ∑m (3, 5, 7)
F2 (A, B, C) = ∑m (4, 5, 7)

30
Programmable Logic Devices, Memory

Solution:
Step 1: Truth table for the given functions

A B C F1 F2
0 0 0 0 0
0 0 1 0 0
0 1 0 0 0
0 1 1 1 0
1 0 0 0 1
1 0 1 1 1
1 1 0 0 0
1 1 1 1 1
Step 2: K-map Simplification

Step 3: PLA Program table

Input
Product s Outputs
term A B C F1 (C) F2 (T)
AC 1 1 - 1 1 1
BC 2 - 1 1 1 -
AB‘ 3 1 0 - - 1

Step 4: PLA Diagram

31
Programmable Logic Devices, Memory

5. A combinational circuit is defined by the

functions, F1 (A, B, C) = ∑m (1, 3, 5) F2
(A, B, C) = ∑m (5, 6, 7)
Implement the circuit with a PLA having 3 inputs, 3 product terms
and 2 outputs
Solution:
Step 1: Truth table for the given functions

A B C F1 F2

0 0 0 0 0
0 0 1 1 0
0 1 0 0 0
0 1 1 1 0
1 0 0 0 0
1 0 1 1 1
1 1 0 0 1
1 1 1 0 1

32
Programmable Logic Devices, Memory

Step 2: K-map Simplification

With this simplification, total number of product term is 5 But we require only 3
product terms Therefore find out F1‘ and F2‘

Now select, F1‘ and F2, the product terms are AC, AB and C’
Step 3: PLA Program table
Inpu t
Prod uct s Outputs
term A B C F1 (C) F2 (T)
AB 1 1 1 - 1 1
C‘ 2 - - 0 1 -
AC 3 1 - 1 - 1

Step 4: PLA Diagram

33
Programmable Logic Devices, Memory

6. A combinational circuit is defined by the

functions, F1 (A, B, C) = ∑m (0, 1, 3,
4)
F2 (A, B, C) = ∑m (1, 2, 3, 4, 5)
Implement the circuit with a PLA having 3 inputs, 4 product terms and
2 outputs
Solution:
Step 1: Truth table for the given functions

A B C F1 F2
0 0 0 1 0
0 0 1 1 1
0 1 0 0 1
0 1 1 1 1
1 0 0 1 1
1 0 1 0 1
1 1 0 0 0
1 1 1 0 0

34
Programmable Logic Devices, Memory

Step 2: K-map Simplification

The product terms are B’C’, A’C, AB’ and A’B

Step 3: PLA Program table
Inpu
t
Prod uct s Outputs
term
A B C F1 (T) F2 (T)
B‘C‘ 1 - 0 0 1 -
A‘C 2 0 - 1 1 1
AB‘ 3 1 0 - - 1
A‘B 4 0 1 - - 1

Step 4: PLA Diagram

35
Programmable Logic Devices, Memory

7. A combinational logic circuit is defined by the function,

F (A, B, C, D) = ∑m (3, 4, 5, 7, 10, 14, 15)
G (A, B, C, D) = ∑m (1, 5, 7, 11, 15)
Implement the circuit with a PLA having 4 inputs, 6 product terms and 2 outputs

Solution:

Step 1: Truth table for the given functions

A B C D F G
0 0 0 0 0 0
0 0 0 1 0 1
0 0 1 0 0 0
0 0 1 1 1 0
0 1 0 0 1 0
0 1 0 1 1 1
0 1 1 0 0 0
0 1 1 1 1 1
1 0 0 0 0 0
1 0 0 1 0 0
1 0 1 0 1 0
1 0 1 1 0 1
1 1 0 0 0 0
1 1 0 1 0 0
1 1 1 0 1 0
1 1 1 1 1 1

Step 2: K-map Simplification

36
Programmable Logic Devices, Memory

The product terms are A‘BC‘, A‘CD, BCD, ACD‘, A‘C‘D, ACD

Step 3: PLA Program table

Product Inputs Outputs
term A B C D F (T) G (T)
A‘BC‘ 1 0 1 0 - 1 -
A‘CD 2 0 - 1 1 1 -
BCD 3 - 1 1 1 1 1
ACD‘ 4 1 - 1 0 1 -
A‘C‘D 5 0 - 0 1 - 1
ACD 6 1 - 1 1 - 1

Step 4: PLA Diagram

37
Programmable Logic Devices, Memory

8 Design a BCD to Excess-3 code converter and implement using suitable PLA

Solution:
Step 1: Truth table of BCD to Excess-3 converter is shown below,
BCD code Excess-3 code
Decima l
B3 B2 B1 B0 E3 E2 E1 E0
0 0 0 0 0 0 0 1 1
1 0 0 0 1 0 1 0 0
2 0 0 1 0 0 1 0 1
3 0 0 1 1 0 1 1 0
4 0 1 0 0 0 1 1 1
5 0 1 0 1 1 0 0 0
6 0 1 1 0 1 0 0 1
7 0 1 1 1 1 0 1 0
8 1 0 0 0 1 0 1 1
9 1 0 0 1 1 1 0 0
Step 2: K-map Simplification

The product terms are B3, B2B0, B2B1, B2B1’B0’, B2’B0, B2’B1, B1’B0’, B1B0, B0’

38
Programmable Logic Devices, Memory

Step 3: PLA Program table

Prod uct Inputs Outputs
terms B3 B2 B1 B0 E3 (T) E2 (T) E1 (T) E0 (T )

B3 1 1 - - - 1 - - -
B2B0 2 - 1 - 1 1 - - -
B2B1
3 - 1 1 - 1 - - -
B2B1‘B0‘
4 - 1 0 0 - 1 - -
B2‘B0
5 - 0 - 1 - 1 - -
B2‘B1
6 - 0 1 - - 1 - -
B1‘B 0‘
7 - - 0 0 - - 1 -
B1B0
8 - - 1 1 - - 1 -
B0‘
9 - - - 0 - - - 1

Step 4: PLA Diagram

39
Comparison between PROM, PLA, and PAL:

SNo PROM PLA PAL

AND array is fixed Both AND and OR OR array is fixed and
1 and OR array is arrays are AND array is
programmable programmable programmable
Cheaper and simpler
2 Costliest and complex Cheaper and simpler
to use

AND array can be AND array can be

All minterms are
3 programmed to get programmed to get
decoded
desired minterms desired minterms
Only Boolean
Any Boolean
functions in standard Any Boolean functions
functions in SOP form
4 SOP form can be in SOP form can be
can be implemented
implemented using implemented using PLA
using PLA
PROM

40