Course Title: Microcontrollers Course Code: BEC405A

SEM: IV Credits: 03 L:T:P:S = 3:0:0:x

Module – 2 Notes
Prepared By: Malashree G ,HOD, Department of E&C,Dr.SMCE

Module – 2: Instruction set

Syllabus:
Instruction Set: 8051 Addressing Modes, Data Transfer Instructions, Arithmetic instructions, Logical
instructions, Jump & Call Instructions Stack & Subroutine Instructions of 8051 (with examples in assembly
Language).
Reference: Textbook 2- Chapter 5,6,7,8, Additional reading Refer Textbook 3, Chapter 3 for complete
understanding of instructions with examples

E-1: Introduction to 8051 assembly programming: [Additional topic for extended learning]
Machine language:
The CPU can understand and work only on binary digits and it can do so at a very high speed. In the early
days of the computer, programmers coded programs in machine language which consists of 0s & 1s.
Although the hexadecimal system was used as a more efficient way to represent binary numbers, the process
of working in machine code was still cumbersome for humans.
Assembly language (Low-level language):
Complexity in machine language programming, eventually, led to the development of Assembly Language
that provided mnemonics for the machine code instructions, plus other features that made programming
faster and less prone to error. The term mnemonic refer to codes and abbreviations that are relatively easy to
remember. Assembly language programs must be translated into machine code by a program called an
assembler. Assembly language is referred to as a low-level language because it deals directly with the
internal structure of the CPU. To program in Assembly language, the programmer must know all the
registers of the CPU and the size of each, as well as other details.
High-Level language:
The languages such as BASIC, Pascal, C, C++, Java, and numerous others are called high-level languages
because the programmer does not have to be concerned with the internal details of the CPU: Whereas an
assembler is used to translate an Assembly language program into machine code (sometimes also called
object code or opcode for operation code), high-level languages are translated into machine code by a
program called a compiler.
Structure of Assembly language:
An Assembly language program consists of, among other things, a series of lines of Assembly language
instructions.
An Assembly language instruction consists of four fields:
[label:] mnemonic [operands] [; comment]

Brackets indicate that a field is optional, and not all lines have them. Brackets should not be typed in.
Regarding the above format, the following points should be noted. .

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1. The label field allows the program to refer to a line of code by name. The label field cannot exceed a
certain number of characters. Check the assembler for the rule.
2. The Assembly language mnemonic (instruction) and operand(s) fields together perform the real work of
the program and accomplish the tasks for which the program was written.
3. The comment field begins with a semicolon comment indicator ";". Comments may be at the end of a line
or on a line by themselves. The assembler ignores comments, but they are indispensable to programmers.
Although comments are optional, it is recommended that they be used to describe the program and make it
easier for someone else to read and understand, or for the programmer to remember what they wrote.
4. Any label referring to an instruction must be followed by a colon symbol, ":".
Sample of an Assembly Language Program
ORG 0H ; start (origin) at location 0
MOV R5, #25H ; load 25H into R5
MOV R7, #34H ; load 34H into R7
MOV A, #0 ; load 0 into A
ADD A, R5 ; add contents of R5 to A, now A = A + R5
ADD A, R7 ; add contents of R7 to A, now A = A + R7
ADD A, # 12H ; add to A value 12H, now A = A + 12H
Here: SJMP HERE ; stay in this loop
END ; end of asm source file
A given Assembly language program is a series of statements, or lines; which are either assembly language
instructions such as ADD and MOV, or statements called directives.
While instructions tell the CPU what to do, directives (also called pseudo-instructions) give directions to the
assembler. For example, in the above program while the MOV and ADD instructions are commands to the
CPU, ORG and END are directives to the assembler. ORG tells the assembler to place the opcode at memory
location 0 while END indicates to the assembler the end of the source code. In other words, one is for the
start of the program and the other one for the end of the program.
Assembling and Running an 8051 program:
The steps to create an executable Assembly language program are outlined as follows as shown in fig. 1:
1. An Editor program is used to type a assembly program. Many excellent editors or word processors are
available that can be used to create and/or edit the program. A widely used editor is the MS-DOS EDIT
program (or Notepad in Windows), which comes with all Microsoft operating systems. The editor must be
able to produce an ASCII file. For many assemblers, the file names follow the usual DOS conventions,
but the source file has the extension "asm" or "src", depending on the assembler.
2. The" asm" source file containing the program code created in step 1 is fed to an 8051 assembler. The
assembler converts the instructions into machine code. The assembler will produce an object file and a list
file. The extension for the object file is "obj" while the extension for the list file is "lst".
3. Assemblers require a third step called linking. The link program takes one or more object files and
produces an absolute object file with the extension "abs". This abs file is used by 8051 trainers that have a
monitor program. The list file is as shown below.

1. 0000 ORG 0H ; star (origin) at 0

2. 0000 7D 25 MOV R5, #25H ; load 25 into R5
3. 0002 7F 34 MOV R7, #34H ;Load 34H into R7

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 4. 0004 74 00 MOV A, #0 ; load 0 into A
; add contents of R5 to A ; now A = A +
5. 0006 2D ADD A, R5
R5
; add contents of R57to A; now A = A +
6. 0007 2F ADD A, R7
R7
7. 0008 24 12 ADD A, #12H ; add to A value 12H ; now A = A+12H
8. 000A 80 0A HERE: SJMP HERE ; stay in this loop
9. 000C END ; end of asm source file

List file: The list file, which is optional, is very useful to the programmer because it lists all the opcodes
and addresses as well as errors that the assembler detected. Many assemblers assume that the list file is
not wanted unless you indicate that you want to produce it. This file can be accessed by an editor such as
DOS EDIT and displayed on the monitor or to the printer to produce a hard copy. The programmer uses
the list file to find syntax errors. It is only after fixing all the errors indicated in the list file that the obj file
is ready to be input to the linker program.
4. The "abs" file is fed into a program called "OH" (object to hex converter), which creates a file with
extension "hex" that is ready to burn into ROM. 'This program comes with all 8051 assemblers. Recent
Windows-based assemblers combine steps 2 through 4 into one step.

Fig. 1: Assembly language programming process

8051 Data types and Directives:
The 8051 Microcontroller has only one data type. It is 8 bits, and the size of each register is also 8 bits. It is
the job of the programmer to break down data larger than 8 bits (00 to FFH, or 0 to 255 in decimal) to be
processed by the CPU.
DB (define byte):
The DB directive is the most widely used data directive in the assembler. It is used to define the 8-bit data.
When DB is used to define data, the numbers can be in decimal, binary, hex, or ASCII formats. For decimal,

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the "D" after the decimal number is optional but using "B" (binary) and "H" (hexadecimal) for the others is
required. Regardless of which is used, the assembler will convert the numbers into hex. To indicate ASCII,
simply place the characters in quotation marks ('like this'). The assembler will assign the ASCII code for the
numbers or characters automatically. The DB directive is the only directive that can be used to define ASCII
strings larger than two characters; therefore, it should be used for all ASCII data definitions. DB is also used
to allocate memory in byte-sized chunks.
Following are some DB examples:
Either single or double quotes can be used around ASCII strings.
ORG 500H
DATA1: DB 28 ; DECIMAL (1C in hex)
DATA2: DB 00110101B ; BINARY (35 in hex)
DATA3: DB 39H ; HEX
ORG 510H
DATA4: DB “2591” ; ASCII NUMBERS
ORG 518H
DATA6: DB “I Love my culture” ; ASCII CHARACTERS

Assembler directives:
The following are some more widely used directives of the 8051.
ORG (origin):
The ORG directive is used to indicate the beginning of the address. The number that comes after ORG can be
either in hex or in decimal. If the number is not followed by H, it is decimal, and the assembler will convert it
to hex. Based on the assembler “. ORG” or “ORG” notation is used.
Ex: ORG 500h
EQU (equate):
This is used to define a constant without occupying a memory location. The EQU directive does not set aside
storage for a data item but associates a constant value with a data label so that when the label appears in the
program, its constant value will be substituted for the label. The following uses EQU for the counter constant
and then the constant is used to load the R3 register.
Ex: COUNT EQU 25
... ....
MOV R3, #COUNT
Advantage of using EQU?
Assume that there is a constant (a fixed value) used in many different places in the program, and the
programmer wants to change its value throughout. By the use of EQU, the programmer can change it once
and the assembler will change all of its occurrences, rather than search the entire program trying to find every
occurrence.
END:
This indicates to the assembler the end of the source (asm) file. The END directive is the last line of an 8051
program, meaning that in the source code anything after the END directive is ignored by the assembler.
Some assemblers use “. END” instead of “END”.

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Rules for labels in Assembly language:
• Each label name must be unique.
• The names used for labels in Assembly language programming consist of alphabetic letters in both
uppercase and lowercase, the digits 0 through 9, and the special characters question mark (?), period (.), at
(@), underline (_), and dollar sign ($).
• The first character of the label must be an alphabetic character, it cannot be a number.
• Every assembler has some reserved words that must not be used as labels in the program. Foremost
among the reserved words are the mnemonics for the instructions.

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2.1 8051 Addressing modes:
The method of specifying the operands in the instructions is called addressing mode.
Or
The method of supplying the data for the instruction’s operation is called addressing mode.

Sl. Addressing Description

Example
No. mode
Data Memory Addressing modes
In immediate addressing mode, an 8-bit/16-bit immediate data or
Immediate
constant is specified in the instruction itself. The immediate data is i) MOV R0, #25h
1. addressing
represented by using symbol # along with data. ii) ADD A, #0EFh
mode
Destination operand can’t be immediate
Register The name of the register in which the data is available is specified
i) MOV A, R0
2. addressing in the instruction.
ii) SUB A, R1
mode
Direct The address of the data is directly specified in the instruction. The
i) MOV R2, 50h
3. addressing direct address can be the address of an internal data RAM location
ii) AND A, 75h
mode (00h to 7Fh) or the address of SFR (80h to FFh)
The address of the data (memory location) is specified through the
registers in the instruction. Only registers R1 & R0 are used for
Register i) MOV A, @R0
this purpose. The external RAM can be addressed indirectly
Indirect ii) OR A, @R1
4. through DPTR.
addressing iii) MOVX A,
The register which holds the address is called as data pointer & in
mode @DPTR
the instruction it is represented using @ symbol with the register
name.
Bit inherent The address of the bit operand is implied in the opcodes of the
5. i) CLR C
addressing mode instruction itself. This mode is used to operate on flags.
The address of the bit location is directly mentioned in the
Bit direct instruction. This mode is used to access & operate on bit i) SETB 05h
6.
addressing mode addressable area of internal RAM (20h to 2Fh) and bit addressable ii) MOV C, bit
SFRs.
Program memory addressing modes (refer to fig. 8 for the address ranges)
In relative addressing mode, the instruction specifies the address
Relative relative to the Program Counter (PC). The instruction will carry an a) JC offset
7.
addressing mode offset whose range is -128d to + 127d. The offset is added to the ii) SJMP L1
PC to generate the 16-bit physical address.
In 8051, this short absolute addressing mode assumes that AJMP L2
program memory is divided into a series of pages of 2K bytes
each, giving a total of 32d (20H) pages. The upper 5 bits of the
Program Counter (PC) hold the page number and the lower 11 bits
hold the address within each page. An absolute address is formed
Short absolute by taking the page no. of the instruction following the branch and
8.
addressing mode attaching the absolute page range address of 11 bits to it to form
the 16-bit address. The page description is as shown below:
Page
Hex address Binary address
no.
01 0000 – 07FFh 0000 0000 0000 0000 to
0000 0111 1111 1111

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 02 0800 – 0FFFh 0000 1000 0000 0000 to
0000 1111 1111 1111
03 1000 – 17FFh 0001 0000 0000 0000 to
0001 0111 1111 1111
04 1800 – 1FFFh 0001 1000 0000 0000 to
0001 1111 1111 1111
05 2000 – 2FFFh 0010 0000 0000 0000 to
0010 0111 1111 1111
-- -- --

-- -- --

32 F800 - FFFFh 1111 1000 0000 0000 to

1111 1111 1111 1111
Long absolute The entire program space from 0000h to FFFFh can be accessed.
9. LJMP L1
addressing mode
Indexed addressing mode is used to access data elements of look
up table entries located in the program ROM space of the 8051.
MOVC A,
Indexed In this mode, instruction MOVC is used and as operands the
10. @A+DPTR
addressing mode combination of PC & A or DPTR & A are used. PC/DPTR holds
MOVC A, @A+PC
the base address & A register holds the offset address. The sum of
base address & offset address gives the absolute 16-bit address.
11. Stack memory addressing mode PUSH & POP

Fig. 14: Branching instrution ranges

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2.2 Instruction set of 8051:
2.2.1 Data Transfer Instructions:
Data transfer instructions move (copy) one source operand to another destination operand. Source and
destination operands may be as shown in the below table:

Destination operand Source operand

Accumulator Immediate (8-bit/16-bit)
Register (Rn) Accumulator
Direct (data_addr) Register (Rn)
Indirect (@Ri or @DPTR) Direct (data_addr)
DPTR Indirect (@Ri or @DPTR)
Output ports Input ports
Note:
➢ The data transfers are not possible between
• Register (Rn) & Register (Rn)
• Indirect (@Ri) & Indirect (@Ri)
➢ Both the operands must be of same data type.
➢ All exchange instructions use Accumulator as one of the operands.
➢ One of the operands should be Accumulator for I/O transfers.
➢ No flags are affected on the execution of the data transfer instructions.

The various data transfer instructions available in 8051 are tabulated below:

Sl. Sl.
Instruction Operation Instruction Operation
No. No.
1. MOV A, Rn A  Rn 16. MOV DPTR, #imm16 DPTR  imm16
A  Rn
2. MOV A, data_addr A  [data_addr] 17. XCH A, Rn
Rn  A
A  [data_addr]
3. MOV A, @Ri A  [Ri] 18. XCH A, data_addr
[data_addr]  A
A  [Ri]
4. MOV A, #imm8 A  imm8 19. XCH A, @Ri
[Ri]  A
5. MOV Rn, A Rn  A 20. MOVX A, @Ri A  [Ri]
6. MOV Rn, data_addr Rn  [data_addr] 21. MOVX @Ri, A [Ri]  A
7. MOV Rn, #imm8 Rn  imm8 22. MOVX A, @DPTR A  [DPTR]
8. MOV data_addr, A [data_addr]  A 23. MOVX @DPTR, A [DPTR]  A
9. MOV data_addr, Rn [data_addr]  Rn 24. MOVC A, @A+PC A  [A+PC]
[data_addr]  MOVC A,
10. MOV data_addr, @Ri 25. A  [A+DPTR]
@Ri @A+DPTR

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 MOV data_addr, [data_addr]  SP  SP+1
11. 26. PUSH data_addr
#imm8 imm8 [SP]  [data_addr]
MOV data_addr, [data_addr]  [data_addr]  [SP]
12. 27. POP data_addr
data_addr [data_addr] SP SP-1
13. MOV @Ri, A [Ri]  A 28. MOV port, A Port  A
14. MOV @Ri, #data [Ri]  imm8 29. MOV A, Port A  Port
15. MOV @Ri, data_addr [Ri]  [data_addr]

External data moves:

It is possible to expand RAM & ROM memory space by adding external memory chips to the 8051
microcontrollers. The externa, memory can be as large as 64K for each of the RAM and ROM memory areas.
Opcodes that access this external memory always use indirect addressing to specify the external memory.

Fig. shows that registers R0, R1, and DPTR can be used to hold the address of the data byte in external
RAM. R0 & R1 are limited to external RAM address ranges of 00h to 0FFh, while the DPTR register can
address the maximum RAM space of 0000h to 0FFFFh.

Fig.: External addressing using MOVX & MOVC

NOTE:
i) All external data moves must involve the A register.
ii) Ri can address 256 bytes; DPTR can address 64K bytes.
iii) MOVX is normally used with external RAM or I/O addresses.
iv) Note that there are two sets of RAM addresses between 00h and 0FFh: one internal and one
external to the 8051.

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Code Memory Read-Only Data Moves:
There are times when the data must be permanent to be of repeated use and is stored in the program ROM
using assembler directives that store the programmed data anywhere in ROM that the programmer wishes.
Access to this data is made possible by using indirect addressing and the A register in conjunction with either
the PC or the DPTR as shown in fig. in both the cases, the number in register A is added to the pointing
register to form the address in ROM where the desired data is to be found. The data is then fetched from the
ROM address so formed and placed in the A register. The original data in A is lost, and the addressed data
takes its place.

Note:
i) The PC is incremented by 1 (to point to the next instruction) before it is added to A to form the final
address of the code byte.
ii) All data is moved from the code memory to the A register.
iii) MOVC is normally used with internal or external ROM and can address 4K of internal or 64K of
external code.

PUSH & POP Opcodes:

The PUSH and POP opcodes specify the direct address of the data. The data moves between an area of
internal RAM, known as the stack, and the specific address. The stack pointer special-function register (SP)
contains the address in RAM where data from the source address will be PUSHed, or where data to be
Popped to the destination address is found. The SP register actually is used in the indirect addressing mode
but is not named in the mnemonic. It is implied that the SP holds the indirect address whenever PUSHing or
Popping. Figure shows the operation of the stack pointer as data is PUSHed or Popped to the stack area in
internal RAM.

A PUSH opcode copies data from the source address to the stack. SP is incremented by 1 before the data is
copied to the internal RAM location contained in SP so that the data is stored from low addresses to high
addresses in the internal RAM. The stack grows up in memory as it is PUSHed. Excessive PUSHing can
make the stack exceed 7Fh (the top of internal RAM), after which the PUSHed data is lost.

A POP opcode copies data from the stack to the destination address. SP is decremented by 1 after data is
copied from the stack RAM address to the direct destination to ensure that data placed on the stack is
retrieved in the same order as it was stored.

Fig.: PUSH and POP the stack

The SP register is set to 07h when the 8051 is reset, which is the same direct address in internal RAM as
register R7 in bank 0. The first PUSH opcode would write data to R0 of bank 1. The SP should be initialized

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by the programmer to point to an internal RAM address above the highest address likely to be used by the
program.

NOTE:
i) When the SP reaches FFh it “rolls over” to 00h (R0).
ii) RAM ends at address 7Fh; PUSHes above 7Fh result in errors.
iii) The SP is usually set at addresses above the register banks.
iv) The SP may be PUSHed & POPed to the stack.
v) Note that direct addresses, not register names, must be used for R0-R7. The stack mnemonics have no
way of knowing which bank is in use.

2.2.2 Arithmetic Instructions:

The arithmetic group includes instructions for performing addition, subtraction, multiplication division,
decrement, and increment operation on the binary data.
➢ The result of most of the arithmetic operations is stored in the accumulator except a few decrement and
increment operations.
➢ The arithmetic instructions except increment and decrement modify the flags of 8051.
Sl.
Instruction Operation Source operands Flags affected
No.
1. ADD A, Src A  A + Src Imm8, Rn, data_addr, @Ri All status flags
2. ADDC A, Src A A+ Src + CF Imm8, Rn, data_addr, @Ri All status flags
3. SUBB A, Src A  A – Src – CF Imm8, Rn, data_addr, @Ri All status flags
A, Rn, data_addr, @Ri, No flags
4. INC dest destdest + 1
DPTR
A, Rn, data_addr, @Ri, No flags
5. DEC dest destdest – 1
DPTR
6. MUL AB B:A  A * B No other operands used OF = 1 when A*B >FFh
A  A/B (Q) No other operands used OF = 1 on division by 0
7. DIV AB
B  A%B (R)
i) If (A[LN]) >9 or AF=1; No other operands used No flags
A A+06h
8. DA A
ii) If (A[HN]) >9 or
CF=1; A A+60h

2.2.3 Logical Instructions:

The logical group include instructions for performing logical AND, OR and Exclusive – OR.
➢ The logical instructions do not modify the flags
➢ Results are stored in accumulator in most of the cases, except in few cases where it is stored in RAM

Sl.
Instruction Operation Source operands
No.
1. ANL A, Src A  A &Src Imm8, Rn, data_addr, @Ri

2. ANL data_addr, A [data_addr]  [data_addr] & A No other operands used

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 3. ANL data_addr, #imm8 [data_addr]  [data_addr] &imm8 No other operands used
4. ORL A, Src A  A ¦Src Imm8, Rn, data_addr, @Ri
5. ORL data_addr, A [data_addr]  [data_addr] ¦ A No other operands used
6. ORL data_addr, #imm8 [data_addr]  [data_addr] ¦ imm8 No other operands used
7. XRL A, Src A A^ Src Imm8, Rn, data_addr, @Ri
8. XRL data_addr, A [data_addr]  [data_addr] ^ A No other operands used
9. XRL data_addr, #imm8 [data_addr]  [data_addr] ^imm8 No other operands used

2.2.4 Program Flow Control Instructions

Normally a program is executed sequentially and the Program Counter (PC) keeps track of the
instructions and it is incremented appropriately after each fetch operation.
Program flow control can be achieved by using branching instructions like JUMP instructions which are
broadly classified into Unconditional branching instructions & Conditional branching instructions. CALL &
RET instructions defined for accessing subroutines also alters the program flow.
In unconditional branching instructions, the PC is loaded with the new address unconditionally. The
various forms of unconditional branching instructions and its operations are tabulated in the below table:
Sl.
Instruction Operation Remarks
No.
PC PC + 2 Short jump
1. SJMP code_offset
PCPC + code_offset 8-bit signed offset is used
Absolute jump
PC  PC + 2
2. AJMP code_addr11 11-bit address limiting to within 2KB
PC(10-0) code_addr11
page
3. LJMP code_addr16 PC code_addr16 Long jump, Entire 64 KB memory
4. JMP @A + DPTR PC code_addr16 (A + DPTR) Long jump, Entire 64 KB memory
i) PC PC + 2
ii) SP  SP + 1
Absolute jump
iii)[SP]  PCL
5. ACALL code_addr11 11-bit address limiting to within 2KB
iv) SP SP + 1
page
v) [SP] PCH
vi) PC(10-0) code_addr11
i) PC PC + 3
ii) SP  SP + 1
iii)[SP]  PCL
6. LCALL code_addr16 Long jump, Entire 64 KB memory
iv) SP SP + 1
v) [SP] PCH
vi) PC code_addr16
i) PCH [SP]
7. RET ii) SP SP – 1
iii) PCL [SP]

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 iv) SP SP – 1

Short jump instruction is to a relative address within -128 and + 127. Absolute jump instruction is to
direct 11-bit address in program memory. Long jump instruction is to direct 16-bit address in program
memory. Jump instruction is pointed by A + @DPTR.
Program flow control in a subroutine call is by absolute call or long call instruction. Absolute call
instruction is to call a specified direct 11-bit address at program memory. Long call instruction is to call a
specified direct 16-bit address directly at program memory. Return from a called routine is by RET
instruction and return from interrupt service routine is by RETI.
In conditional branching instructions, the content of the PC is modified, only if the condition specified in
the instruction is true.
➢ Only relative addressing mode (Short Jumps) is used.
➢ The conditional branching instructions are normally used immediately after the arithmetic/logical
operations so that branching can occur based on a condition specified.

The various forms of conditional branching instructions and its operations are tabulated in the below table:
Sl.
Instruction Operation Remarks
No.
i) PC PC + 2
ii) If (A = 0)
1. JZ code_offset Jump if result in A is zero
PCPC + code_offset
Else, Next instruction is executed
i) PC PC + 2
ii) If (A ≠ 0)
2. JNZ code_offset Jump if result in A is not zero
PCPC + code_offset
Else, Next instruction is executed
i) PC PC + 2
ii) If (CF = 0)
3. JC code_offset Jump if carry flag
PCPC + code_offset
Else, Next instruction is executed
i) PC PC + 2
ii) If (CF ≠ 0)
4. JNC code_offset Jump if no carry flag
PCPC + code_offset
Else, Next instruction is executed
i) PC PC + 3
ii) If ([bit_addr] = 1)
5. JB bit_addr, code_offset Jump if bit set
PCPC + code_offset
Else, Next instruction is executed
i) PC PC + 3
JNB bit_addr, ii) If ([bit_addr] ≠1) {i.e.
6. Jump if no bit
code_offset [bit_addr]=0}
PCPC + code_offset

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 Else, Next instruction is executed
Next instruction will be executed
i) PC PC + 3
ii) If ([bit_addr] =1)
JBC bit_addr,
7. PCPC + code_offset Jump if bit set & clear it
code_offset
[bit_addr]=0
Else, Next instruction is executed
Compare & jump if not equal
to
i) PC PC + 3
Other forms:
ii) If ( A ≠ [data_addr])
ii) CJNE A, #imm8,
CJNE A, data_addr, PCPC + code_offset
8. code_offset
code_offset Also, if A< [data_addr], CF = 1
iii) CJNE Rn, #imm8,
A > [data_addr], CF = 0
code_offset
Else, Next instruction is executed
iv) CJNE @Ri, #imm8,
code_offset
i) PC PC + 2
ii) Rn Rn – 1 Decrement & jump if not zero
9. DJNZ Rn, offset iii) If (Rn ≠ 0) ii) DJNZ data_addr,
PCPC + code_offset code_offset
Else, Next instruction is executed

2.2.5 Bit Manipulation Instructions

Each bit of certain SFRs and a 16-byte internal RAM (20h – 2Fh) are assigned bit addresses in 8051
hardware. There are bit manipulation instructions to clear, set, AND, OR, MOV the bit. Only the flags which
are acted upon will be affected.
Sl. Sl.
Instruction Operation Instruction Operation
No. No.
1. CLR C CF  0 7. ANL C, bit_addr CF  CF & [bit_addr]
2. CLR bit_addr [bit_addr]  0 8. ANL C, /bit_addr CF  CF & [~bit_addr]
3. SETB C CF  1 9. ORL C, bit_addr CF CF ! [bit_addr]
4. SETB bit_addr [bit_addr] 1 10. ORL C, /bit_addr CF CF ! [~bit_addr]
5. CPL C CF  ~CF 11. MOV C, bit_addr CF  [bit_addr]
6. CPL bit_addr [bit_addr]  [~bit_addr] 12. MOV bit_addr, C [bit_addr]  CF

2.2.6 Byte Manipulation Instructions

There are byte manipulation instructions to rotate right A, rotate left A, rotate right A with carry, rotate left
A with carry, complement A, clear A and swap with A lower and upper nibble (set of 4 bits). Various
instructions available in 8051 and their operations are tabulated below:
Sl. Flags affected
Instruction Operation
No.
1. CLR A A  00 No flags
2. CPL A A  ~A No flags

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3. RL A No flags

4. RR A No flags

5. RLC A CF

6. RRC A CF

7. SWAP A No flags

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Annexure: HEX codes of the instructions of 8051 microcontroller

No. of
Sl. No. of
Mnemonic Operands Hex Code Machine
No. Bytes
cycles
1. NOP 00 1 1
2. AJMP Addr11 01 2 2
3. LJMP Addr16 02 3 2
4. RR A 03 1 1
5. INC A 04 1 1
6. INC Data_ addr 05 2 1
7. INC @R0 06 1 1
8. INC @R1 07 1 1
9. INC R0 08 1 1
10. INC R1 09 1 1
11. INC R2 0A 1 1
12. INC R3 0B 1 1
13. INC R4 0C 1 1
14. INC R5 0D 1 1
15. INC R6 0E 1 1
16. INC R7 0F 1 1
17. JBC Bit_addr, code_addr 10 3 2
18. ACALL Code_addr 11 2 2
19. LCALL Code_addr 12 3 2
20. RRC A 13 1 1
21. DEC A 14 1 1
22. DEC Data_ addr 15 2 1
23. DEC @R0 16 1 1
24. DEC @R1 17 1 1
25. DEC R0 18 1 1
26. DEC R1 19 1 1
27. DEC R2 1A 1 1
28. DEC R3 1B 1 1
29. DEC R4 1C 1 1
30. DEC R5 1D 1 1
31. DEC R6 1E 1 1
32. DEC R7 1F 1 1
33. JB Bit_addr, Code_addr 20 3 2
34. AJMP Code_addr 21 2 2
35. RET 22 1 2
36. RL A 23 1 1
37. ADD A, #data 24 2 1
38. ADD A, data_addr 25 2 1
39. ADD A, @R0 26 1 1
40. ADD A, @R1 27 1 1
41. ADD A, R0 28 1 1
42. ADD A, R1 29 1 1
43. ADD A, R2 2A 1 1
44. ADD A, R3 2B 1 1
45. ADD A, R4 2C 1 1
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46. ADD A, R5 2D 1 1
47. ADD A, R6 2E 1 1
48. ADD A, R7 2F 1 1
49. JNB Bit_addr, code_addr 30 3 2
50. ACALL Code_addr 31 2 2
51. RETI 32 1 2
52. RLC A 33 1 1
53. ADDC A, #data 34 2 1
54. ADDC A, data_addr 35 2 1
55. ADDC A, @R0 36 1 1
56. ADDC A, @R1 37 1 1
57. ADDC A, R0 38 1 1
58. ADDC A, R1 39 1 1
59. ADDC A, R2 3A 1 1
60. ADDC A, R3 3B 1 1
61. ADDC A, R4 3C 1 1
62. ADDC A, R5 3D 1 1
63. ADDC A, R6 3E 1 1
64. ADDC A, R7 3F 1 1
65. JC Code_addr 40 2 2
66. AJMP Code_addr 41 2 2
67. ORL Data_addr, A 42 2 1
68. ORL Data_addr, #data 43 3 2
69. ORL A, #data 44 2 1
70. ORL A, data_addr 45 2 1
71. ORL A, @R0 46 1 1
72. ORL A, @R1 47 1 1
73. ORL A, R0 48 1 1
74. ORL A, R1 49 1 1
75. ORL A, R2 4A 1 1
76. ORL A, R3 4B 1 1
77. ORL A, R4 4C 1 1
78. ORL A, R5 4D 1 1
79. ORL A, R6 4E 1 1
80. ORL A, R7 4F 1 1
81. JNC Code_addr 50 2 2
82. ACALL Code_addr 51 2 2
83. ANL Data_addr, A 52 2 1
84. ANL Data_addr, #data 53 3 2
85. ANL A, #data 54 2 1
86. ANL A, data_addr 55 2 1
87. ANL A, @R0 56 1 1
88. ANL A, @R1 57 1 1
89. ANL A, R0 58 1 1
90. ANL A, R1 59 1 1
91. ANL A, R2 5A 1 1
92. ANL A, R3 5B 1 1
93. ANL A, R4 5C 1 1
94. ANL A, R5 5D 1 1

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95. ANL A, R6 5E 1 1
96. ANL A, R7 5F 1 1
97. JZ Code_addr 60 2 2
98. AJMP Code_addr 61 2 2
99. XRL Data_addr, A 62 2 1
100. XRL Data_addr, #data 63 3 2
101. XRL A, #data 64 2 1
102. XRL A, data_addr 65 2 1
103. XRL A, @R0 66 1 1
104. XRL A, @R1 67 1 1
105. XRL A, R0 68 1 1
106. XRL A, R1 69 1 1
107. XRL A, R2 6A 1 1
108. XRL A, R3 6B 1 1
109. XRL A, R4 6C 1 1
110. XRL A, R5 6D 1 1
111. XRL A, R6 6E 1 1
112. XRL A, R7 6F 1 1
113. JNZ Code_addr 70 2 2
114. ACALL Code_addr 71 2 2
115. ORL C, bit_addr 72 2 2
116. JMP @A+DPTR 73 1 2
117. MOV A, #data 74 2 1
118. MOV Data_addr, #data 75 3 2
119. MOV @R0, #data 76 2 1
120. MOV @R1, #data 77 2 1
121. MOV R0, #data 78 2 1
122. MOV R1, #data 79 2 1
123. MOV R2, #data 7A 2 1
124. MOV R3, #data 7B 2 1
125. MOV R4, #data 7C 2 1
126. MOV R5, #data 7D 2 1
127. MOV R6, #data 7E 2 1
128. MOV R7, #data 7F 2 1
129. SJMP Code_addr 80 2 2
130. AJMP Code_addr 81 2 2
131. ANL C, bit_addr 82 2 2
132. MOVC A, @A+PC 83 1 2
133. DIV AB 84 1 4
134. MOV Data_addr, data_addr 85 3 2
135. MOV Data_addr, @R0 86 2 2
136. MOV Data_addr, @R1 87 2 2
137. MOV Data_addr, R0 88 2 2
138. MOV Data_addr, R1 89 2 2
139. MOV Data_addr, R2 8A 2 2
140. MOV Data_addr, R3 8B 2 2
141. MOV data addr, R4 8C 2 2
142. MOV Data_addr, R5 8D 2 2
143. MOV Data_addr, R6 8E 2 2

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144. MOV Data_addr, R7 8F 2 2
145. MOV DPTR, #data 90 3 2
146. ACALL Code_ addr 91 2 2
147. MOV Bit_addr, C 92 2 2
148. MOVC A, @A+DPTR 93 1 2
149. SUBB A, #data 94 2 1
150. SUBB A, data_addr 95 2 1
151. SUBB A, @R0 96 1 1
152. SUBB A, @R1 97 1 1
153. SUBB A, R0 98 1 1
154. SUBB A, R1 99 1 1
155. SUBB A, R2 9A 1 1
156. SUBB A, R3 9B 1 1
157. SUBB A, R4 9C 1 1
158. SUBB A, R5 9D 1 1
159. SUBB A, R6 9E 1 1
160. SUBB A, R7 9F 1 1
161. ORL C, /bit_addr A0 2 2
162. AJMP Code_addr A1 2 2
163. MOV C, bit_addr A2 2 1
164. INC DPTR A3 1 2
165. MUL AB A4 1 4
166. reserved A5
167. MOV @R0, data_addr A6 2 2
168. MOV @R1, data_addr A7 2 2
169. MOV R0, data_addr A8 2 2
170. MOV R1, Data_addr A9 2 2
171. MOV R2, Data_addr AA 2 2
172. MOV R3, Data_addr AB 2 2
173. MOV R4, Data_addr AC 2 2
174. MOV R5, Data_addr AD 2 2
175. MOV R6, Data_addr AE 2 2
176. MOV R7, Data_addr AF 2 2
177. ANL C, /bit_addr B0 2 2
178. ACALL Code_addr B1 2 2
179. CPL Bit_addr B2 2 1
180. CPL C B3 1 1
181. CJNE A, #data, code addr B4 3 2
182. CJNE A, data_addr, code_addr B5 3 2
183. CJNE @R0, #data, code_addr B6 3 2
184. CJNE @R1, #data, code_addr B7 3 2
185. CJNE R0, #data, code_addr B8 3 2
186. CJNE R1, #data, code_addr B9 3 2
187. CJNE R2, #data, code_addr BA 3 2
188. CJNE R3, #data, code_addr BB 3 2
189. CJNE R4, #data, code_addr BC 3 2
190. CJNE R5, #data, code_addr BD 3 2
191. CJNE R6, #data, code_addr BE 3 2
192. CJNE R7, #data, code_addr BF 3 2

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193. PUSH Data_addr C0 2 2
194. AJMP Code_addr C1 2 2
195. CLR Bit_addr C2 2 1
196. CLR C C3 1 1
197. SWAP A C4 1 1
198. XCH A, data_addr C5 2 1
199. XCH A, @R0 C6 1 1
200. XCH A, @R1 C7 1 1
201. XCH A, R0 C8 1 1
202. XCH A, R1 C9 1 1
203. XCH A, R2 CA 1 1
204. XCH A, R3 CB 1 1
205. XCH A, R4 CC 1 1
206. XCH A, R5 CD 1 1
207. XCH A, R6 CE 1 1
208. XCH A, R7 CF 1 1
209. POP Data_addr D0 2 2
210. ACALL Code_addr D1 2 2
211. SETB Bit_addr D2 2 1
212. SETB C D3 1 1
213. DA A D4 1 1
214. DJNZ Data_addr, code_addr D5 3 2
215. XCHD A, @R0 D6 1 1
216. XCHD A, @R1 D7 1 1
217. DJNZ R0, code_addr D8 2 2
218. DJNZ R1, code_addr D9 2 2
219. DJNZ R2, code_addr DA 2 2
220. DJNZ R3, code_addr DB 2 2
221. DJNZ R4, code_addr DC 2 2
222. DJNZ R5, code_addr DD 2 2
223. DJNZ R6, code_addr DE 2 2
224. DJNZ R7, code_addr DF 2 2
225. MOVX A, @DPTR E0 1 2
226. AJMP Code_addr E1 2 2
227. MOVX A, @R0 E2 1 2
228. MOVX A, @R1 E3 1 2
229. CLR A E4 1 1
230. MOV A, data_addr E5 2 1
231. MOV A, @R0 E6 1 1
232. MOV A, @R1 E7 1 1
233. MOV A, R0 E8 1 1
234. MOV A, R1 E9 1 1
235. MOV A, R2 EA 1 1
236. MOV A, R3 EB 1 1
237. MOV A, R4 EC 1 1
238. MOV A, R5 ED 1 1
239. MOV A, R6 EE 1 1
240. MOV A, R7 EF 1 1
241. MOVX @DPTR, A F0 1 2

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242. ACALL Code_addr F1 2 2
243. MOVX @R0, A F2 1 2
244. MOVX @R1, A F3 1 2
245. CPL A F4 1 1
246. MOV Data_addr, A F5 2 1
247. MOV @R0, A F6 1 1
248. MOV @R1, A F7 1 1
249. MOV R0, A F8 1 1
250. MOV R1, A F9 1 1
251. MOV R2, A FA 1 1
252. MOV R3, A FB 1 1
253. MOV R4, A FC 1 1
254. MOV R5, A FD 1 1
255. MOV R6, A FE 1 1
256. MOV R7, A FF 1 1

Page 21 of 22
Review Questions for module 2:

1. What is the purpose of pseudo-instructions?

2. __________ are translated by the assembler into machine code, whereas _______ are not.
3. True or false. Assembly language is a high-level language.
4. Which of the following produces opcode?
(a) ADD A, R2 (b) MOV A,#12 (c) ORG 2000H (d) SJMP HERE
5. Pseudo-instructions are also called ________.
6. True or false. Assembler directives are not used by the CPU itself. They are simply a guide to the
assembler.
7. True or false. The DOS program EDIT produces an ASCII file
8. True or false. Generally, the extension of the source file is "asm" or "src".
9. Which of the following files can be produced by the DOS EDIT program?
(a) myprog.asm (b) myprog.obj (c) myprog.exe (d) myprog.1st
10. Which of the following files is produced by an 8051 assembler?
(a) myprog.asm (b) myprog.obj (c) myprog.hex (d) myprog.1st
11. Which of the following files lists syntax errors?
(a) myprog.asm (b) myprog.obj (c) myprog.hex (d) myprog.lst
12. The ________ directive is always used for ASCII strings.
13. How many bytes are used by the following?
DATA_1: DB “AMERICA”
14. What is the advantage in using the EQU directive to define a constant value?
15. How many bytes are set aside by each of the following directive?
(a) ASC_DATA: DB “1234” (b) MY_DATA: DB “ABC1234”
16. State the contents of memory locations 200H – 205H for the following:
ORG 200H
MYDATA: DB “ABC123”
17. There are a total of ____________ ports in the 8051 and each has _________bits.
18. True or false. All of the, 8051 ports can be used for both input and output.
19. Which 8051 ports need pull-up resistors to function as ail I/O port?
20. True or false. Upon power-up, the I/O pins are configured as output ports.
21. Show simple statements to send 99H to ports P1 and P2.

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