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AFSD-Assignment # 1 (22 Feb. 2025)

This document outlines an assignment for ECE-863: Advanced FPGA-based System Design, focusing on various tasks related to digital signal processing, robotic arm control, arithmetic unit design, smart home automation, and simulation control in Verilog HDL. Students are required to demonstrate their understanding of hierarchical modeling, modeling styles, logical vs. bitwise operators, and proper coding practices. The assignment emphasizes originality, as responses will be checked for plagiarism.

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Rehman Uz Zaman
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13 views2 pages

AFSD-Assignment # 1 (22 Feb. 2025)

This document outlines an assignment for ECE-863: Advanced FPGA-based System Design, focusing on various tasks related to digital signal processing, robotic arm control, arithmetic unit design, smart home automation, and simulation control in Verilog HDL. Students are required to demonstrate their understanding of hierarchical modeling, modeling styles, logical vs. bitwise operators, and proper coding practices. The assignment emphasizes originality, as responses will be checked for plagiarism.

Uploaded by

Rehman Uz Zaman
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Pak-Austria Fachhochschule: Institute of Applied Sciences and Technology

Department of Electrical and Computer Engineering


Assignment # 1
ECE-863: Advanced FPGA-based System Design Deadline: Feb. 28, 2025
Name: ___________ Registration No:___________ Marks: 50

Note: Show all the required steps while providing answers and don’t change the sequence of
questions. The similarity will be checked using Turnitin. If your response is found plagiarized, it
will be rejected.

1. Imagine you are part of a team tasked with designing a complex digital signal processor
(DSP) for an advanced audio processing application. The DSP needs to handle various
operations such as filtering, modulation, and demodulation of audio signals. Given the
complexity of the DSP and the need for modular design, your team decides to use
hierarchical modeling in Verilog HDL for the development process. As a designer, you are
required to explain hierarchical modeling by presenting a clear example. [10 marks]
2. Consider yourself member of a design team that has to design a digital system for an
advanced robotic arm. The robotic arm requires precise control over its movements, along
with feedback mechanisms for position sensing. As part of the design process, you need to
choose appropriate modeling styles in Verilog HDL to represent different components of
the robotic arm effectively. You need to implement the control logic for the robotic arm's
movement and integrate sensors for position feedback. First, explain the modeling styles,
and justify which modeling style in Verilog HDL would you choose for each of the
following components.
a. The main control unit that computes the desired angles for the robotic arm. [marks
5]
b. The combinational logic that processes sensor data to determinme the current
position of the arm. [marks 5]
c. The overall arrangement of different modules, including the control unit and the
sensors. [marks 5]
3. You are part of a team working on a digital design project to create a simple arithmetic unit
that will perform basic operations like addition, subtraction, AND, OR, and XOR. Your task
is to implement this unit using Verilog HDL, making use of both logical and bitwise
operators. During a team meeting, your lead developer asks you to explain the differences
between logical and bitwise operators, as well as their applications in the design. You need
to clarify these concepts to your team with suitable examples. [marks 10]
4. You are developing an automation system for a smart home system. The system controls
various objects like lights, heating, and security systems based on user preferences and

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conditions. One part of the application is responsible for managing the living room lighting.
The logic is designed to turn on the lights if someone is home and it is getting dark outside.
However, there is a missing part in the code that handles what happens when the condition
is not met.
Here is the relevant piece of code:

if (isSomeoneHome && isDarkOutside) begin

// Turn on the living room lights

turnOnLights();

// Additional actions like setting the light to warm color

end

// Missing 'else' or actions for 'else

What will happen if ‘else’ or ‘actions for else’ are missing. Further, you should complete
`else` clause to ensure the system behaves appropriately when no one is at home or when it
is not dark outside. [marks 10]
5. In the context of your digital design project in Verilog HDL, explain the purpose of
using $stop and $finish system tasks, and how do they differ in terms of controlling the
simulation flow. [marks 5]

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