4.

1 INTRODUCTION p and n-channel MOSFETs are employed

and are fabricated on the same silicon chip.
Digital ICs are a collection of resistors,
diodes, and transistors fabricated on a 4.2 CHARACTERISTICS OF DIGITAL IC
single piece of semiconductor material
(usually silicon) called a substrate, which is With the widespread use of ICs in digital
commonly referred to as a chip. systems and with the development of
various technologies for the fabrication of
4.1.1 BIPOLAR LOGIC FAMILIES ICs, it has become necessary to be familiar
The main elements of a bipolar IC are with the characteristics of IC logic families
resistors, diodes (which are also capacitors) and their relative advantages and
and transistors. Basically, there are two disadvantages. Digital ICs are classified
types of operations in bipolar ICs: either according to the complexity of the
1. Saturated circuit, as the relative number of individual
2. Non-saturated. basic gates (2-input NAND gates) it would
In saturated logic, the transistors in the IC require to build the circuit to accomplish
are driven to saturation, whereas in the the same logic function or the number of
case of non-saturated logic, the transistors components fabricated on the chip. The
are not driven into saturation. The saturated classification of digital ICs is given in the
bipolar logic families are: table:
1. Resistor–transistor logic (RTL) Classification of digital ICs
2. Direct–coupled transistor logic (DCTL), IC Classification Equivalent Number of
individual components
3. Integrated–injection logic ( 2 L) basic gates
4. Diode–transistor logic (DTL) Small-scale Less than 12 Up to 99
5. High–threshold logic (HTL) integration (SSI)
6. Transistor-transistor logic (TTL). Medium-scale 12-99 100-999
integration (MSI)
Large-scale 100-999 1,000-9,999
The non-saturated bipolar logic families integration(LSI)
are: Very large-scale Above 1,000 Above
1. Schottky TTL integration(VLSI) 10,000
2. Emitter-coupled logic (ECL).
The various characteristics of digital ICs
4.1.2 UNIPOLAR LOGIC FAMILIES used to compare their performances are:
1. Speed of operation (propagation delay)
MOS devices are unipolar devices and only 2. Power dissipation
MOSFETs are employed in MOS logic circuits. 3. Figure of merit
The MOS logic families are: 4. Fan-out
1. PMOS 5. Noise immunity
2. NMOS
3. CMOS 4.2.1 PROPAGATION DELAY
In PMOS only p-channel MOSFETs are used
and in NMOS only n-channel MOSFETs are The speed of a digital circuit is specified in
used, in complementary MOS (CMOS), both terms of the propagation delay time. The
input and output waveforms of a logic gate

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 are shown in Fig. The delay times are increase in the power dissipation and vice-
measured between the 50 percent voltage versa.
levels of input and output waveforms.
There are two delay times: t pHL , when the
output goes from the HIGH state to the
LOW state and tpLH , corresponding to the 4.2.4 FAN-OUT
output making a transition from the LOW
This is the number of similar gates which
state to the HIGH state. The propagation
can be driven by a gate. High fan-out is
delay time of the logic gate is taken as the
advantageous because it reduces the need
average of these two delay times.
for additional drivers to drive more gates.

4.2.5 NOISE IMMUNITY

The input and output voltage levels defined

The propagation delay of a logic gate is
above are shown in Fig.
t pHL t pLH
defined as: t pd
2

4.2.2 POWER DISSIPATION

This is the amount of power dissipated in

an IC. It is determined by the current, IC(avg) ,
that it draws from the Vcc supply, and is
given by VCC IC(avg) .This power is specified
VIH : This is the minimum input voltage
in milliwatts. which is recognized by the gate as
logic 1.
4.2.3 FIGURE OF MERIT VIL : This is the maximum input voltage
The figure of merit of a digital IC is defined which is recognized by the gate as
as the product of speed and power. The logic 0.
speed is specified in terms of propagation VOH : This is the minimum voltage available
delay time expressed in nanoseconds. at the output corresponding to logic 1.
VOL : This is the maximum voltage available
Figure of merit at the output corresponding to logic 0.
propagation delay time(ns) power(mW)
Note: The logic gates are not able to
It is specified in Pico joules. determine logic ‘1’ or logic ‘0’, if voltage lies
A low value of speed-power product is in the intermediate level. Stray electric and
desirable. In a digital circuit, if it is desired magnetic fields may induce unwanted
to have high speed, i.e. low propagation voltages, known as noise, on the connecting
delay, then there is a corresponding wires between logic circuits. This may
cause the voltage at the input to a logic

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 circuit to drop below VIH or rise above VIL
and may produce undesired operation. The
circuit’s ability to tolerate noise signals is
referred to as the noise immunity, a
quantitative measure of which is called
noise margin. The high-state noise margin
VNH is defined as
VNH V0H – VIH
For the operation discussed below, we
Any negative noise spike greater than VNH assume that the load gates are not present
appearing on the signal line may cause the and the voltages for logic 0 and 1 are
voltage to drop in the indeterminate range , VCE sat 0.2V and VCC 5V respectively.
where an unpredictable operation may
occur. The low-state noise margin VNL is Condition I: At least one input is LOW
defined as The emitter–base junction of T1
VNL VIL – VOL corresponding to the input in the LOW
state is forward-biased making voltage at
4.2.6 WIRED LOGIC CAPABILITY B1 , VB1 0.2 0.7 0.9V .For base–collector
junction of T1 to be forward-biased, and
Input Transistors Output for T2 and T3 to be conducting, B1 is
A B T1 T2 T3 Y required to be at least 0.6 + 0.5 + 0.5 = 1.6
0 0 Active Cut-off Cut-off 1 V. Hence, T2 and T3 are OFF.
0 1 Active Cut-off Cut-off 1
Since T3 is OFF, therefore Y VCC .
1 0 Active Cut-off Cut-off 1
Reverse
1 1 active Saturation Saturation 0 Condition II: All inputs are HIGH
The outputs can be connected together to
perform additional logic without any extra The emitter–base junctions of T1 are
hardware. reverse-biased. If we assume that T2 and
T3 are ON, then VB2 VC1 0.8 0.8 1.6V .
4.3 TRANSISTOR–TRANSISTOR LOGIC (TTL)
Since B1 is connected to VCC (5V) through
Transistor–transistor logic (TTL) is a
class of digital circuits built from bipolar R B1 , the collector-base junction of T1 is
junction transistors (BJT) and resistors. It forward-biased. The transistor T1 is
is called transistor logic because both the operating in the active inverse mode,
logic gating function (e.g., AND) and the
making IC1 flow in the reverse direction.
amplifying function are performed by
transistors. This current flows into the base of T2
driving T2 and T3 into saturation. Therefore,
4.3.1 Operation of TTL NAND Gate Y = 0.2 V.
Note: The speed of the circuit can be
improved by decreasing RC3 which
decreases the time constant R C3 C0
with which the output capacitance charges
from 0 to 1 logic level. Such a reduction,
however, would increase dissipation and

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 would make it more difficult for T3 to VC2 VB4 VBE3,sat VCE 2,sat
saturate. 0.8 0.2 1.0V
Since VO VCE3,sat 0.2V, the voltage
Inpu Transistors Out
t put across the base-emitter junction of T4
A B T1 T2 T3 T4 Y and diode D equals 1.0–0.2=0.8V, which
0 0 Active Cut- Cut- Saturati 1 means T4 and D are cut-off.
off off on b) If one of the inputs drops to LOW logic
0 1 Active Cut- Cutoff Saturati 1 level, T2 and T3 go to cut-off. The output
off on voltage cannot change instantaneously
1 0 Active Cut- Cut- Saturati 1
(being the voltage across Co) and
off off on because of T2 going to cut-off, the
1 1 Reverse Satura Satura Cut-off 0
voltage at the base of T4 rises driving it
Active tion tion to saturation.

4.3.3 WIRED-AND
4.3.2 Active Pull-up
When the output of TTL NAND gate is
connected together it works as if both the
outputs are applied to AND gate. Wired-
AND connection must not be used for
totem-pole output circuits because of the
current spike problem. TTL circuits with
open-collector outputs are available which
can be used for wired-AND connections.

4.3.4 OPEN COLLECTOR OUTPUT

In a circuit with open-collector output is
It is possible in TTL gates to hasten the
the collector resistor R C3 of T3 is missing.
charging of output capacitance without
corresponding increase in power The collector terminal C3 is available
dissipation with the help of an output outside the IC and the passive pull-up is to
circuit arrangement referred to as an be connected externally. Naturally, the
active pull-up or totem-pole output. advantages of active pull-up are not
available in this. Gates with open-collector
a) For output Y to be in LOW state, output can be used for wired -AND
transistor T4 and diode D are cut-off. operation.
When the output makes a transition
from LOW to HIGH corresponding to 4.3.5 UNCONNECTED INPUTS
any input going to LOW, transistor T4 If any input of a TTL gate is left
enters saturation and supplies current disconnected (open or floating) the
for the charging of the output capacitor corresponding E–B junction of T1 will not
with a small time constant. Diode D is be forward-biased. Hence, it acts exactly in
used in the circuit to keep T4 in cut-off the same way as if a logical 1 is applied to
that input. Therefore, in TTL ICs, all
when the output is at logic 0.
unconnected inputs are treated as logical
Corresponding to this, T2 and T3 are in 1s. However, the unused inputs should
saturation, therefore,

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 either be connected to some used input(s) VIH(min) 2 2 2 2 2 2
or returned to VCC through a resistor. VIL(max) 1 0.8 0.8 0.8 0.8 0.8
Noise Margin 0 0.3 0.3 0.3 0.3 0.3
4.3.6 CLAMPING DIODES

4.4 EMITTER-COUPLED LOGIC (ECL)

Emitter-coupled logic (ECL) is the fastest
of all logic families and therefore is used in
applications where very high speed is
essential. High speeds have become
possible in ECL because the transistors are
Clamping diodes are commonly used in all used in difference amplifier configuration,
TTL gates to suppress the ringing caused in which they are never driven into
from the fast voltage transitions found in saturation and thereby the storage time is
TTL. These diodes shown in Fig. clamp the eliminated. Here, rather than switching the
negative undershoot at approximately– transistors from ON to OFF and vice-versa,
0.7V. they are switched between cut-off and
active regions. Propagation delays of less
4.3.7 VARIOUS TTL SERIES than 1 ns per gate have become possible in
TTL Series Prefix Example IC ECL.
Standard TTL 74 7404(hex
INVERTER)
Schottky TTL 74S 74S04(hex
INVERTER)
Low-power 74LS 74LS04(hex
Schottky TTL INVERTER)
Advanced 74AS 74AS04(hex
Schottky TTL INVERTER)
Advanced low- 74ALS 74ALS04(hex
power Schottky INVERTER)
TTL

4.3.8 TTL SERIES CHARACTERISTICS

Performance 74 74S 74L 74 74ALS74F

ratings S AS Basically, ECL is realized using difference
Propagation 9 3 9.5 1.7 4 3 amplifier in which the emitters of the two
delay (ns)
Power 10 20 2 8 1.2 6
transistors are connected and hence it is
dissipation referred to as emitter-coupled logic. A 3-
(mW) input ECL gate is shown in Fig. above which
Speed-power 90 60 19 13. 4.8 18 has three parts:
product(pJ) 6 1. The middle part is the difference
Max.clock rate 35 125 45 200 70 100 amplifier which performs the logic
(MHz) operation.
Fan-out(same 10 20 20 40 20 33 2. Emitter follower are used for d.c. level
series) shifting of the outputs Note that two
Voltage
parameters
output Y1 and Y2 are available in this
VOH(min) 2 2.7 2.7 2.5 2.5 2.5 circuit which are complementary. Y1
corresponds to OR logic and Y2 to NOR
VOL(max) 0 0.5 0.5 0.5 0.5 0.5
logic and hence it is named as an
OR/NOR gate.

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 3. Additional transistors are used in
parallel to T1 to get the required fan-in.
There is a fundamental difference
between all other logic families
(including MOS logic) and ECL as far as
the supply voltage is concerned. In ECL,
the positive end of the supply is
connected to ground in contrast to
other logic families in which negative
end of the supply is grounded. This is
done to minimize the effect of noise
induced in the power supply and
protection of the gate from an 4.4.3 OPEN-EMITTER OUTPUT
accidental short circuit developing
between the output of a gate and Similar to open-collector output in TTL,
ground. The symbol of an ECL OR/NOR open-emitter outputs are available in ECL
gate is shown in Fig. which is useful for wired-OR applications.

4.4.4 UNCONNECTED INPUTS

4.4.1 FAN OUT
If any input of an ECL gate is left
If all the inputs are LOW, the input unconnected, the corresponding E-B
transistors are cut-off. Therefore the input junction of the input transistor will not be
resistance is very high. On the other hand, conducting. Hence it acts as if a logical 0
if an input is HIGH, the input resistance is level voltage is applied to that input.
that of an emitter follower which is also Therefore, in ECL ICs, all unconnected
high. Therefore, the input impedance is inputs are treated as logical 0s.
always high. The output resistance is either
that of an emitter follower or the forward 4.5 MOS LOGIC
resistance of a diode ( T3 or T4 act as a
diode) which is always low. Because of the MOSFETs have become very popular for
low output impedance and high input logic circuits due to high density of
impedance, the fan-out is large. fabrication and low power dissipation.
When MOS devices are used in logic
4.4.2 WIRED OR LOGIC circuits, there can be circuits in which
either only p or only n-channel devices are
The outputs of two or more ECL gates can used. Such circuits are referred to as PMOS
be connected to obtain additional logic and NMOS logic respectively.
without using additional hardware. The The basic MOS gate is an inverter as shown
wired-OR configurations are shown in Fig. in Fig. 4.25, in which T1 is an enhancement
MOSFET which acts as driver and T2 is an
enhancement MOSFET, which acts as load.

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 1. In the NOR gate if both inputs are 0,
both transistors T1 and T2 are OFF
I D1 =I D2 =0 hence the output is DD . If
either one or both of the inputs are V(1)
= VDD, the corresponding FETs will be
ON and the output is 0 V.
2. In the NAND gate if either one or both
the inputs are V(0) =0, the
corresponding FETs will be OFF, the
voltage across the load FET will be 0,
Instead of fabricating diffusion resistor for hence the output is VDD . If both inputs
load, which usually occupies an area about are V(1) = VDD, both T1and T2 are ON
20 times that of a MOS device, MOSFET and the output is 0
itself is used as the load. This makes
possible high density of fabrication and 4.6 CMOS LOGIC
therefore MOS logic made large scale
integration possible. A complementary MOSFET (CMOS) is
The logic levels for the MOS circuits are obtained by connecting a p-channel and an
n-channel MOSFET in series, with drains
V (0) =0 tied together and the output is taken at the
V (1) = DD common drain. Input is applied at the
Although the MOS logic circuits are common gate formed by connecting the
identical in configuration to bipolar DCTL, two gates together. In a CMOS, p-channel
the problem of current hogging is not and n-channel enhancement MOS devices
present. are fabricated on the same chip, which
4.5.1 MOSFET NAND and NOR Gates makes its fabrication more complicated
NOR gates can be obtained by using and reduces the packing density. But
multiple drivers in parallel, whereas for because of negligibly small power
NAND gates the drivers are to be connected consumption, CMOS is ideally suited for
in series. battery operated systems.

4.6.1 CMOS INVERTER

NOR Gate NAND Gate

Inputs Output Inputs Output
A B Y A B Y
0 0 VDD 0 0 VDD
0 VDD 0 0 VDD VDD The basic CMOS logic circuit is an inverter
VDD 0 0 VDD 0 VDD shown in Fig. For this circuit the logic levels
VDD VDD 0 VDD VDD 0 are 0 V (logic 0) and VDD (logic 1). When

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 VIN VDD , T1 turns ON and T2 turns OFF.
Therefore VO 0V , and since the
transistors are connected in series the
current ID is very small. On the other hand,
when VIN 0V , turns OFF and T2 turns ON
giving an output voltage. In either logic
state, T1 or T2 is OFF and the quiescent
power dissipation which is the product of
the OFF leakage current and is very low.

4.6.2 TRANSMISSION GATE

A CMOS transmission gate controlled by

gate voltages C and Cis shown in Fig.
Assume C = 1.
1) IA= V (1) f, then T1 is OFF and T2
conducts in the ohmic region because
there is no voltage applied at the drain.
Therefore, T2 behaves as a small
resistance connecting the output to the
input and B= A= V (1).
2) Similarly, if A= V (0), then T2 is OFF and
T1 conducts, connecting the output to
the input and B=A= V (0). This means
the signal is transmitted from A to B
when C = 1.
In a similar manner, it can be shown
that if C=0, transmission is not possible.
In this gate the control C is binary;
whereas the input at A may be either
digital or analog [the instantaneous
value must lie betweenV(0) andV(1)].

4.7 COMPARISON BETWEEN LOGIC

FAMILIES

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