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Rohini College of Engineering and Technology

Direct Memory Access (DMA) allows data transfer between external devices and main memory without continuous CPU intervention, enhancing efficiency. A DMA controller manages these transfers by handling memory addresses and bus signals, while the CPU can execute other tasks during the transfer. The operating system coordinates the DMA operations and manages program states during the process.

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0% found this document useful (0 votes)
8 views3 pages

Rohini College of Engineering and Technology

Direct Memory Access (DMA) allows data transfer between external devices and main memory without continuous CPU intervention, enhancing efficiency. A DMA controller manages these transfers by handling memory addresses and bus signals, while the CPU can execute other tasks during the transfer. The operating system coordinates the DMA operations and manages program states during the process.

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ROHINI COLLEGE OF ENGINEERING AND TECHNOLOGY

DIRECT MEMORY ACCESS (DMA)

A special control unit is provided to allow transfer of a block of data directly betweenan
external device and the main memory, without continuous intervention by the processor.
This approach is called direct memory access, or DMA.
(OR)

DMA stands for "Direct Memory Access" and is a method of transferring data from the
computer's RAM to another part of the computer without processing it using the CPU.
While most data that is input or output from your computer is processed by the CPU, some
data does not require processing, or can be processed by another device.
In these situations, DMA can save processing time and is a more efficient way to
move data from the computer's memory to other devices. In order for devicesto use direct
memory access, they must be assigned to a DMA channel. Each type ofport on a computer
has a set of DMA channels that can be assigned toeach connecteddevice.
 Transfer of data between a fast storage device and memory is limited by the speed
of CPU

 Remove CPU from the path of communication and the technique is DMA
DMA transfers are performed by a control circuit that is part of the I/O device interface.
We refer to this circuit as a DMA controller. The DMA controller performs the
functions that would normally be carried out by the processor whenaccessing the main
memory.
For each word transferred, it provides the memory address and all the bus signals
that control data transfer. Since it has to transfer blocks of data, the DMA
controller must increment the memory address for successive words andkeep track
of the number of transfers.
Although a DMA controller can transfer data without intervention by the processor, its
operation must be under the control of a program executed by the processor.
To initiate the transfer of a block of words, the processor sends the starting address,
the number of words in the block, and the direction of the transfer. On receiving this
information, the DMA controller proceeds to perform the requestedoperation. When the
entire block has been transferred, the controller informs theprocessor by raising an
interrupt signal.

CS3351-DIGITAL PRINCIPLES AND COMPUTER ORGANIZATION


ROHINI COLLEGE OF ENGINEERING AND TECHNOLOGY

While a DMA transfer is taking place, the program that requested the transfer cannot
continue, and the processor can be used to execute another program. Afterthe DMA
transfer is completed, the processor can return to the program that requested the
transfer. I/O operations are always performed by the operating system of the computer
in response to a request from an application program.

The OS is also responsible for suspending the execution of one program and starting
another. Thus, for an I/O operation involving DMA, the OS puts the program that
requested the transfer in the Blocked state initiates the DMA operation, and starts the
execution of another program. When the transfer is completed, the DMA controller
informs the processor by sending an interrupt request. In response, the OS puts the
suspended program in the runnable state sothat it can be selected by the scheduler to
continue execution.
Cycle Stealing –The DMA controller must use the bus only when the processordoes
not need it, or it must force the processor to suspend operation temporarily. This
technique is referred to as cycle stealing. It allows DMA controller to transfer one data
word at a time after which it must return control of the buses tothe CPU

DMA Controller

A simple DMA controller is a standard component in modern PCs, and many bus-
mastering I/O cards contain their own DMA hardware.
Handshaking between DMA controllers and their devices is accomplished through two
wires called the DMA-request and DMA-acknowledge wires.
While the DMA transfer is going on the CPU does not have access to the PCI bus(

CS3351-DIGITAL PRINCIPLES AND COMPUTER ORGANIZATION


ROHINI COLLEGE OF ENGINEERING AND TECHNOLOGY

including main memory ), but it does have access to its internal registers andprimary and
secondary caches.
DMA can be done in terms of either physical addresses or virtual addresses that are
mapped to physical addresses. The latter approach is known as DirectVirtualMemory
Access, DVMA, and allows direct data transfer from one memory- mapped device to
another without using the main memory chips.
The controller is integrated into the processor board and manages all DMA data transfers.
Transferring data between system memory and an I/O device requirestwo steps.
i. Data goes from the sending device to the DMA controller and then to the receiving
device. The microprocessor gives the DMA controller the location, destination, and
amount of data that is to be transferred. Then the DMA controller transfers the data,
allowing the microprocessor to continue with other processing tasks. When a
device needs to use the Micro Channel bus to
send or receive data, it competes with all the other devices that are trying to gain
control of the bus. This process is known as arbitration.
ii. The DMA controller does not arbitrate for control of the BUS instead; the I/Odevice
that is sending or receiving data (the DMA slave) participates in arbitration.
DMA controller takes over the buses to manage the transfer directly betweenthe
I/O device and memory
Bus Request (BR) –used by the DMA controller to request the CPU to claim orgive
up control of the buses.
CPU activates bus grant to inform the external DMA that the buses are in high
impedance state.
Burst transfer –block sequence consisting of memory words is transferred in a
continuous bus when DMA controller is the master.

CS3351-DIGITAL PRINCIPLES AND COMPUTER ORGANIZATION

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