EXCEL ENGINEERING COLLEGE

(Autonomous)
Department of Computer science and Engineering
IIISemester
20CS303- COMPUTER ARCHITECTURE AND ORGANIZATON
QuestionBank
UNIT 5-MEMORY SYSTEM MEMORY AND I/O SYSTEMS
PART-A

Q.No Questions
1 Give the classification of the Optical Media.
 Optical media can be classified as
 CD-ROM – Compact Disk Read Only Memory
 WORM – Write Once Read Many
 Rewriteable - Erasable
 Multifunction – WORM and Erasable

2 Define a Mini Disk.

Minidisk for data (MD-Data) is the data version of the new rewriteable storage format
developed by Sony Corporation for both business and entertainment as a convenient medium for
carrying music, video and data. MD can be used in three formats to support all potential uses as
follows:
 A premastered optical disk.
 A recordable magneto-optical disk.
 A hybrid that is partially mastered and partially recordable.

3
List some applications for WORM.
 Some of the application or WORM devices are
 On-Line catalogs such as automobile party’s dealer
 Large Volume Distribution
 Transaction logging such as stock trading company
 Multimedia Archival
4 Recall the multifunctional drives.
A multifunctional drive is a single unit which is capable of reading and writing a variety
of disk media. This type of drive provides the permanence of a read-only device as well as full
flexibility of a rewriteable device along with the powerful intermediate write once capability.

5 Name the types of technology used in multifunctional drive.

Three types of technologies utilized for multifunctional drives are
*Magneto – Optical Disk for both rewriteable and WORM capability
*Magneto- Optical disk for rewriteable and dye polymer disk for WORM capability
*Phase change technology for both rewriteable and WORM capability
6
Recap the Migration and Archiving.
 The process of moving an object from one level in the storage hierarchy to another level in
that hierarchy is called migration. Migration of Objects to off-line media and removal of
these objects from on-line media is called archiving.
7 What is the use of High water marks in a cache?
 Cache design use a high-water mark and a low water mark to trigger cache management
operations. When the cache storage fills up to the high – water mark , the cache manager
starts creating more space in cache storage.
 Space is created by discarding objects that have not been modified and writing back those
object that have been modified.
8 Point out the various cache usages in a LAN –based system.
In a LAN – based system there can be as many as three stages of caches as follows
 Disk Cache or System memory cache
 Hard Disk cache for each object server
 Shared network cache for all object servers
9
List the multimedia applications uses caches.
Some Multimedia application areas where cache is extensively used are
 Multimedia Entertainment
 Education
 Office Systems
 Audio and video Mail
10 Retell virtual memory technique.
Techniques that automatically move program and data blocks into the physical memory when
they are required for execution are called virtual memory technique.
11 Recall the logical addresses.
The binary addresses that the processor issues for either instruction or data are called
logical addresses.
12 Define translation buffer.
 Most commercial virtual memory systems incorporate a mechanism that can avoid the bulk
of the main memory access called for by the virtual to physical addresses translation buffer.
This may be done with a cache memory called a translation buffer.
13 Point out Static RAM and Dynamic RAM.

 Static RAM is fast, but they come at high cost because their cells require several transistors.
Less expensive RAM can be implemented if simpler cells are used. However such cells do
not retain their state indefinitely, hence they are called Dynamic RAM.
14 Tell about asynchronies DRAM and synchronous RAM.
 The specialized memory controller circuit provides the necessary control signals, RAS and
CAS that govern the timing. The processor must take into account the delay in the response
of the memory. Such memories are referred to as asynchronous DRAMS. The DRAM whose
 operations are directly synchronized with a clock signal. Such Memories are known as
synchronous DRAM.
15 Expand SCSI.
Small computer system interface can be used for all kinds of devices including RAID storage subsystems
and optical disks for large- volume storage applications
16 List the two types of latencies associated with storage.
The latency associated with storage is divided into 2 categories
1. Seek Latencies which can be classified into Overlapped seek, Mid transfer seek and Elevator
seek
2. Rotational Latencies which can be reduced either by Zero latency read or Write and Interleave
factor.
17
Infer an interrupt.
An interrupt is an event that causes the execution of one program to be suspended and
another program to be executed.
18
What is an I/O channel?
An i/o channel is actually a special purpose processor, also called peripheral processor. The
main processor initiates a transfer by passing the required information in the input output channel.
19
Name some of the IO devices.
 Video terminals
 Video displays
 Alphanumeric displays
 Graphics displays
 Flat panel displays
 Printers
 Plotters
20 Recall DMA.
A special control unit may be provided to enable transfer a block of data directly between an external
device and memory without contiguous intervention by the CPU. This approach is called DMA
 PART-B

Q.No Questions
Write short note on Memory Hierarchy Levels.
The goal is to present the user with as much memory as is available in the cheapest technology, while
providing access at the speed offered by the fastest memory.

When we move away from the processor, the levels take progressively longer to access.
Data is copied between only two adjacent levels at a time.

The upper level—the one closer to the processor— is smaller and faster Fig. shows that the minimum unit
1 of information that can be either present or not present in the two-level hierarchy is called a block or a line.

Block (line): unit of copying May be multiple words / word / byte. If accessed data is present in upper level is
called as HIT. The hit rate, or hit ratio, is the fraction of memory accesses found in the upper level.

Hit ratio: hits/accesses

 If accessed data is absent in upper level is called as MISS. The lower level in the hierarchy is then
accessed to retrieve the block containing the requested data.
 The miss rate (1−hit rate) is the fraction of memory accesses not found in the upper level.

Miss ratio: misses/accesses

 Then accessed data supplied from upper level. Hit time is the time to access the upper level of the
memory hierarchy, which includes the time needed to determine whether the access is a hit or a miss.
 The miss penalty is the time to replace a block in the upper level with the corresponding block from the
lower level, plus the time to deliver this block to the processor.
 The hit time will be much smaller than the time to access the next level in the hierarchy (miss penalty),
which is the major component of the miss penalty.

2 Discuss types of mapping function.

 Direct mapping.
 Associative mapping.
 Set-associative mapping.
Direct Mapping

 Block j of the main memory maps to j modulo 128 of the cache. 0 maps to 0, 129 maps to Block 1,
129, 257 are stored in cache block 1 & so on.
 More than one memory block is mapped onto the same position in the cache.
 May lead to contention for cache blocks even if the cache is not full.
 Resolve the contention by allowing new block to replace the old block, leading to a trivial replacement
algorithm.
 Memory address is divided into three fields:
• Low order 4 bits determine one of the 16 words in a block.
• When a new block is brought into the cache, the next 7 bits determine
Which cache block this new block is placed in.
• High order 5 bits determine which of the possible 32 blocks is currently
Present in the cache. These are tag bits.
Simple to implement but not very flexible.

Associative mapping

 Main memory block can be placed into any cache position.

 Memory address is divided into two fields:
o Low order 4 bits identify the word within a block.
o High order 12 bits or tag bits identify a memory block when it is resident in the cache.
 Flexible, and uses cache space efficiently.
 Replacement algorithms can be used to replace an existing block in the cache when the cache is full.
 Cost is higher than direct-mapped cache because of the need to search all 128 patterns to determine
whether a given block is in the cache.
Set-Associative mapping

 Blocks of cache are grouped into sets. Mapping function allows a block of the main memory to reside
in any block of a specific set. Divide the cache into 64 sets, with two blocks per set. Memory block 0,
64, 128 etc. map to block 0, and they can occupy either of the two positions.
 Memory address is divided into three fields:
o 6 bit field determines the set number.
 o High order 6 bit fields are compared to the tag fields of the two blocks in a set.
 Set-associative mapping combination of direct and associative mapping. Number of blocks per set is a
design parameter.
• One extreme is to have all the blocks in one set, requiring no set bits (fully associative
mapping).
• Other extreme is to have one block per set, is the same as direct mapping.
 The number of blocks per set is decided according to the requirement of the application used.
 Cache that has k blocks per set is referred to as a k-way set associative cache.
 A control bit called valid bit must be provided for each block.
Advantage: less expensive.

3 Explain Virtual Memory

The main memory can act as a “cache” for the secondary storage this technique is called virtual memory.

Need for Virtual Memory

 To allow efficient and safe sharing of memory among multiple programs.

 Virtual memory role is to protect and ensuring that a program can only read and write the portions of
main memory that have been assigned to it
 Virtual memory implements the translation of a program’s address space to physical addresses. This
translation process enforces protection of a program’s address space

Protection

 A set of mechanisms for ensuring that multiple processes sharing the processor, memory, or I/O
devices cannot interfere, intentionally or unintentionally, with one another by reading or writing each
other’s data.
 It is also used to isolate OS process and user process.

User program

 Virtual memory allows a single user program to exceed the size of primary memory.
 Programmers divided programs into pieces and then identified the pieces that were mutually exclusive.
 User program control ensures that program never access overlays that are not loaded and these
overlays never exceed the allocated size of the memory.

Page, Page Fault, Address Translation

 A virtual memory block is called a page, and a virtual memory miss is called a page fault.
 The processor produces a virtual address, which is translated by a combination of hardware and soft
ware to a physical address, which intern can be used to access main memory. This process is called
address mapping or address translation.

Mapping from a virtual to a physical address

 Address Translation

 Virtual memory also simplifies loading the program for execution by providing relocation.
 This relocation allows us to load the program anywhere in main memory.
 All virtual memory systems uses relocation, the program is divided as a set of fixed-size blocks
(pages), it eliminates the need to find a contiguous block of memory for a program
 instead, the operating system need only find a sufficient number of pages in main memory.
 In virtual memory, the address is broken into a virtual page number and a page off set. (refer
previous diagram)
 The physical page number constitutes the upper portion of the physical address, while the page off
set, which is not changed, constitutes the lower portion.
 The number of bits in the page off set field determines the page size.
 A larger number of virtual pages than physical pages is essentially the concept to show unbounded
amount of virtual memory.
 Page fault leads to enormous miss penalty. (millions of clock cycles)

To Design a virtual memory system

1. 1. Pages should be large enough to reduce high access time. Sizes from 4 KiB to 16 KiB are typical
today (depends on computer types).
2. The primary technique used here is to allow fully associative placement of pages in memory.
3. Page faults can be handled in software because the overhead will be small compared to the disk access
time. (it reduces miss penalty)
4. Write-through will not work for virtual memory, since writes take too long. Instead, virtual memory
systems use write-back.

4 Explain about Translation-Look aside Buffer (TLB).

 Page tables are stored in main memory. Memory access by a program can take at least twice as long.

1. One memory access to obtain the physical Address

2. Second access to get the data.

 To improve performance, rely on locality of reference i.e., when a virtual page is translated, it will be
referenced again(due to temporal and spatial locality).
 So, special address translation cache is used and is traditionally referred to as a translation-lookaside
buffer (TLB) or translation cache
 TLB is accessed instead of the page table on every reference, the TLB will need to include other status
bits, such as the dirty and the reference bits
 When a miss in the TLB occurs, we must determine whether it is a page fault or merely a TLB miss.
 If the page exists in memory, then the TLB miss indicates only that the translation is missing, so the
processor can handle the TLB miss by loading the translation from the page table into the TLB.
 If the page is not present in memory, then the LB miss indicates a true page fault.

Details about TLB

1. TLB size: 16–512 entries

2. Block size: 1–2 page table entries (typically 4–8 bytes each)
3. Hit time: 0.5–1 clock cycle
4. Miss penalty: 10–100 clock
5. cycles Miss rate: 0.01%–1%
To obtain lower miss rate

• TLB uses small, fully associative mapping (lower miss rate).

Handling a TLB miss or a page fault requires using the exception mechanism to interrupt the active process,
transferring control to the operating system, and later resuming execution of the interrupted process.

5 Write short notes on I/O modules or I/O Organizations.

The computer system's input/output (I/O) architecture is its interface to the outside world. We have
discussed the two important modules of the computer system - The processor and The memory module.

The third key component of a computer system is a set of I/O modules. Each I/O module interfaces to
the system bus and controls one or more peripheral devices.

There are several reasons why an I/O device or peripheral device is not directly connected to the
system bus. Some of them are as follows -

 There are a wide variety of peripherals with various methods of operation. It would be impractical to
include the necessary logic within the processor to control several devices.
 The data transfer rate of peripherals is often much slower than that of the memory or processor. Thus,
it is impractical to use the high-speed system bus to communicate directly with a peripheral.
 Peripherals often use different data formats and word lengths than the computer to
which they are attached.
Thus, an I/O module is required.
Input / Output Modules

The major functions of an I/O module are categorized as follows –

 Control and timing

 Processor Communication
 Device Communication
 Data Buffering
 Error Detection

Control & timings: The I/O function includes a control and timing requirement to co-ordinate the
flow of traffic between internal resources and external devices. For example, the control of the transfer of data
from an external device to the processor might involve the following sequence of steps –

1. The processor interacts with the I/O module to check the status of the attached device.
2. The I/O module returns the device status.
3. If the device is operational and ready to transmit, the processor requests the transfer of data, by means
of a command to the I/O module.
4. The I/O module obtains a unit of data from external device.
5. The data are transferred from the I/O module to the processor.

If the system employs a bus, then each of the interactions between the processor and the I/O module
involves one or more bus arbitrations.
Processor & Device Communication

During the I/O operation, the I/O module must communicate with the processor and with the external
device. Processor communication involves the following -

Command decoding: The I/O module accepts command from the processor, typically sent as signals on
control bus.

Data : Data are exchanged between the processor and the I/O module over the data bus.

Status Reporting : Because peripherals are so slow, it is important to know the status of the I/O module. For
example, if an I/O module is asked to send data to the processor(read), it may not be ready to do so because it
 is still working on the previous I/O command. This fact can be reported with a status signal. Common status
signals are BUSY and READY.

Address Recognition : Just as each word of memory has an address, so thus each of the I/O devices. Thus an
I/O module must recognize one unique address for each peripheral it controls. On the other hand, the I/O must
be able to perform device communication. This communication involves command, status information and
data.

Data Buffering

An essential task of an I/O module is data buffering. The data buffering is required due to the
mismatch of the speed of CPU, memory and other peripheral devices. In general, the speed of CPU is
higher than the speed of the other peripheral devices. So, the I/O modules store the data in a data buffer and
regulate the transfer of data as per the speed of the devices.

In the opposite direction, data are buffered so as not to tie up the memory in a slow transfer
operation. Thus the I/O module must be able to operate at both device and memory speed.

Error Detection

Another task of I/O module is error detection and for subsequently reporting error to the processor.
One class or error includes mechanical and electrical malfunctions reported by the device (e.g. paper jam).
Another class consists of unintentional changes to the bit pattern as it is transmitted from devices to the I/O
module. Block diagram of I/O Module is shown in the Fig.

6 Write short notes on DMA.

 Programmed I/O and Interrupt-driven I/O methods require the active intervention of the processor to
transfer data between memory and the I/O module, and any data transfer must transverse a path
through the processor. Thus both these forms of I/O suffer from two inherent drawbacks.

 The I/O transfer rate is limited by the speed with which the processor can test and service a
device.
 The processor is tied up in managing an I/O transfer; a number of instructions must be executed for
each I/O transfer.

 To transfer large block of data at high speed, a special control unit may be provided to allow transfer
of a block of data directly between an external device and the main memory, without continuous
intervention by the processor. This approach is called direct memory access or DMA.

 DMA transfers are performed by a control circuit associated with the I/O device and this circuit is
 referred as DMA controller. The DMA controller allows direct data transfer between the device and
the main memory without involving the processor.

 To transfer data between memory and I/O devices, DMA controller takes over the control of the
system from the processor and transfer of data take place over the system bus.
 For this purpose, the DMA controller must use the bus only when the processor does not need it, or it
must force the processor to suspend operation temporarily.

 The later technique is more common and is referred to as cycle stealing, because the DMA module in
effect steals a bus cycle.
 The typical block diagram of a DMA controller is shown in the Figure. When the processor wishes to
read or write a block of data, it issues a command to the DMA module, by sending to the DMA
module the following information.

 Whether a read or write is requested, using the read or write control line between the processor and
the DMA module.
 The address of the I/O devise involved, communicated on the data lines.
 The starting location in the memory to read from or write to, communicated on data lines and stored
by the DMA module in its address register.
 The number of words to be read or written again communicated via the data lines and stored in the
data count register.

o The processor then continues with other works. It has delegated this I/O operation to the DMA
module. The DMA module checks the status of the I/O devise whose address is communicated
to DMA controller by the processor.
o If the specified I/O devise is ready for data transfer, then DMA module generates the DMA
request to the processor. Then the processor indicates the release of the system bus through
DMA acknowledge.

 The DMA module transfers the entire block of data, one word at a time, directly to or from memory,
without going through the processor.
 When the transfer is completed, the DMA module sends an interrupt signal to the processor. After
 receiving the interrupt signal, processor takes over the system bus. Thus the processor is involved only
at the beginning and end of the transfer. During that time the processor is suspended.
o It is not required to complete the current instruction to suspend the processor. The processor may
be suspended just after the completion of the current bus cycle.
o On the other hand, the processor can be suspended just before the need of the system bus by the
processor, because DMA controller is going to use the system bus, it will not use the processor.
The point where in the instruction cycle the processor may be suspended shown in the Fig..

o When the processor is suspended, then the DMA module transfer one word and return control
to the processor. Note that, this is not an interrupt; the processor does not save a context and do
something else. Rather, the processor pauses for one bus cycle.
o During that time processor may perform some other task which does not involve the system
bus. In the worst situation processor will wait for some time, till the DMA releases the bus.

o The net effect is that the processor will go slow. But the net effect is the enhancement of
performance, because for a multiple word I/O transfer, DMA is far more efficient than interrupt
driven or programmed I/O.

(Note:*Blooms Level (R – Remember, U – Understand, AP – Apply, AZ – Analyze, E – Evaluate, C –

Create)
PART A- Blooms Level : Remember, Understand, Apply
PART B- Blooms Level: Understand, Apply, Analyze, Evaluate(if possible)
Marks: 16 Marks, 8+8 Marks, 10+6 Marks)

SubjectIn-charge CourseCoordinator HOD IQAC

(Name&Signature) (Name&Signature)