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DFT - VLSI Tutorials

The document outlines a structured tutorial on Design for Testability (DFT) in VLSI, covering key topics such as fault models, scan techniques, on-chip clock control, LFSR concepts, and Logic Built-In Self-Test (LBIST). It includes detailed sections on clock architecture, test compression, and response analysis. The tutorial is designed to guide learners through essential DFT concepts in a sequential manner.

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Shamik Chakraborty
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102 views2 pages

DFT - VLSI Tutorials

The document outlines a structured tutorial on Design for Testability (DFT) in VLSI, covering key topics such as fault models, scan techniques, on-chip clock control, LFSR concepts, and Logic Built-In Self-Test (LBIST). It includes detailed sections on clock architecture, test compression, and response analysis. The tutorial is designed to guide learners through essential DFT concepts in a sequential manner.

Uploaded by

Shamik Chakraborty
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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22/02/2025, 17:05 DFT – VLSI Tutorials

VLSI Tutorials

DFT

I would suggest you to go through the topics in the sequence shown below –

1. DFT, Scan & ATPG


What is DFT
Fault models
Basics of Scan
2. How test clock is controlled for Scan Operation using On-chip Clock Controller.
Why do we need OCC
How test clock is controlled by OCC
Example of a simple OCC with its systemverilog code
3. How to define a clock architecture for Scan.
How to handle clock mux and clock divider
How to put OCC
4. LFSR and Ring generator concepts (to learn test compression)
Types of LFSR
How to transform a modular type LFSR to Ring generator
5. Logic Built in Self Test (LBIST)
Basics of LBIST
Test Pattern Generator
Phase shifter
How to find seed and degree of LFSR
And a separate page specifically for Response Analyzer(RA) of LBIST
Role of RA
Characteristics of good RA
Aliasing
Probability of Aliasing
LFSR based serial RA
CRC theory
LFSR based parallel RA (or MISR)

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22/02/2025, 17:05 DFT – VLSI Tutorials

Masking in MISR
6. Test compression which cover topics like –
Basics of test compression and EDT
EDT – Decompressor
EDT – Compactor

VLSI Tutorials / A WordPress.com Website.

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