REVIEW

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Graphene-Based Silicon Photonic Devices for Optical

Interconnects
Zheng Wang, Yan Cai, Haitao Jiang, Ziao Tian, and Zengfeng Di*

and reliable data links.[3] To meet the

The exponential growth of global data traffic is driven by the unprecedented requirements of next-generation high-
digitalization of the world. To meet the demands of next-generation capacity data communication systems, a
high-capacity data communication systems, innovative solutions are required. substantial increase in the complexity of op-
Silicon photonics has gained significant attention due to its ability to integrate tical interconnects will be necessary. Simply
adding more channels with discrete optical
multiple core functions of optical interconnects into small-scale chips,
components will hardly suffice. Integrated
offering cost-effective and scalable manufacturing capabilities. By leveraging solutions that can automatically meet
silicon photonics, it becomes possible to address the challenge of scaling critical alignment tolerances of subcompo-
system complexity while reducing size, cost, and energy consumption. nents are highly desired. The transparency
Despite its advantages, silicon has inherent limitations that restrict its and high refractive index contrast to sil-
icon dioxide (SiO2 ) enables low-loss and
application range, such as the weak plasma dispersion effect and relatively
high-confinement silicon waveguides,[4,5]
large bandgap. Recently, graphene has emerged as a promising solution for which makes silicon-on-insulator (SOI)
traditional silicon photonics because of its exceptional electrical and optical an ideal platform for high-density inte-
properties. For instance, graphene on a silicon chip enables nearly pure phase gration with compact silicon photonic
modulation and ultrafast photodetection beyond 500 GHz. Moreover, the devices.[6–9] More importantly, silicon pho-
demonstrated compatibility of graphene with wafer-level integration paves the tonic chips could be cost-effectively and
massively fabricated via complementary
way for mass production of graphene-based silicon photonic devices, offering
metal-oxide-semiconductor (CMOS) man-
improved yield, scalability, and cost-effectiveness. In this work, a ufacturing technology. Due to the presence
comprehensive review is provided, focusing on graphene-based silicon of well-established infrastructures and
photonic devices and their applications in optical interconnects, aiming to highly mature supply chains, silicon pho-
explore the potential of graphene in advancing silicon photonic technology. tonics has undergone rapid development
in the past decade.[10–12] Multiple core
functions of optical interconnect includ-
ing modulation,[1,13–15] detection,[16–21]
polarization manipulation,[22–26] and
1. Introduction multiplexing/de-multiplexing[27–32] could be simultaneously im-
In the past quarter of a century, with the unprecedented dig- plemented on a millimeter-scale silicon photonic chip.[12] Al-
italization of our world, the global data traffic has exponen- though the indirect band structure of silicon prevents an efficient
tially grown to the “Zettabyte Era” where the annual global data light emission, heterogeneous integration approaches such as
traffic is expected more than 2 zettabytes (1 zettabyte = 1021 wafer bonding[33–40] and micro-transfer printing[41–46] have been
bytes).[1] Conventional electrical interconnects are facing a grow- developed to offer on-chip semiconductor optical amplifiers and
ing challenge in fulfilling the ever-increasing demands of data- light sources. By leveraging the abovementioned advantages, sili-
intensive applications such as high-definition video streaming con photonics could provide promising solutions to optical inter-
and cloud computing due to their inherent limitations in band- connects by resolving the dilemma of scaling system complexity
width and power consumption.[2] Optical interconnects have while reducing the size, cost, and energy consumption. Various
been widely adopted to offer affordable solutions to high-capacity application-specific silicon photonic integrated circuits (PICs),
ranging from connections as far as between data centers[47] to
those as near as between central processing units (CPUs) and
Z. Wang, Y. Cai, H. Jiang, Z. Tian, Z. Di memories,[48] have been demonstrated.
National Key Laboratory of Materials for Integrated Circuits Although silicon photonics has been becoming the dominant
Shanghai Institute of Microsystem and Information Technology
Chinese Academy of Sciences solution to optical interconnects, its application is limited due
865 Changning Road, Shanghai 200050, China to inherent limitations including but not limited to high sen-
E-mail: [email protected] sitivity to fabrication, high thermo-optical (TO) coefficient, and
significant two-photon absorption (TPA) from silicon itself.[49–52]
The ORCID identification number(s) for the author(s) of this article These limitations restrict its usage in applications such as high-
can be found under https://doi.org/10.1002/adfm.202307461
performance wavelength division multiplexing (WDM)[53] and
DOI: 10.1002/adfm.202307461

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optical frequency combs.[54,55] Silicon nitride (SiN), which has A schematic of a graphene-based silicon photonic transceiver
been widely used in CMOS process as a passivation and sacrificial chip with WDMtechnologies is shown in Figure 1. At the trans-
material, has become an important supplement to SOI in silicon mitting end, multiple continuous-wave (CW) lasers serve as
photonics[56–60] in recent years. The ecosystem developed for the multi-wavelength sources. The light is modulated by input elec-
silicon photonics industry, including process-design kits (PDKs), trical signals through graphene-based electro-optic modulators.
packaging, and assembly, is fully compatible with SiN. The mod- Subsequently, the multi-wavelength optical signal is combined
erate index contrast and relatively low TO coefficient (≈13% of into a single optical channel via an optical multiplexer. After mul-
silicon)[58] of SiN enables the development of passive silicon pho- tiplexing, optical signals are coupled from the chip into an opti-
tonic devices with superior performance, such as ultra-low loss cal fiber and propagate within it. The propagation distance can
waveguides,[61–63] high coupling efficiency edge couplers,[64–66] vary from several hundred meters to tens of kilometers, depend-
ultra-high quality factor micro-ring resonators,[67–74] fabrication- ing on the specific application. Once the optical signals reach
tolerant and temperature-insensitive (de)multiplexers,[75–79] and the receiving end, they will first be demultiplexed and then con-
high-performance optical phased arrays.[80–83] Moreover, the neg- verted back into electrical signals through graphene-based pho-
ligible TPA of SiN makes it an ideal platform for handling todetectors. It is worth noting that the electrical signals obtained
high optical power, thereby paving the way for on-chip nonlin- from the photodetectors typically require post-processing for
ear optics.[84–86] For instance, by employing the hybrid integra- recovery.
tion of III–V reflective semiconductor optical amplifier (RSOA) In this paper, we present a comprehensive review of graphene-
via an edge-coupled approach[87] or the heterogeneous integra- based silicon photonic devices for their applications in optical
tion of III-V materials with wafer bonding techniques,[88,89] high- interconnects. In Section 2, the state-of-the-art silicon photonic
performance on-chip SiN-based optical frequency combs have device manufacturing will be reviewed. Section 3 will review the
been demonstrated. To address the increasing demand for SiN- graphene technology, encompassing the processes of synthesis,
based PICs, particularly driven by the need for high-performance transfer, and metallization. In Section 4, we will introduce the
optical phased arrays used in solid-state LiDARs, foundries are fundamentals of optical modulation, providing a comprehensive
actively integrating SiN into their existing silicon photonic pro- understanding of this key concept. Following that, we will delve
cesses by offering pilot line fabrication services.[90,91] into the topic of graphene-based silicon photonic modulators.
Nevertheless, the dielectric properties of SiN present signif- We will highlight their unique features and discuss their appli-
icant challenges in achieving high-speed active optoelectronic cations in optical interconnects, showcasing how graphene tech-
devices such as optical modulators and photodetectors using nology enhances their performance and efficiency. Similarly in
this material. To address this issue, a common solution is to Section 5, we will review graphene-based silicon photonic pho-
adopt a hybrid approach that combines SiN with silicon and ger- todetectors. Finally, a summary and outlook will be presented in
manium (Ge). However, it should be noted that silicon mod- Section 6.
ulators face difficulties in achieving low power consumption,
large bandwidths, and high modulation efficiencies simultane-
ously. On the other hand, Ge photodetectors require sophisti-
cated epitaxy and doping processes. Graphene, one of the most 2. Silicon Photonic Device Manufacturing: State of
prominent atomically thick two-dimensional materials, has gar- the Arts
nered tremendous interest in addressing the aforementioned
dilemma.[92,93] This is due to its extraordinary electrical and opti- Silicon photonics is widely regarded as the leading candidate for
cal properties, as well as its capacity for wafer-level integration.[94] integrated photonics among various materials due to its excep-
Graphene has a carrier mobility >100 000 cm2 v−1 s−1 at room tional electro-optical performance. It is a technology that holds
temperature[95–97] (compared to the ≈1400 cm2 v −1 s −1 of sili- great potential for applications such as high-performance com-
con) and an ultra-broadband optical absorption from visible to puting and optical communications. Moreover, it has quickly
THz wavelengths.[93] One of the key advantages of graphene is emerged as a vital technology, primarily because of its compati-
its ability to shift the Fermi level through electric gating.[98,99] bility with the standard CMOS manufacturing process employed
Furthermore, the photo-thermoelectric effect of graphene allows in the microelectronics industry. This compatibility allows for
for the direct conversion of photons into electrical voltage sig- the realization of compact, high-volume devices through cost-
nals. These properties make graphene an ideal material for high- effective foundry processes.
performance optical modulators and photodetectors in optical in- Over the past two decades, there have been significant advance-
terconnects. Unlike traditional approaches that require carrier ments in the design and fabrication technologies of silicon pho-
doping and epitaxy processes, graphene-based solutions can rely tonics. These advancements have led to a gradual replacement of
solely on passive building blocks. This eliminates the need for discrete components with silicon-based devices in optical com-
expensive SOI wafers and sophisticated implantation and epitaxy munication systems, thereby achieving process standardization.
processes. Consequently, the fabrication of active devices can be The emergence of international foundries offering multi-project
shifted from the front-end-of-line (FEOL) to the back-end-of-line wafer services has played a pivotal role in transitioning this tech-
(BEOL). Overall, the implementation of graphene technology of- nology from research laboratories to the industry. Notable exam-
fers significant advantages, simplifying manufacturing processes ples include IMEC, in collaboration with Ghent University in Bel-
and reducing costs. This paves the way for graphene-enhanced gium, AMF in Singapore, AIM Photonics in the US, CEA-Leti
silicon photonic solutions with an excellent price-performance in France, and IHP’s monolithic electronic-photonic integration
ratio for next-generation high-capacity optical interconnects.[100] platform in Germany[90,91,101]

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Figure 1. Schematic of a graphene-based silicon photonic transceiver chip.

2.1. Silicon Photonic Platforms Based on SOI was used as the starting substrate. The top silicon layer can be
patterned using photolithography. After exposure and the resist
Silicon photonics is based on SOI substrate as the primary in- is developed, the design pattern is transferred to hard mask layer.
tegration platform.[8,9] The salient assets of SOI platform stem First Etch is used to transfer the pattern to the top silicon layer
from its fabrication compatibility with CMOS foundries and high with an etching depth of 70 nm by inductively coupled plasma
refractive index contrast, which make low-cost manufacturing of (ICP) dry etching. Repeat the photolithography and etching steps
PICs and dense integration feasibility. SOI wafer with a top sili- mentioned above, 60 nm silicon etch and 150 nm silicon etch are
con thickness of 220 nm is the mainstream platform for silicon then carried out. After the three-step etching, oxide is deposited
photonics. In addition, there is also a 3 μm thick top silicon SOI as the upper cladding to protect the waveguide layer. At this stage,
known as a thick silicon photonics platform, which combines rib we get 70nm-etch for grating coupler, 130nm-etch for modula-
and strip type waveguide. The large cross-sectional area of waveg- tor, and 220nm-etch for waveguide and the wafer is ready for
uides in this platform allows to propagate of higher optical pow- further processing such as dopant implantation, Ge epitaxy, tita-
ers (>1 W) compared to submicron-thick SOI waveguides.[102] nium nitride (TiN) heater deposition, metal pad formation, deep
The general fabrication method of different optical materials trench etching and etc. Figure 2(b) is the final cross-sectional
on the silicon platform, taking the typical silicon passive waveg- schematic for a full silicon photonics process flow including
uide device as an example, is illustrated in Figure 2(a). A 220 nm gratings, electro-optic silicon-based modulators, Ge detectors,
thick top silicon and 3 μm thick buried oxide (BOX) SOI wafer TiN heaters, Al metal electrodes, and others from the silicon

Figure 2. a) General fabrication processes for passive devices in silicon photonics. b) Cross-sectional schematic of a complete silicon photonics process
flow from SITRI, illustrating functional devices such as grating couplers, modulators, and photodetectors.

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Table 1. State-of-the-art silicon photonic passive devices from foundries.

Foundry Wafer size Wavelength Strip waveguide Edge coupler Grating coupler 1 × 2 MMI Crossing
[mm] [nm] propagation loss coupling loss coupling loss
[dB cm−1 ] [dB/facet] [dB/facet] Insertion loss Imbalance Insertion loss Crosstalk
[dB] [dB] [dB] [dB]

IMEC[ 9,103] 200 1550 ≈1.4 ≈2 - - - - -

1310 - - - - - - -
AMF[ 9 ] 200 1550 ≈1.48 1.25–1.30 <4 <0.1 <0.1 <0.15 <-40
1310 - 1.25–1.64 <4 <0.2 <0.1 <0.15 <-40
AIM Photonics[ 9,104] 300 1550 1.8–2.6 ≈1.5 ≈3 - - - -
SITRI 200 1550 ≈2.5 - 3.6 0.07 0.07 0.03 <-40
1310 ≈3.5 - 2.9 0.13 0.08 0.03 <-40

photonics platform at Shanghai Industrial Technology Research an ideal candidate for fulfilling specific requirements in various
Institute (SITRI). applications.[105]
In the following sections, we will provide an overview of The SiN-on-insulator wafer typically utilizes SiN cores with
the fundamental building blocks and core functional devices a thermal SiO2 bottom cladding layer that is 3 μm or thicker,
that are fabricated on mainstream silicon photonic foundries formed on a silicon substrate. The SiN layer is commonly
offering public multi-project wafer (MPW) services, particu- deposited using plasma-enhanced chemical vapor deposition
larly catering to academic users. Tables 1–3 summarizes the (PECVD) at 400 °C or low-pressure chemical vapor deposition
typical figure of merits (FOMs) of essential passive and ac- (LPCVD) at approximately 800 °C. Photolithography or electron
tive devices. Please note that in these tables, “-” indicates beam lithography (EBL) and ICP dry etching are then employed
that the latest FOMs have not been publicly disclosed, but to fabricate various photonic devices.[59,101] By adjusting the pro-
they can be accessed by signing a non-disclosure agreement cess variables of PECVD, such as pressure, temperature, flow
(NDA) with the respective foundry. It is worth mentioning rate, gas ratio, and RF power, the thickness and refractive in-
that all the listed SOI platforms in these tables have a uni- dex of the SiN film can be controlled, resulting in a typical
form top layer silicon thickness of 220 nm, allowing for a fair index contrast of 1.0 (cladded with air) or 0.55 (cladded with
comparison SiO2 ) in a SiN waveguide.[101] In Figure 3(a), a regular subtrac-
tive process flow of a 6-inch SiN foundry fabrication process is
depicted.[106] First, a SiN film and a SiO2 film are sequentially de-
2.2. Silicon Photonic Platforms Based on SiN posited on a clean thermal wet SiO2 substrate using LPCVD. Sub-
sequent steps involve deep ultraviolet (DUV) stepper photolithog-
SiN has garnered attention as a flexible CMOS-compatible pho- raphy and dry etching to transfer the waveguide pattern from
tonics integrated platform that complements the functionality the photoresist mask to the SiO2 hard mask and then into the
and capabilities of SOI photonics. It caters to a wide range of SiN layer. The etched waveguide undergoes thermal annealing
photonic applications, spanning from the visible to mid-infrared in a nitrogen atmosphere to eliminate nitrogen-hydrogen bonds
wavelengths. SiN benefits from its intrinsic properties, including in the SiN that cause absorption loss. Finally, a SiO2 cladding
a wide transparency window, moderately high material optical is deposited, which also requires high-temperature annealing
nonlinearity, low optical attenuation, and negligible two-photon to remove silicon-hydrogen bonds that contribute to absorption
absorption at 1550 nm. Moreover, SiN is compatible with mass loss.
manufacturing processes.[72] Furthermore, SiN offers flexibility With technological advancements, several optimization so-
in tuning its optical properties such as the optical band gap and lutions have been proposed to reduce on-chip SiN waveguide
refractive index. By adjusting the N/Si ratio of the material, the propagation loss. These include high-temperature thermal an-
optical band gap can be varied from 5.0 to 2.7 eV, while the refrac- nealing after deposition to break N-H bonds, chemical me-
tive index can be tuned from 1.7 to 3.0. This tunability makes SiN chanical polishing to improve film roughness and waveguide

Table 2. State-of-the-art silicon photonics Mach-Zehnder modulators from foundries.

Foundry Wavelength [nm] V𝜋L [V·cm] 3-dB bandwidth Peak-to-peak driving Dynamic extinction ratio Insertion loss [dB]
[GHz] voltage [V]

IMEC[ 8 ] 1550 1.39 ≈27 2.5 ≈4.1 dB @ 56 Gbps ≈2.2

AMF[ 9 ] 1550 2.11 >40 3 ≈3.9 dB @ 56 Gbps ≈3.2
AIM Photonics[ 104] 1550 0.8 - 0.8 ≈6 dB@ 50 Gbps ≈4.1
SITRI 1310 1.2 ≈35 - - ≈4.4

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Table 3. State-of-the-art Ge photodetectors from foundries.

Foundry Wavelength [nm] Bias [V] 3-dB bandwidth [GHz] Responsivity [A W−1 ] Dark current [nA] Signal-to-noise ratio

IMEC[ 8 ] 1550 -2 24 0.98 10.7 5.3 @ 35 Gbps

1550 -2 >50 0.86 16.4 5.2 @ 50 Gbps
AMF[ 9 ] 1550 -2 35 0.85 30 -
AIM Photonics[ 104] 1550 -1 ≈50 >1 - -
SITRI 1550 -2 ≈30 0.8 <100 -
1310 -2 ≈20 0.8 <100 -

sidewall roughness, the use of reactive sputtered SiN thin shown in Figure 4(a) is from AMF and features a single-layer SiN
films[107] and photonic damascene process.[63,70] The photonic on top of a standard SOI. This platform successfully integrates
damascene process enables the fabrication of very thick SiN films SiN devices for large-scale light routing with SOI passive and ac-
(0.8–1.75 μm) hosting waveguides with a propagation loss of tive devices. The propagation losses of SiN waveguides are as low
less than 0.05 dB m−1 .[108] The optimized damascene process in- as ≈0.17 dB cm−1 and ≈0.15 dB cm−1 for LPCVD and PECVD
volves DUV lithography, dry etching, reflow, LPCVD SiN deposi- SiN at 1550 nm and <0.2 dB cm−1 for the entire C band.[9] In
tion, planarization, and SiO2 cladding deposition, as illustrated in IMEC’s latest demonstration, the SiN-SOI photonics platform
Figure 3(b).[109] is upgraded with the monolithic integration of a lower-loss and
highly uniform LPCVD SiN waveguide layer, exhibiting a loss
2.3. Silicon Photonic Platforms Based on SiN-SOI of 1.2 dB cm−1 at 1550 nm and 0.23 dB cm−1 at 1310 nm. No-
tably, this platform uses the as-deposited LPCVD SiN film with-
A multilayer SiN-SOI platform has been developed, where one out any post-deposition annealing. With additional annealing for
or more SiN waveguide layers are deposited on and/or be- the LPCVD SiN standalone platform, the losses can be further
low a silicon photonic layer. The integration of these plat- reduced to 0.21 dB cm−1 at 1550 nm and 0.2 dB cm−1 at 1310
forms combines the advantages of a complete set of optical nm.[103]
functional devices with the ultra-low transmission losses of The second platform depicted in Figure 4(b) is a typical double-
SiN waveguides on the SOI platform, offering improved de- layer SiN-SOI platform, introduced to overcome the trade-off be-
vice functionality and performance.[60] This heterogeneous in- tween interlayer transition loss and crossing loss in a single-layer
tegration platform is capable of meeting the requirements of SiN-SOI platform.[110] This platform is suitable for constructing
applications spanning from visible light to the mid-infrared very large PICs containing numerous crossings. Efficient inter-
bands.[108] layer transitions are achieved through close spacing between ad-
Figure 4(a,b) illustrates the cross-sectional schemes of typical jacent layers, while ultra-low-loss crossings are enabled by the
silicon photonics integration platforms, including a single-layer large spacing between the topmost and bottommost layers. In-
SiN and a double-layer SiN, respectively,[9,110] The first platform terlayer taper transitions with losses < 0.15 dB for wavelengths

Figure 3. a) Subtractive process flow of SiN waveguides. Adapted with permission.[106] Copyright 2023, Optica Publishing Group. b) Optimized dam-
ascene process flow of SiN waveguides. The false-color SEM images show the SiN regions in the blue shade. Adapted with permission.[109] Copyright
2021, Nature Publishing Group.

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Figure 4. a) Cross-sectional schematic of a typical silicon photonics integration platform from AMF Reproduced with premission.[9] Copyright 2021,
Optica Publishing Group. b) Left: Schematic of the BEOL SiN1/SiN2/Si multilayer platform with full active integration. Right: Illustration of interlayer
transitions between the Si, SiN1, and SiN2 layers Adapted with permission.[110] Copyright 2018, Institute of Electrical and Electronics Engineers.

ranging from 1480 nm to 1620 nm and crosstalk below −56 dB hand, graphene possesses CMOS compatibility, as wafer-scale
have been demonstrated.[111] graphene sheets can be grown using chemical vapor deposition
In conclusion, we provide a comparison of silicon photonic (CVD) and transferred to cover an entire wafer.[118–120] This ca-
platforms with SiN integration from mainstream foundries in pability enables the integration of high-quality graphene onto a
Table 4, including information on wafer size, SiN type, anneal- silicon photonics platform, facilitating the realization of wafer-
ing, integration with SOI, waveguide size, and typical waveguide level scalable graphene-based optoelectronic devices.[121,122] In
propagation losses. this section, we will first review the methods for achieving high-
quality graphene in Section 3.1. Next, we will discuss the core
steps involved in the transfer and metal contact formation of
3. Solutions to Graphene Integration graphene integration in Sections 3.2 and 3.3, respectively. Finally,
we will review the efforts made in graphene integration within
Ever since its isolation and study by Novoselov and Geim in silicon photonics in Section 3.4.
2004,[112] graphene has captured significant attention from re-
searchers and scientists globally due to its remarkable proper-
ties. It is regarded as one of the most promising materials for 3.1. Synthetization of Graphene
future nanoelectronic devices and interconnects beyond silicon.
Moreover, graphene shows potential as a transparent electrode in Several promising synthesis methods for graphene have been re-
optoelectronic applications, including solar cells and flat-panel ported, and they can be broadly categorized into bottom-up and
displays.[113–117] Its exceptional properties have paved the way top-down approaches. In Figure 5(a), a summary of the main-
for exploring new possibilities in various fields. On the other stream graphene synthesis methods is provided.

Table 4. State-of-the-art SiN platforms from foundries.

Foundry Wafer size SiN type Anneal or not Integration with SOI Waveguide propagation loss Waveguide propagation loss
(mm) or not at 1550 nm [dB cm−1 ] at 1310 nm [dB cm−1 ]

IMEC[ 8 ] 200 LPCVD No Yes ≈1.2 ≈0.23

Yes No ≈0.21 ≈0.2
PECVD No Yes ≈2.6 ≈0.8
AMF[ 9 ] 200 PECVD - Yes <0.2 <3.01
LPCVD - Yes <0.42 <0.30
AIM Photonics[ 104] 300 PECVD - Yes 0.5–5.5 -
SITRI 200 LPCVD Yes No <0.15 <0.25

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Figure 5. Major approaches of graphene synthesis. Fabrications of graphene could be categorized into several approaches: a) mechanical exfoliation,
chemical exfoliation, mechanical force-assisted liquid exfoliation, b) epitaxial growth, and c) chemical vapor deposition Adapted with permission.[171]
Copyright 2017, Nature Publishing Group.

The top-down methods involve the exfoliation of thin graphene bility for mass production purposes. As a result, alternative syn-
layers from bulk graphite. This includes techniques such as me- thesis methods such as CVD have been developed to address the
chanical cleavage, where individual graphene layers are mechan- scalability and production challenges associated with mechanical
ically separated from graphite using adhesive tape. Another top- exfoliation.
down approach is liquid phase exfoliation, which utilizes solvents
to disperse and exfoliate graphite flakes into graphene layers. On
3.1.2. Chemical Exfoliation
the other hand, bottom-up approaches involve the construction
of graphene from small molecules or atoms, gradually building
The “Hummers” method, initially developed by William Hum-
them up to form a graphene structure. Epitaxial growth is one
mers in the late 1950s,[131] is a widely used approach for large-
such bottom-up method, where graphene is grown on a suitable
scale graphene synthesis. This method involves a water-free mix-
substrate by depositing carbon atoms in a controlled manner.[123]
ture of concentrated sulfuric acid, sodium nitrate, and potas-
CVD is another commonly used bottom-up technique, where
sium permanganate. It is known for its simplicity and relatively
carbon-containing gases are decomposed on a substrate to form
short reaction time. The reaction is conducted at a temperature
graphene layers.[124–128] PECVD is a variant of CVD that utilizes
of around 45 °C and can be completed within 2 hours.
plasma to enhance the growth process.[129,130] These different
The “Hummers” method employs strong acids and oxidants
synthesis methods offer flexibility in terms of scalability, quality,
to produce graphene oxide (GO) from graphite. Graphene oxide
and control over the graphene properties, allowing researchers
refers to graphene that has undergone oxidation, resulting in the
and scientists to choose the most suitable method for their spe-
disruption of the pristine graphene lattice structure. This process
cific applications.
helps to separate the graphene layers from the graphite source.
Although the “Hummers” method allows for the production of
graphene oxide, further reduction steps are necessary to con-
3.1.1. Mechanical Exfoliation
vert it into graphene. This reduction process is typically referred
to as the reduction of graphene oxide (rGO) and involves the
Mechanical exfoliation, as used in the original work to isolate
restoration of the graphene lattice structure by removing oxygen-
graphene, remains one of the most successful techniques for ob-
containing functional groups from GO.
taining high-quality graphene flakes. In 2004, the first graphene
It is important to note that the “Hummers” method involves
flake in the world was obtained from Highly Oriented Pyrolytic
the use of powerful oxidizing agents and strong acids, which
Graphite (HOPG) using mechanical exfoliation.[112] Mechanical
can be hazardous and require careful handling. However, this
exfoliation enables the production of graphene sheets with differ-
method has played a significant role in the development of large-
ent thicknesses by peeling off layers from various graphitic mate-
scale graphene synthesis, serving as a foundation for further ad-
rials such as HOPG, single-crystal graphite, or natural graphite.
vancements and alternative approaches in graphene production.
This technique is considered non-destructive because it does not
In recent years, significant progress has been made in Hummers’
involve the use of chemicals or chemical reactions during the fab-
method.[132–135]
rication process. The resulting graphene flakes obtained through
mechanical exfoliation can exhibit perfect crystal quality. How-
ever, the mechanical cleavage method does have certain limita- 3.1.3. Mechanical Force-assisted Liquid Exfoliation
tions. It suffers from low production yield and poor throughput,
making it less suitable for large-scale production. The manual Liquid phase exfoliation methods have emerged as effective tech-
and time-consuming nature of the process restricts its applica- niques for obtaining ultrathin 2D nanosheets from layered bulk

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graphite. These methods involve applying mechanical forces to cise control over monolayer thickness, and effective suppression
graphite crystals dispersed in liquid media, leading to the exfo- of wrinkle formation on a wafer scale. This technique leverages
liation of graphene flakes. Two main categories of mechanical commercially available semi-insulating SiC wafers, allowing for
force-assisted liquid exfoliation methods have been developed: the direct growth of high-quality and uniformly layered graphene
sonication-assisted liquid exfoliation[133,136–138] and shear force- on a large scale. Although graphene derived from SiC has demon-
assisted liquid exfoliation.[135,139–141] strated utility in electronics and radiofrequency transistors, the
In sonication-assisted liquid exfoliation, graphite is chemically utilization of SiC wafers introduces limitations regarding the uni-
dispersed in a liquid medium without the use of surfactants. The formity of epitaxial graphene thickness, wafer sizes, wafer costs,
dispersion is then subjected to ultrasonication in organic sol- and the availability of micromachining methodologies[146–148]
vents. Ultrasonication utilizes cavitation, a process in which rapid
formation and collapse of bubbles generate local high tempera-
tures and extreme pressures. This cavitation process effectively 3.1.5. Chemical Vapor Deposition
breaks apart stacked graphene flakes in the bulk crystal, resulting
in the exfoliation of graphene layers. The process minimizes me- The most promising, inexpensive, and readily accessible ap-
chanical damage to graphite, mainly impacting graphene’s sur- proach for depositing reasonably high-quality graphene is CVD
face. Sonication in organic solvents yields high-quality graphene onto transition metal substrates such as Ni,[124] Pd,[125] Ru,[126]
but requires longer treatment.[137] Ir,[127] or Cu.[128] Figure 5(c) illustrates the CVD process of
Shear force-assisted liquid exfoliation, on the other hand, in- graphene on copper foil. However, extensive initial investigations
volves applying shear forces to the graphite dispersion. This can using nickel revealed a fundamental limitation with this catalyst.
be achieved through various methods such as mechanical shear- It was found that single and few-layer graphene obtained over
ing or hydrodynamic flow. The shear forces act on the graphite tens of microns was not homogeneous across the substrate sur-
crystals, causing them to separate into individual graphene face. This issue arises because at temperatures above 800°C, car-
layers. bon, and nickel form a solid solution due to the large solubility
Both sonication-assisted and shear force-assisted liquid ex- of carbon in nickel.
foliation methods have shown promise in achieving high-yield In the cooling process, the solubility of carbon decreases, caus-
and large-scale exfoliation of graphene. By utilizing mechanical ing carbon to diffuse out of the Ni. Carbon segregation occurs
forces in liquid media, these techniques enable the production rapidly within Ni grains and is heterogeneous at grain bound-
of graphene flakes from layered graphite, offering a pathway for aries. Consequently, there is an uneven distribution of graphene
scalable graphene synthesis. layers, with a higher number of layers forming at grain bound-
aries compared to those forming over Ni grains. This leads to
variations in the number of graphene layers on the surface. Un-
3.1.4. Epitaxial Growth like Ni substrates, which have high carbon solubility (0.9 at. % at
1084 °C),[149] Cu substrates with low carbon solubility (0.00045 at.
Figure 5(b) illustrates the fundamental phenomenon of epitaxial % at 850 °C)[150] allow for more facile formation of single-layer
graphene growth on silicon carbide (SiC) substrates. When SiC graphene over large areas. In contrast to growth on Ni film, as
is subjected to heat in a vacuum or argon atmosphere, the silicon mentioned earlier, graphene synthesized on polycrystalline Cu
atoms selectively evaporate from the surface due to the difference foil exhibits exceptional film uniformity over a large area. Stud-
in vapor pressures between silicon and carbon. Consequently, ies have demonstrated the growth of monolayer graphene over
the remaining carbon atoms rearrange themselves and sponta- 95% of the Cu surface, while the remaining surface is covered by
neously form epitaxial graphene on the SiC surface.[123,142–144] a few layers of graphene.[128] One significant advantage of Cu is
This process takes advantage of the vaporization behavior of sili- its suitability for growth over extensive areas. This was demon-
con, leaving behind a carbon-rich environment that facilitates the strated by Bae et al. in a roll-to-roll process for the production of
formation of an epitaxial graphene layer. predominantly 30-inch graphene film.[151]
In 2000, Kusunoki and coworkers observed few-layer Both single-nucleation[152–154] and multi-nucleation[155,156] ap-
graphene (FLG) on SiC(0001) using a transmission electron proaches have been employed for the growth of single-crystal
microscope.[143] This was followed by Novoselov’s report on the graphene.[129,130] While the single-nucleation approach is effec-
electric field effect in FLG in the same year. In 2004, Berger et al. tive in producing high-quality graphene, the multi-nucleation ap-
made significant contributions by demonstrating the presence proach offers faster growth rates, making it more suitable for
of Shubnikov–de Haas oscillations in epitaxial graphene on scalable and efficient graphene production. In line with this,
SiC,[144] which laid the foundation for the study of a novel a pilot-scale CVD system has been designed and constructed
quantum Hall system. They also revealed the Dirac nature of specifically for the mass production of single-crystal graphene
the charge carriers and showcased exceptional carrier mobility wafers. This system is capable of producing 25 graphene wafers
exceeding 25 000 cm2 ·V−1 ·s−1 in graphene on SiC.[142] in a single process cycle, demonstrating the potential for large-
Around 2008, wafer-scale homogeneous graphene growth be- scale production.[157] The scalability of wafer-sized single-crystal
came possible through annealing in an argon atmosphere, which graphene is crucial for its application in high-performance elec-
suppressed the decomposition rate and improved the quality of tronics and optoelectronics, as it enables compatibility with exist-
the graphene.[145] Epitaxial growth of graphene on the silicon ing wafer processes.
face of SiC, as depicted in Figure 5(a), enables the production of While chemical vapor deposition (CVD) techniques utiliz-
high-quality films with uniform crystallographic orientation, pre- ing metal catalysts show promise for synthesizing large-area,

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near-perfect, and transferable graphene, the catalyst involves an Additionally, the PMMA/graphene layer floats on the water sur-
inevitable transfer step, which may introduce defects and im- face, allowing for easy retrieval and transfer onto the desired
purities, potentially degrading the performance of graphene- substrate. To complete the transfer, the polymer support can be
based devices.[158] Moreover, synthesizing graphene on metal dissolved using solvents such as acetone or acetic acid, separat-
substrates presents a persistent challenge due to the inherent ing the graphene from the PMMA layer. This step finalizes the
risk of metal contamination, particularly in semiconductor de- graphene transfer process.
vice production.[159,160] Exploring CVD methods for the direct Electrochemical methods, pioneered by Wang et al. involve im-
synthesis of graphene on non-metal insulating substrates repre- mersing graphene in copper in water and applying a bias to the
sents another promising avenue.[161] Most CVD approaches with copper substrate.[175] This process leads to water electrolysis and
nonmetal substrates use solid substrates, such as quartz,[162,163] the formation of H2 bubbles between the graphene and the metal
SiO2 ,[164] Si3 N4 ,[165] and sapphire.[166,167] Although numerous substrate. These bubbles generate a peeling force, ultimately de-
studies have been conducted to achieve direct growth on insu- laminating the graphene from the growth substrate. This trans-
lating surfaces, achieving large area, homogeneous monolayer fer method is particularly suitable for conducting substrates that
graphene remains challenging. The growth rate and quality of can serve as electrodes. It allows for the clean detachment of
graphene films are limited by the low catalytic activity of the graphene from the growth substrate, enabling the recycling of
quartz surface and the sluggish diffusion speed of carbon species the substrate. This sets it apart from conventional wet transfer
on insulating substrates. Obtaining single-crystalline graphene methods that involve chemical etching of the metal substrate.
with full wafer-scale coverage directly is extremely difficult. An- The electrochemical method is economical as it reduces the need
other approach to promote graphene growth is by introducing for etchants or cleaning agents and is scalable.
gaseous catalysts, which facilitate transfer-free growth. The use In a study by Gao et al., the bubble transfer method
of silane as a gaseous catalyst significantly enhances the growth was investigated for transferring graphene from[176] platinum
rate and domain size of graphene on h-BN substrates, achiev- substrates.[176] Notably, they observed no contamination of metal
ing an 80-fold increase compared to growth without catalysts.[168] ions on the transferred graphene, highlighting a significant ad-
Recently, a promising alternative has emerged with the use of vantage of non-etching transfer methods. By avoiding the intro-
semiconducting Ge wafers as substrates for epitaxial graphene duction of metal ion impurities onto the graphene, these trans-
growth.[169] Ge wafers offer advantages such as catalytic activity fer methods ensure the preservation of graphene’s purity and
and low carbon solubility, effectively addressing the contamina- quality.[131] However, it is important to note that during the elec-
tion issue. In a groundbreaking development, Lee et al. achieved trochemical delamination process, the production of hydrogen
the synthesis of wafer-scale single-crystal graphene films on bubbles can potentially cause mechanical damage to the trans-
2-inch Ge substrates with an unusual (110) orientation. This ferred graphene.
achievement marks a significant stride in controlled graphene To address the limitations of the PMMA support layer, PDMS
growth on non-metallic substrates, holding potential for semi- (Polydimethylsiloxane) has been introduced as a replacement in
conductor device manufacturing.[170] the graphene transfer process.[173,177,178] The PDMS interface is
weaker than the substrate interface due to its extremely low sur-
face energy. While this technique is considered suitable, it re-
3.2. Transfer of Graphene quires a stronger adhesion between the graphene and the new
substrate compared to the adhesion between the graphene and
Currently, the transfer of large-area and high-quality graphene the PDMS stamp. This limitation has restricted the use of the
synthesized on metal substrates typically requires the use of polymeric layer alone for graphene transfer.
wet etching methods.[128,172] However, these processes have cer-
tain drawbacks. They can introduce ionic species between the
graphene and substrate interface, which act as scattering centers
and negatively impact the electrical properties of graphene-based 3.2.2. Small Molecular-assisted Transfer
devices. Furthermore, the etching procedure results in the loss of
metal material, leading to increased overall costs in the transfer Based on density functional theory (DFT) calculations, the ad-
process. sorption energy (Ead ) of PMMA to graphene is determined to
be 2.69 eV, indicating a strong binding between PMMA and
graphene. This strong adsorption energy is one of the reasons
3.2.1. Polymer-assisted Transfer why a significant amount of PMMA residues are retained dur-
ing the transfer process. To address the limitations associated
The polymer-assisted transfer (PAT) method is a widely used with PMMA, researchers have focused on exploring alternative
technique for transferring graphene onto a target substrate. In supporting materials for graphene transfer. Among these alter-
this method, a thin support layer, typically poly(methyl methacry- natives, small molecular materials have emerged as an effec-
late) (PMMA), is first incorporated onto the surface of the tive category of supported materials for graphene transfer. These
graphene.[128,172] The underlying metal substrate is then selec- small molecules provide a promising solution as they can offer
tively etched away, either using ammonium persulfate or iron better control over the transfer process and potentially reduce
(III) chloride, as shown in Figure 6(a).[128,172–174] The PMMA layer the residue issue. By using small molecular materials as sup-
serves as a protective barrier, preventing the fragile single-layer port layers, it is possible to achieve efficient and clean transfer
graphene from folding or fracturing during the etching process. of graphene without the drawbacks associated with PMMA.

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Figure 6. Schematics of the graphene wet transfer process using various supporting materials. a) PMMA. Adapted with permission.[183] Copyright 2012,
American Chemical Society. b) Rosin. Adapted with permission.[184] Copyright 2013, American Association for the Advancement of Science. c) Paraffin.
Adapted with permission.[182] Copyright 2019, Nature Publishing Group.

In 2017, the Cheng Group discovered that Resin need for extensive rinsing, this approach mitigates potential dam-
(C19 H29 COOH), a small natural organic molecule, is highly age to the graphene during the removal process.
suitable as a supporting layer for the transfer of CVD-grown To address the issues of polymer contamination and graphene
graphene films.[179,180] This alternative material exhibited lower wrinkling associated with the use of PMMA as a supporting ma-
adsorption energy (Ead = 1.04 eV) on the graphene surface terial, the J. Kong group introduced a novel method utilizing
while maintaining competent supporting strength, making it an paraffin as an alternative supporting material for graphene trans-
excellent choice for the transfer of CVD-grown graphene films, fer (see Figure 6(c)).[182] A crucial step in the process involved
as shown in Figure 6(b). transferring the paraffin-supported graphene layer onto deion-
Traditionally, the removal of support materials in graphene ized water maintained at a temperature of 40°C for one hour. At
transfer processes involves rinsing the graphene-loaded wafer this temperature, the paraffin support layer experienced slight
with an organic solvent like acetone. However, Chandrashekar thermal expansion while remaining in a solid state. The absorp-
et al. introduced an innovative method that utilizes camphor for tion of heat from the water caused the paraffin to expand, re-
graphene transfer.[181] In this method, the transferred graphene sulting in the stretching of the graphene film beneath. This ther-
is subjected to sublimation at room temperature for 1 hour, fol- mal expansion-induced stretching effectively reduced the forma-
lowed by a short exposure to 90°C for 5 minutes to completely tion of wrinkles in the graphene, ensuring a smoother and more
remove the camphor. The unique property of camphor being eas- uniform graphene layer. Paraffin-transferred CVD monolayer
ily removable through sublimation alone sets this method apart. graphene on Si/SiO2 substrate experienced almost zero strain
By reducing the reliance on organic solvents and minimizing the and very weak p-doping, approaching that of intrinsic graphene.

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Figure 7. Schematics of the renewable graphene dry transfer process from various substrates. a) Copper. Adapted with permission.[183] Copyright
2012, American Chemical Society. b) SiC. Adapted with permission.[184] Copyright 2013, American Association for the Advancement of Science. c) Ge
(with metal). Adapted with permission.[170] Copyright 2014, American Association for the Advancement of Science. d) Ge (with hBN). Adapted with
permission.[187] Copyright 2019, American Chemical Society.

3.2.3. Dry Transfer play a crucial role in determining the success of the exfoliation
process.
Dry transfer of graphene is a technique that allows for the trans- Yoon et al. conducted pioneering work on the mechanical peel-
fer of graphene from one substrate to another without the use of ing of graphene from copper (Cu) substrates.[183] They calculated
wet chemical processes or solvents. This method offers several the adhesion energies (0.72 ± 0.07 J·m−2 ) between graphene and
advantages, including the preservation of the integrity and quality Cu to understand the underlying mechanisms of the peeling pro-
of the graphene layer, precise placement control, and compatibil- cess. The detachment of graphene from copper (Cu) substrates
ity with various devices and structures. It has gained significant is made possible by peeling off the graphene using polyimide
attention in graphene research and applications, especially in the (PI) (Figure 7(a)).[185] In this process, the adhesion strength be-
fields of electronics and optoelectronics. tween suitably cured PI and graphene is higher than the adhesion
To achieve non-destructive removal of graphene from the syn- strength between graphene and Cu. This difference in adhesion
thesis substrate for substrate recycling, it is necessary to over- strength enables the successful detachment of graphene from the
come the adhesion between graphene and the growth substrate. Cu substrate.
A single layer of graphene cannot be exfoliated or manipulated High-quality graphene can be synthesized on SiC wafers
without the support of a supporting layer during the exfoliation through a self-limiting sublimation process silicon. This growth
process. The adhesion strength between graphene and the sup- method ensures the formation of graphene with a single orien-
porting substrate must be greater than that between graphene tation due to the self-limiting nature of the process. While SiC
and the growth substrate. substrates are electrically insulating, making them suitable for
The design of a graphene exfoliation process goes beyond con- certain applications without the need for transfer, the high cost of
sidering the relative strengths of adhesion between graphene SiC necessitates the exploration and establishment of techniques
and the substrates used for synthesis and exfoliation. Other fac- for effectively transferring graphene synthesized on SiC wafers to
tors, such as the roughness of the growth substrate and the pro- enable its utilization in various applications.[186] As mentioned
cessing parameters, also have a significant impact. Parameters earlier, the adhesion strength between graphene and SiC is high,
such as the temperature and pressure during the deposition of allowing graphene to be exfoliated with the right adhesion layer.
the supporting substrate can influence the interfacial area be- Kim et al. demonstrated that single-layer graphene can be exfoli-
tween the graphene and the supporting substrate. These factors ated by using an adhesive-strained layer (Ni) and a handling layer

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(thermal release tape).[184] The graphene released from the SiC device performance. However, the reported value of contact resis-
surface is then transferred onto a wafer, and subsequently, the tance does not provide a consistent picture. It has been observed
thermal tape and Ni are removed (as shown in Figure 7(b)). that there is a slight difference in contact resistance as the dif-
The hydrogen-terminated Ge, which exhibited weak adhesion ference in the metal/graphene work functions varies, as shown
to graphene, allowed the authors to exfoliate the graphene from in Figure 8(a), indicating that work function should not be relied
the wafer using a thin film of evaporated gold (as shown in upon as a sole basis of analysis.[196–200] Xia et. al reported that
Figure 7(c)). The group also demonstrated repetitive sequential an anharmonic potential between the metal and graphene can
graphene synthesis and exfoliation from the same wafer without modify the M-G coupling, resulting in the traditional Landauer’s
any apparent deterioration of the graphene. Five years later, K.J. model being no longer appropriate for the accurate prediction of
Kim reported a method that uses van der Waals interactions to contact resistance.[194] They developed a modified model for de-
transfer continuous, high-quality graphene films from Ge(110) scribing the carriers’ transport at the junction based on two cas-
to a different substrate held by hexagonal boron nitride carri- caded processes: first, carriers are injected from the metal into the
ers in a clean, dry environment (Figure 7(d)).[187] The transferred graphene under it, followed by their transportation into the gate-
films are uniform and continuous with low defect density and controlled channel with probabilities TMG and TK , as shown in
few charge puddles. The transfer is effective due to the weak in- Figure 8(b). TMG reflects the coupling strength between the metal
terfacial adhesion energy between graphene and Ge. Based on and the graphene under it. Contact conductance is therefore de-
the minimum strain energy required for film isolation, the up- termined by TMG , TK, and the lowest number of modes under
per limit of the interfacial adhesion energy is estimated to be the metal or in the gate-controlled graphene channel. Figure 8(c)
23 meV per carbon atom, making graphene/Ge(110) the first as- schematically illustrates band profile and dipole formation at the
grown graphene film to have a substrate adhesion energy lower M-G interface. 𝜑M is the palladium work function, 𝜑G represents
than that of typical van der Waals interactions between layered the work function of monolayer graphene, ΔEFM (ΔEFG ) is the dif-
materials. It is suggested that graphene on Ge can serve as an ference between the Dirac-point and Fermi-level energies in the
ideal material platform to be integrated with other material sys- metal-doped graphene (graphene channel), ΔV is the total built-
tems through a clean assembly process. Due to the weak adhe- in potential difference, deq is the equilibrium distance, and d1 is
sion between graphene and the substrate, the graphene film can the effective distance between the charge sheets in the graphene
be effectively exfoliated and transferred while being attached to and metal. The red cross represents the Dirac cone, and thick red
an h-BN superlayer through van der Waals interactions, as shown lines are used to denote the broadening of electronic states. As a
in Figure 7(d). The transferred films exhibit uniformity and conti- result of combining experimental and theoretical results, it can
nuity with a low density of defects and few charge puddles. These be concluded that carrier transport in graphene under palladium
results indicate that our method offers a versatile, clean, and scal- (Pd) is close to ballistic, and a contact resistance as small as 110
able approach to engineer graphene interfaces. Ω·μm is realized.[194]
For a more deterministic route, edge contacts are formed by
removing a portion of the graphene under the contact using
3.3. Electrical Contract to Graphene lithographic methods in order to enable covalent bonds between
graphene and metal to be formed.[201] Originally proposed by
A realization of low metal-graphene (M-G) contact resistance Wang et al,[195] this approach utilizes an ingenious contact geom-
and the disclosure of its intrinsic limiting factors would have etry and is anticipated to provide much lower contact resistances.
significant implications for the development of and use of The edge-contact fabrication process is illustrated in Figure 8(d).
high-performance graphene-based optical electronics.[188–190] As In Figure 8(e), a cross-section scanning transmission electron
graphene has a much lower work function than traditional semi- microscope (STEM) image of a representative device shows the
conductor materials, electron injection from a metal contact resulting geometry of the edge-contact, and electron energy-loss
is much more difficult, and therefore, graphene devices may spectroscopy (EELS) mapping confirms that the graphene and
suffer from low current injection levels and/or high contact metal overlap at a well-defined interface. In this edge-contact ge-
resistance.[191] Moreover, the lack of surface bonding sites on ometry, the layer assembly and contact metallization processes
each side as well as the strong orbital hybridization of graphene, can be separated completely, allowing the edge contacts to per-
may also contribute to increased contact resistance at the M-G in- form better than traditional surface contacts. Using this technol-
terface. These intrinsic characteristics limit the contact resistance ogy, the edge contact resistance is ≈100 Ω·μm on an exfoliated
of M-G to a few thousand Ω·μm, which is ≈100 times higher than monolayer graphene and the sheet resistivity is less than 40 Ω
the resistance of silicon-based componentry.[192,193] per square, as shown in Figure 8(f).[195]
Consequently, researchers have developed various strategies to Besides the two strategies described above, thermal an-
minimize contact resistance and advance the development of op- nealing has also proven to be successful in reducing contact
toelectronics, including (i) work-function engineering[194] and (ii) resistance.[202] In particular, when coupled with other techniques,
edge-contact engineering.[195] In the first route, reducing contact contact resistance shows dramatic improvements even when the
resistance can be achieved by maximizing the work function dif- contact area of the graphene surface is contaminated with resist
ference between the metal and graphene by selecting a metal that residue.[201] Franklin et al. demonstrated an improvement in con-
can provide a large graphene density of states (DOS). This max- tact resistance of at least 40% over traditional top contacts us-
imized work function difference ensures good electrical contact ing a double-contact geometry with contact metals above and be-
between the metal and graphene and also increases the electrical low the graphene layer.[203] It is also possible to create defects in
current flow between the two materials, resulting in improved the graphene contacts before metallization by using low-power

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Figure 8. Contact resistance minimization strategies. a–c) work-function engineering. d–f) edge-contact engineering. a) Relationship between contact
resistance and work function difference between the metal (𝜑M ) and graphene (𝜑G ) (reprinted from).[200] b) Schematic view of two cascaded carrier
transport processes at the metal–graphene junction, with transmission efficiencies TMG and TK . c) Schematic view of the band profile and dipole
formation at the metal–graphene interface. (b,c) are reprinted from.[194] d) Schematic of the edge-contact fabrication process. e) High-resolution bright-
field STEM image and magnified false-color EELS map. f) Two-terminal resistance versus channel length at fixed density. Inset: Optical image of a transfer
length methods (TLM) device with edge contacts. (d–f) are reproduced with permission.[195] Copyright 2013, American Association for the Advancement
of Science.

O[204] or ultraviolet (UV) ozone[204] to clean graphene and make To meet the requirements of large-scale integration in sili-
it hydrophilic. Chemical bonds between M-G are formed during con photonic chip manufacturing, the development of a stan-
chemical bond formation, thus improving contact metals. De- dardized graphene-CMOS compatible process is highly desir-
spite the substantial progress that has been made in the reduc- able. Recently, a research team at IMEC made a significant
tion of contact resistance, it remains unclear what the underlying breakthrough.[122] They established a wafer-scale graphene inte-
physics is of the M-G contact. A general picture of M-G contact gration process within a 300 mm CMOS pilot line. They were
still needs to be further developed. able to transfer a 6-inch large graphene sheet onto a 300 mm large
SOI wafer for subsequent in-line processing (See Figure 9(a)). As
a proof of concept, single-layer graphene electro-absorption mod-
3.4. Graphene Integration in Silicon Photonic Platforms ulators were chosen as test vehicles to showcase the capabilities
of their graphene integration process. In their process, graphene
In standard silicon photonic platforms, SOI wafers serve as the is shaped using a hard mask, and the metal contacts are fabri-
backbone for building silicon photonic chips, with silicon and cated using a CMOS Ti/TiN/W damascene metallization process.
SiN as the core materials for constructing photonic integrated cir- More specifically, 250 nm diameter contact holes were patterned
cuits. Maintaining CMOS compatibility is critical when integrat- using DUV lithography and dry etching. The etching process is
ing new materials into a silicon photonic platform. Otherwise, selectively stopped at an Al2 O3 capping layer (See Figure 9(b)),
the core advantage of silicon photonics, which allows for low-cost, followed by resist stripping, etching of the Al2 O3 and graphene
large-volume, and high-yield fabrication in CMOS foundries with layers, and stopping at the underlying SiO2 layer. It’s worth not-
existing infrastructure, will be compromised. When compared ing that the dangling bonds created during graphene etching can
to other popular optical materials such as lithium niobate, poly- form strong covalent bonds with the metal, which hinders the
mers, and III-V semiconductors, graphene offers unique CMOS formation of good contacts and increases contact resistance. Al-
compatibility. Graphene can be grown at a wafer scale using CVD. lowing some time to pass between the etching of graphene and
Additionally, wafer-sized graphene can be transferred as long as the deposition of metal can passivate the dangling bonds with
the top surface of the target wafer is sufficiently flat.[118,119] What’s atmospheric water and oxygen.
more, the transfer of graphene can be carried out in both FEOL In addition to in-depth metallization studies, the IMEC team
and BEOL processes within a standard CMOS process flow,[122] also optimized the chemical mechanical polishing (CMP) pro-
providing significant flexibility for integrating graphene into sil- cess to minimize the topography of the SOI wafer before the
icon photonic platforms. wafer-scale graphene transfer process (See Figure 9(c)). With all

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Figure 9. In-line graphene integration on a 300 mm CMOS platform.Adapted with permission.[122] Copyright 2023, Wiley-VCH. a) A 6-inch large graphene
sheet integrated on a 300 mm large SOI wafer. b) Cross-section transmission electron microscope (TEM) images of a final device. c) Cross-section TEM
images taken at the waveguide edge for wafer with standard and optimized CMP.

these optimizations, they achieved a statistical modulation depth through the EAM can be adjusted. Phase modulators offer an al-
of 50 ± 4 dB mm−1 from 400 devices and a statistical electro- ternative method for achieving intensity modulation, allowing for
optical bandwidth of 15.1 ± 1.8 GHz measured from 25 μm long precise control over the intensity of optical beam by manipulating
devices. These results are comparable to lab-based graphene de- the phase of the light. Phase modulators allow the index of their
vices with a similar design and CVD graphene quality. Through active materials to be changed when an electric field is applied,
measurements on hundreds of graphene devices, the IMEC team resulting in a phase shift. This phase shift can be converted to an
successfully demonstrated the reproducibility of their graphene amplitude difference through interference or resonance effects,
wafer-scale integration on a silicon photonic platform. Their enabling intensity modulation of the optical signal. Both EAMs
work not only resolves the bottleneck of large-scale fabrication and phase modulators are commonly used for intensity modula-
of graphene-based photonic devices but also holds the potential tion in optical interconnects. The specific choice depends on the
to implement graphene-based electronic building blocks. requirements of the application. It is worth noting that, in com-
parison to EAMs, phase modulators offer a distinct advantage in
enabling coherent communications, which is particularly desir-
4. Graphene-based Silicon Photonic Modulators able for long-haul optical interconnects.[206]
In this section, we will first introduce the fundamentals of opti- However, due to its centrosymmetric crystal lattice, silicon ex-
cal modulators, with a focus on on-chip integrated silicon pho- hibits almost no linear electro-optic effects such as the Pockels
tonic modulators in Section 4.1. Following that, we will illustrate effect. Consequently, the most commonly employed method to
the working principle of graphene-based optical modulators in achieve high-speed optical modulation in silicon photonics is
Section 4.2. Afterward, various types of graphene-based silicon through the utilization of the plasma dispersion effect. This ef-
photonic modulators, including electro-absorption modulators, fect relies on altering the refractive index (Δn) and absorption
phase modulators, and plasmonic modulators will be introduced (Δ𝛼, measured in cm−1 ) of silicon by varying the concentration
and reviewed in Section 4.3. of free charges within the material. Soref and Bennett quantified
changes with phenomenological expressions.[207]

4.1. Fundamentals of Silicon Photonic Modulators Δn (at1550nm) = −8.8 × 10−22 ΔN − 8.5 × 10−18 ΔP0.8 (1)

Messages are typically digitalized into sequences of electrical bits, Δ𝛼 (at1550nm) = 8.5 × 10−18 ΔN + 6.0 × 10−18 ΔP (2)
which are then transmitted through optical channels in optical
interconnects. Optical modulators are employed to encode these where ΔN, ΔP are the carrier densities of electrons and holes
electrical signals into light by varying fundamental characteris- (the unit is cm−3 ). Indeed, the refractive index change induced by
tics of optical beams, such as amplitude, phase, or polarization. the plasma dispersion effect in silicon is typically larger than the
Among the various methods for data communication,[205] one changes induced by the Kerr effect and Franz-Keldysh effects.[1]
widely adopted approach is intensity modulation and direct detec- This characteristic makes the plasma dispersion effect a promi-
tion (IM-DD). In this method, a digital “1” is typically represented nent approach for achieving high-speed optical modulation in sil-
by a high optical power state, while a digital “0” is typically rep- icon photonics. Additionally, a crucial advantage of utilizing the
resented by a low optical power state. To achieve intensity mod- plasma dispersion effect in silicon photonics is its full compatibil-
ulation, one simple approach is to utilize an electro-absorption ity with CMOS processing. This compatibility enables seamless
modulator (EAM). This type of modulator alters the absorption integration of the plasma dispersion effect, making it the main-
of its active materials when an electric field is applied. By con- stream method for realizing high-speed optical modulators in
trolling the electric field, the intensity of the optical beam passing silicon photonics.

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Figure 10. Approaches to changing free carrier concentration in silicon photonics. a) Carrier accumulation. b) Carrier injection. c) Carrier depletion.

While both the refractive index (Δn) and absorption (Δ𝛼) are is the Fermi-Dirac distribution, e is the charge of an electron, ℏ is
affected by the plasma dispersion effect, it primarily manifests the reduced Planck’s constant, kB is Boltzmann’s constant, 𝜔 is
as an electro-refractive effect. This effect enables the realization the frequency of the electromagnetic wave, Ef is the Fermi level,
of phase modulation by manipulating the free carrier concen- and Γ is the phenomenological scattering rate (its reciprocal is
tration within an optical waveguide. There are three main ap- the scattering time 𝜏 = Γ−1 , and is assumed to be energy inde-
proaches commonly employed to introduce changes in the free pendent). Here we follow the e−i𝜔t (i2 = −1) convention. At optical
carrier concentration: 1) Carrier accumulation: Carriers are ac- frequencies, as ℏ𝜔 > >kB T, thus Equation (3) could be simplified
cumulated into an embedded capacitor within a silicon waveg- to[236]
uide, typically requiring an insulating barrier (as shown in Figure [ ( ) ( )]
e2 ℏ𝜔 + 2Ef ℏ𝜔 − 2Ef
10(a)). 2) Carrier injection: Carriers are moved by applying a 𝜎G = tanh + tanh
forward bias to a positive-intrinsic-negative (PIN) junction in- 8ℏ 4kB T 4kB T
tegrated into a silicon waveguide, as depicted in Figure 10(b). ( )2
3) Carrier depletion: Carriers are depleted from a PN junction ⎡ ℏ𝜔 + 2Ef ⎤ Ef
e2 ⎢ ⎥+i e
2
−i ln ( ) ( ) (4)
under a reverse bias, as illustrated in Figure 10(c). These tech- 8𝜋ℏ ⎢ ℏ𝜔 − 2E 2 − 2 k T 2 ⎥ 𝜋ℏ ℏ (𝜔 + iℏΓ)
niques enable phase modulation, which can be further converted ⎣ f B ⎦
into intensity modulation through various interferometric struc-
Then, the complex permittivity of graphene (𝜖 G ) could be cal-
tures such as Mach-Zehnder interferometers (MZIs)[208–213] and
culated with
Michelson interferometers.[214,215] Alternatively, resonant struc-
tures like ring resonators (RRs),[216–225] micro-disk,[226–229] and i𝜎G
photonic crystal cavities[230–233] can also be employed for this pur- 𝜀G = 1 + (5)
𝜔𝜀0 hG
pose. It is important to note that each approach and structure
mentioned above has its own advantages and disadvantages. The where 𝜖 0 is the vacuum permittivity, hG = 0.34 nm is the equiv-
choice of which to utilize depends on specific scenarios and re- alent thickness of graphene.[99] With Equations (4) and (5), the
quirements. For more in-depth information on this topic, com- real (𝜖′G ) and imaginary(𝜖″G ) parts of 𝜖 G are plotted in Figure
prehensive reviews by Rahim and others[1] by Rahim and others 11(a,b) as the function of Fermi level, where the wavelength of
provide valuable insights. photons is 1550 nm (ℏ𝜔 ≈0.8 eV) and 𝜏 = 100 fs. The tempera-
ture is 0.01K and 296K for Figure 11(a,b), respectively. It is evi-
dent that when the Fermi level (Ef ) exceeds half the photon energy
4.2. Working Principle of Graphene-based Silicon Photonic (ℏ𝜔/2, ≈0.4 eV), the imaginary part of the graphene permittivity
Modulators (𝜖″G ), represented by the red color in the plot, exhibits a signifi-
cant drop. This behavior occurs due to the Pauli blocking effect,
When graphene interacts with an electromagnetic wave, it can which inhibits interband transitions in graphene[237] As a result,
be effectively represented as an infinitesimally thin conductivity graphene becomes “transparent,” allowing only intraband tran-
surface[234] the complex conductivity of graphene, denoted as 𝜎 G, sitions to occur, primarily caused by long-range scattering from
could be expressed using the Kubo formula[235] impurities and defects (See Figure 11(c,d), which illustrate the
( ) ( ) ( ) possible optical transitions in graphene). The overall impact of
𝜎G 𝜔, Ef , T, Γ = 𝜎intra 𝜔, Ef , T, Γ (+ 𝜎inter 𝜔, Ef , ) T, Γ intraband transitions is described by the phenomenological scat-
( ) 2 ∞ 𝜕fd (E) 𝜕f (−E) tering rate, Γ, whose reciprocal is the scattering time 𝜏 = Γ−1 ,
𝜎intra 𝜔, Ef , T, Γ = 𝜋ℏ2−ie ∫0 E 𝜕E − d𝜕E dE (3)
( ) (𝜔+i2Γ)
ie2 (𝜔+i2Γ) ∞ fd (−E)−fd (E)
assumed to be energy-independent. A smaller Γ (longer scatter-
𝜎inter 𝜔, Ef , T, Γ = 𝜋ℏ2 ∫0 (𝜔+2iΓ)2 −4(E∕ℏ)2 dE ing time) corresponds to lower intraband absorption, leading to
reduced intrinsic optical absorption. Consequently, Γ serves as
where the intraband interaction and interband interaction are in- a descriptor for the quality of graphene in terms of optical loss.
1
dicated by the “intra” and “inter”, respectively. fd (E) = (E−Ef )∕k BT
e +1
More importantly, both the 𝜖′G or and 𝜖″G will be significantly

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Figure 11. Permittivity of graphene at a) 0.01 K and b) 296. Schematics of possible optical transitions in graphene c) Ef < ℏ𝜔/2 and d) Ef ≥ ℏ𝜔/2.

influenced by the Ef , which could be shifted by external gating. silicon photonic modulators are expected to have the lowest (best)
Therefore, by applying different gating voltages, one can achieve FOMPM .[100]
phase modulators or EAMs by varying the values of 𝜖′G or 𝜖″G To construct a graphene-based silicon photonic modulator,
of graphene. It is noteworthy that graphene can readily achieve electrical gating of graphene is necessary. There are two widely
pure phase modulation compared to silicon photonic modulators used structures to achieve this. The first structure involves a
based on the plasma dispersion effect. Furthermore, for a phase single-layer graphene (SLG) placed on a doped silicon waveguide
modulator, a critical FOM is defined as FOMPM = 𝛼·V𝜋 ·L, where with a dielectric spacer, as depicted in Figure 12(a). This config-
𝛼 is the optical absorption, V𝜋 is the voltage to reach a 𝜋 phase uration creates an SLG-insulator-silicon capacitor, allowing for
shift, and L is the modulator length. Among the mainstream ap- the gating of the graphene. While this approach does not re-
proaches including the plasma dispersion effect, III-V materials, quire a sophisticated junction design, it still necessitates the use
and LiNbO3 for integrated optical modulators, graphene-based of silicon for the waveguide and involves doping processes. To

Figure 12. Cross-sectional schematics of graphene-based silicon photonic modulators. a) SLG silicon photonic modulator. b) DLG silicon photonic
modulator.

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Table 5. Graphene-based silicon photonic EAMs.

Reference Type PIC process Graphene type Static modulation efficiency 3-dB Dynamic extinction ratio
[dB·μm−1 ·V−1 ] bandwidth
[GHz]

[238] SLG on p-doped Si rib EBL, non-planarized CVD-growth ≈25 × 10−3 1.2 n/a
waveguide
[239] SLG on n-doped Si rib DUV, planarized CVD-growth ≈13 × 10−3 5.9 Vpp = 2.5 V
waveguide
2.34 dB @ 10 Gbps
[240] SLG on n-doped Si rib DUV, planarized CVD-growth ≈7 × 10−3 ≈9.5 Vpp = 2.5 V
waveguide
≈1 dB @ 10 Gbps
[249] SLG on n-doped Si rib DUV, planarized CVD-growth ≈10 × 10−3 10.6–16.4 n/a
waveguide (300 mm wafer)
[242] DLG on undoped Si strip EBL, non-planarized CVD-growth ≈27 × 10−3 ≈1 n/a
waveguide
[243] DLG on a-Si strip EBL, non-planarized CVD-growth ≈2.7 × 10−3 35 n/a
waveguide
[244] DLG on undoped Si strip DUV, planarized CVD-growth ≈2.8 × 10−3 29 Vpp = 3 V
waveguide
≈1.7 dB @ 10 Gbps

≈1.3 dB @ 50 Gbps
[245] DLG on SiN RR DUV, planarized CVD-growth ≈50 × 10−3 30 n/a
[247] DLG on undoped Si PCW EBL, non-planarized CVD-growth ≈55 × 10−3 12 n/a
[248] DLG on undoped Si strip DUV, planarized Exfoliated ≈37 × 10−3 39 Vpp = 3.5 V
waveguide
≈5.2 dB @ 40 Gbps

eliminate the need for silicon and doping processes, a dual single- abling electro-absorption optical modulation.40 μm long EAM
layer graphene (DLG) structure has been proposed, as shown in provided a 4 dB static modulation depth under a 4 V bias, result-
Figure 12(b). In the DLG approach, the waveguide core can be ing in a static modulation efficiency of ≈25 × 10−3 dB·μm−1 ·V−1 .
made of any transparent material such as SiN or SiO2 . In this To assess the dynamic optical response of the SLG EAM, small
configuration, an SLG-insulator-SLG capacitor is placed on top signal measurements were conducted, and a 1.2 GHz 3-dB band-
of the waveguides. In the following sections, we will review the width was achieved at a −3.5 V bias.
development and state-of-the-art of graphene-based silicon pho- In 2016, the research team from IMEC and UGent demon-
tonic modulators. Table 5 summarizes the key parameters asso- strated, for the first time, SLG EAM with a standard 200 mm
ciated with these modulators. silicon photonics pilot line.[239] SOI wafers were patterned using
DUV lithography and then planarized through CMP. A 10 nm ox-
ide layer was left on top of the n-type doped silicon waveguide to
4.3. Graphene-based Silicon Photonic Modulators create the SLG-insulator-silicon capacitor. To further improve the
modulation efficiency, a quasi-TM waveguide with dimensions of
4.3.1. Graphene-based Silicon Photonic Electro-Absorption 220 nm in height and 750 nm in width was chosen to construct
Modulators the SLG EAMs (refer to Figure 13(b)). A 5.2 dB static modula-
tion depth was achieved for a 50 μm long SLG EAM, and the
The first graphene-based silicon photonic electro-absorption 3-dB bandwidth was increased to ≈5.9 GHz (0 V bias). Consid-
modulator (EAM) was demonstrated by Liu et al. from UC Berke- ering the voltage limits of CMOS drivers for future large-scale
ley in 2011.[238] A p-type doped silicon waveguide (250 nm in electrical-optical integration, a 2.5 V peak-to-peak (Vpp ) swing
height, 600 nm in width) was patterned using EBL on an SOI voltage was used for the eye-diagram measurements, and open
chip. Subsequently, a 40 μm long SLG structure was fabricated eye-diagrams were clearly observed at 10 Gbps for various wave-
on top of the silicon waveguide without planarization. The SLG lengths, demonstrating the capability for broadband operation.
structure consisted of a CVD-grown graphene and a 7 nm alu- Specifically, a dynamic extinction ratio (ER) of ≈2.34 dB was
minum oxide (Al2 O3 ) layer serving as the isolation layer (refer to achieved for 10 Gbps signals at 1550 nm (Vpp = 2.5 V). Addition-
Figure 13(a) for the schematic). The Al2 O3 layer was deposited ally, a thermal stability evaluation was conducted, demonstrat-
using atomic layer deposition (ALD) to minimize damage to the ing operation at ≈30 °C without the need for a thermoelectric
graphene. By applying a gating voltage between the graphene and cooler (TEC). The implementation of a standard silicon photonics
doped silicon, the Fermi level of graphene could be shifted, en- pilot line enables the large-scale integration of graphene-based

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Figure 13. RepresentatiWDM transmitters with multipleve SLG EAMs. a) SLG EAM on a silicon waveguide fabricated with EBL. Adapted with
permission.[238] Copyright 2011, Nature Publishing Group. b) SLG EAM on a silicon PIC fabricated in a silicon photonics foundry. Adapted with
permission.[239] Copyright 2016, Wiley-VCH. c) WDM transmitters with multiple SLG EAMs. Adapted with permission.[240] Copyright 2020, Optica
Publishing Group.

silicon photonic modulators and paves the way for graphene- icon waveguide, and a 5 nm thick layer of Al2 O3 was chosen as
based silicon photonic interconnects. Following this work, the the isolator between the two SLG sheets (refer to Figure 14(a)).
same research group demonstrated five-channel wavelength- A 6.5 dB static modulation depth was achieved by a 40 μm long
division multiplexing (WDM) transmitters with SLG EAMs.[240] DLG EAM under a 6 V bias, resulting in a static modulation ef-
A 10 nm thick Al2O3 layer was utilized as a top passivation layer ficiency of ≈ 27 × 10−3 dB·μm−1 ·V−1 . While the DLG EAM ex-
to enhance the robustness of SLG EAMs while reducing hys- hibited a 3-dB bandwidth of only ≈1 GHz, primarily attributed
teresis. With process improvements, a 100 μm long SLG EAM to the high series resistance (≈1 kΩ). This issue could potentially
achieved a 3-dB bandwidth of up to 9.5 GHz, and a total trans- be resolved by improving the metal-graphene contact. Later in
mitting rate of 125 Gbps (5 × 25 Gbps) was achieved using the 2016, the same research group presented a novel DLG EAM de-
CMOS-compatible Vpp = 2.5 V swing voltage, with a dynamic ER sign with a deposited amorphous silicon (a-Si) waveguide that
of ≈1 dB. operated in quasi-TM mode.[243] The 3-dB bandwidth was signifi-
To further improve the performance of graphene-based EAMs, cantly improved to 35 GHz. However, due to the use of a thick iso-
the concept of a dual-layer graphene (DLG) structure (refer to lation layer (120 nm thick Al2 O3 ) in the DLG EAM, the static mod-
Figure 12(b)) has been proposed to enhance the light-matter in- ulation efficiency was merely ≈2.7 × 10–3 dB·μm−1 ·V−1 , which ac-
teraction between graphene and the optical field. In the DLG counted for only ≈ 10% of their earlier reported DLG EAM.[242]
structure, two separate single-layer graphene (SLG) sheets inter- Following the pioneering works, Giambra et al. from CNIT
act with the optical modes. This approach offers enhanced light- made advancements in DLG EAMs using a standard SOI pi-
matter interaction[241] and provides the ability to gate graphene lot line.[244] Notably, they incorporated polycrystalline hexagonal
by applying a bias to the graphene-isolator-graphene capacitor, boron nitride (hBN) as a protective layer for the bottom graphene
eliminating the need for a doped silicon waveguide. This not only in the DLG EAM (refer to Figure 14(b)). Additionally, a metal con-
simplifies the PIC fabrication process but also introduces a new tact consisting of 7 nm of nickel (Ni) and 60 nm of gold (Au)
degree of freedom in selecting the waveguide core material, such was employed to mitigate the high series resistance. These im-
as SiN. provements resulted in the successful achievement of ≈ 1.7 and
In 2012, Liu et al. from UC Berkeley conducted the first ex- 1.3 dB dynamic ER at data rates of 10 Gbps and 50 Gbps, respec-
perimental demonstration of DLG EAMs on an SOI chip, which tively, using a Vpp = 3 V driving voltage. However, despite these
consisted of a 340 nm thick silicon layer and a 2 μm thick BOX advancements, this DLG EAM still exhibited a relatively low static
layer.[242] EBL was utilized to pattern a 400 nm wide undoped sil- modulation efficiency of ≈ ≈2.8 × 10−3 dB·μm−1 ·V−1 .

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Figure 14. Representative DLG EAMs. a) DLG EAM on a silicon waveguide fabricated with EBL. Adapted with permission.[242] Copyright 2012, American
Chemical Society. b) DLG EAM with hBN-encapsulated graphene on a silicon PIC fabricated via a silicon photonics CMOS pilot line. Adapted with
permission.[244] Copyrigh 2019, Optica Publishing Group. c) DLG EAM on a SiN PIC. Adapted with permission.[245] Copyright 2015, Nature Publishing
Group. d) DLG EAM with hBN-encapsulated graphene, which breaks through the dilemma between the static modulation efficiency and the 3-dB
bandwidth. Adapted with permission.[248] Copyright 2021, Nature Publishing Group.

To improve the static modulation efficiency, besides the stan- cally for DLG EAMs using the plane-wave expansion method.[247]
dard strip waveguide, several structures have been studied for The PCW consisted of air holes with a diameter of 193 nm in a
an enhancement of light-matter interaction inside DLG EAMs. 250 nm thick silicon layer, with a lattice constant of 390 nm. The
The first approach was building DLG EAMs with ring resonators PCW was patterned using EBL, and the BOX layer beneath the
(RRs). In 2015, Phare et al. from Cornell University designed and PCW was etched using buffered hydrofluoric acid. Subsequently,
implemented a DLG EAM with a SiN RR.[245] The SiN waveguide a 5 nm layer of Al2 O3 was deposited on the device using ALD
had a core width of 1000 nm and a height of 300 nm, with SiO2 to isolate the silicon waveguide and the bottom graphene. 10 μm
serving as both the top and bottom cladding to support single long DLG structure with a 28 nm Al2 O3 isolation layer was then
quasi-TE mode operation (see Figure 14(c)). The RR had a ra- fabricated on top of the suspended silicon PCW. Thanks to the
dius of 40 μm, and the coupling gaps varied between 200 and slow-light effect, the DLG EAMs achieved a remarkable static
900 nm. The waveguides were fabricated by depositing PECVD modulation efficiency as high as ≈55 × 10−3 dB·μm−1 ·V−1 , even
SiN at 400°C and subsequently patterned using 248 nm DUV with a compact length of 10 μm. However, the performance of
lithography. PECVD SiO2 was then deposited and planarized on the DLG EAMs at high speeds was hindered by the poor quality
the top surface of the waveguide using standard chemical me- of graphene caused by the rough surface of the Al2 O3 thin film.
chanical polishing (CMP) techniques. On top of the RR, a DLG The measured bandwidth of the DLG EAMs was 12 GHz.
structure with a 65 nm Al2 O3 isolation layer was fabricated, re- To address the limitations of DLG EAMs and explore their
sulting in a total length of ≈ 30 μm for the DLG EAM. Due to the experimental potential, Agarwal et al. from ICFO utilized hBN-
resonating structure of the RR, the DLG EAM exhibited a remark- encapsulated exfoliated graphene to construct DLG EAMs (see
able static modulation efficiency of ≈50 × 10−3 dB·μm−1 ·V−1 . Fur- Figure 14(d)). The DLG structure, measuring ≈60 μm in length,
thermore, a 3-dB bandwidth of ≈30 GHz was measured under a consisted of a 10 nm thick layer of hafnium oxide (HfO2 ) fab-
−30 V bias, showcasing the high-speed performance of the RR- ricated on top of a standard undoped silicon waveguide oper-
based DLG EAM. ating at quasi-TM polarization (220 nm in height and 750 nm
Another popular approach to enhance the interaction between in width).[248] The silicon waveguide was fabricated on IMEC’s
light and graphene is by utilizing the slow-light effect.[246] Cheng 200 mm silicon photonics line, and the DLG EAM was pre-
et al. from Huazhong University of Science and Technology de- pared using an EBL-based laboratory process. By incorporat-
signed a slow-light photonic crystal waveguide (PCW) specifi- ing hBN-encapsulated exfoliated graphene and HfO2 , the device

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demonstrated both a ≈40 GHz 3-dB bandwidth and a static mod- phase modulator with a 5 GHz 3-dB bandwidth.[251] It has an SLG
ulation efficiency of ≈37 × 10−3 dB·μm−1 ·V−1 . These results rep- structure on top of a silicon MZI. The silicon photonic chip was
resent a significant breakthrough in reconciling the trade-off be- fabricated using IMEC’s iSiPP25G silicon photonics platform.
tween static modulation efficiency and 3-dB bandwidth. Addi- The CVD-grown graphene was then transferred and patterned
tionally, this DLG EAM achieved a world-record 5.2 dB dynamic on top of the silicon MZI, which had a waveguide cross-section
ER at 40 Gbps, using a Vpp = 3.5 V swing voltage. of 220 nm in height and 480 nm in width (refer to Figure 15).
Currently, graphene-based silicon photonic modulators have The waveguide was p-type doped, and a 10 nm SiO2 spacer was
demonstrated superior performance compared to those based on placed between the silicon waveguide core and graphene to cre-
the plasma dispersion effect. However, one of the key challenges ate a capacitor. Utilizing the MZI configuration, an impressive
in implementing graphene-based silicon photonic modulators is static modulation depth of ≈ 35 dB was easily achieved, result-
achieving high-yield manufacturing with wafer-level integration. ing in a V𝜋L value of ≈ 0.28 cm·V. This V𝜋L value surpassed
Wafer-level integration involves fabricating and integrating mul- that of conventional high-speed silicon photonic phase modula-
tiple devices on a single wafer, allowing for efficient and cost- tors, which typically operate in the depletion mode and have V𝜋L
effective production. It requires precise control over the fabrica- values larger than 1 cm·V. The exceptional V𝜋L value allowed
tion processes, including graphene growth, transfer, patterning, the SLG phase modulator to achieve a dynamic ER of 3.94 dB
and integration with other photonic components on the wafer. at 10 Gbps using only a Vpp = 2 V driving voltage. Additionally, it
Researchers and industry are actively working to address these enabled error-free operation for transmission distances of up to
challenges.[100] Recently, the research team from IMEC demon- 50 km when combined with state-of-the-art systems employing
strated SLG EAMs integrated on 300 mm SOI wafers. The inte- soft-decision forward error correction (SD-FEC).
gration is based on IMEC’s 300 mm silicon photonics platform While the SLG silicon photonic phase modulator represents a
and the full integration sequence is using standard CMOS pro- significant breakthrough, it still relies on a doped silicon waveg-
duction tools.[249] The use of 300 mm wafers and standard CMOS uide, introducing unwanted loss. The DLG configuration would
production tools is significant because it allows for large-scale be an ideal choice for constructing graphene-based silicon pho-
manufacturing and enables compatibility with existing semicon- tonic phase modulators. DLG not only boasts the best figure of
ductor fabrication processes. By leveraging IMEC’s silicon pho- merit for phase modulators[100] but can also be integrated with
tonics platform and utilizing standard CMOS tools, the integra- passive waveguides, such as SiN waveguides. However, to date,
tion of SLG EAMs on 300 mm wafers becomes more practical there have been no reports on the experimental demonstration
and commercially viable. This advancement in integration tech- of DLG silicon photonic phase modulators. One possible issue
nology paves the way for the mass production of graphene-based is the requirement of applying a high bias on the DLG to sig-
silicon photonic modulators with improved yield, scalability, and nificantly shift the graphene Fermi level (e.g., Ef > 0.6 eV), which
cost-effectiveness. This development brings graphene-based sil- could potentially lead to the breakdown of the SLG-insulator-SLG
icon photonic modulators closer to commercialization, and the capacitor. Additionally, precise control of the two SLG layers in a
successful high-yield manufacturing of these modulators will en- DLG is a challenging task. Nevertheless, DLG silicon photonic
able their widespread deployment and integration into various phase modulators, especially those built on passive waveguides,
photonic systems and applications. are highly sought after by the research community. They hold
the potential to greatly benefit applications such as microwave
photonics[252–254] and on-chip nonlinear optics,[255–257] contribut-
4.3.2. Graphene-based Silicon Photonic Phase Modulators ing to the prosperity of the silicon photonics field.

As shown in Figure 11(b), 𝜖″G becomes relatively small when

Ef >0.6 while 𝜖′G still varies significantly. This implies that nearly 4.3.3. Graphene-based Silicon Photonic Plasmonic Modulators
pure phase modulation can be achieved with graphene, sur-
passing conventional silicon photonic modulators based on the Traditional graphene-based silicon photonic modulators face a
plasma dispersion effect. Consequently, there is a high demand challenge due to limited light-matter interaction caused by the
for graphene-based silicon photonic phase modulators in the mode mismatch between the relatively large optical modes,
community. which are hundreds of nanometers in size, and the atomic-thin
In 2015, the research group from Applied Micro- and Opto- graphene layer. In a typical silicon waveguide, the field diame-
electronics (AMO) reported their observation about phase mod- ter of an optical mode is approximately four orders of magni-
ulation capabilities of graphene. In their device, a DLG structure tude larger than the thickness of graphene.[258] To address this
with a 90 nm thick Al2 O3 was fabricated on top of one arm of issue, plasmonic waveguides offer a promising solution. They
a MZI.[250] The MZI is fabricated on a standard 220 nm thick can break the diffraction limit and achieve subwavelength con-
SOI platform. To partially planarize the silicon PIC for graphene finement of light,[259–261] which can help overcome the mismatch
integration, a layer of hydrogen silsesquioxane (HSQ) was spin- between the optical field and graphene.
coated. In their experiment, it was observed that the figure of In 2015, Ansell et al. conducted an experimental demonstra-
merit Δn/Δ𝛼 for graphene was a factor of 10 smaller compared tion of graphene-based plasmonic waveguide modulators.[262]
to silicon-based modulators that operate using the plasma disper- They fabricated gold plasmonic strip waveguides with gratings
sion effect. using EBL. These gratings were designed to optimize perfor-
Later in 2018, Sorianello et al. from CNIT for the first time mance for normal incident light at 1.5 μm. Graphene/hBN flakes
demonstrated a high-speed graphene-based silicon photonic were obtained through traditional mechanical exfoliation and

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Figure 15. Graphene-based silicon photonic phase modulator Adapted with permission.[251] Copyright 2018, Nature Publishing Group. a) Optical mi-
crograph of the MZI modulator. b) Cross-section of the modulator through the dashed line A–A′ of (a). c) Extinction ratio at the bar-port of the MZI
modulator at 1550 nm. d) Electro-optical bandwidth of the MZI modulator. e) Eye diagram of the MZI modulator measured at 10 Gbps with 231 − 1
pseudo-random bit sequence (PRBS) non-return-to-zero (NRZ) patterns.

then transferred onto the metal waveguides, which could be di- Later, in 2018, Huang et al. updated their design by introducing
rectly utilized to modulate the graphene (See Figure 16(a)). They localized plasmon resonance to further enhance the performance
achieved a modulation depth of ≈33 × 10−3 dB·μm−1 with a mod- of the graphene-based silicon photonic plasmonic modulator.[266]
ulation efficiency ≈3.6 × 10−3 dB·μm−1 ·V−1 in a device that was They proposed a localized plasmonic-enhanced graphene modu-
over 100 μm long. These figures of merit lag behind their sili- lator. In this design, nanoscale metal structures were placed on
con photonic counterparts. Moreover, the low coupling efficiency top of a silicon waveguide (See Figure 16(c)). The plasmon reso-
of normal incident grating and high metal absorption pose chal- nance of these structures could be adjusted via electrostatic gat-
lenges for the implementation of such graphene plasmonic mod- ing of graphene. Silver was chosen as the representative metal for
ulators. Thus, hybridizing plasmonics and silicon photonics has this study, but it could be substituted with other metals to achieve
emerged as a promising alternative. a similar effect. Due to the localized plasmon resonance, the over-
In 2016, Huang et al. proposed a low-loss and high-speed lapping area between the graphene and the silicon waveguide was
graphene-based silicon photonic plasmonic modulator on a only 500 nm × 400 nm, with a predicted theoretical bandwidth of
hybrid silicon-plasmonic waveguide.[263] In their design, they up to 400 GHz. Furthermore, a 1 V driving voltage could result
placed a double-layer graphene (DLG) structure with Al2 O3 as in ≈ a 6 dB ER, equivalent to ≈1200 × 10−3 dB·μm−1 ·V−1 static
the spacer layer on top of a horizontal Si-Ag hybrid plasmonic modulation efficiency. However, it’s important to note that the
waveguide (See Figure 16(b)). To facilitate the coupling between resonant structure limits the operational wavelength of the mod-
the silicon waveguide and the hybrid plasmonic waveguide for ulator and contradicts the unique broadband optical properties of
triggering surface plasmon polaritons (SPP), they employed a graphene.
silicon taper. Since graphene is sensitive to the tangential elec- To further enhance the light-matter interaction between
tric field[262,264,265] due to its anisotropic property, the hybrid graphene and optical mode fields, Wang et al. proposed the use
plasmonic waveguide was designed for quasi-TE mode opera- of a metal nanoparticle chain (MNC) to strongly confine in-plane
tion to enhance the interaction between horizontal graphene electric field components.[267] They designed a subwavelength-
and the optical field. Their proposed device could achieve an scale graphene-based silicon photonic plasmonic modulator in
ER of 3 dB with less than 1 dB insertion loss in a compact which an MNC is placed on top of a silicon waveguide. A layer
8.5 μm long device. It had a theoretical bandwidth of up to of graphene/hBN is positioned between them, where the in-
400 GHz, although it required a driving voltage as high as plane electric field components are expected to be maximized
12 V. (See Figure 16(d)). The MNC can achieve an ultra-high in-plane

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Figure 16. a) Graphene-metal plasmonic modulators. Adapted with permission.[262] Copyright 2015, Nature Publishing Group. Graphene-based sili-
con photonic plasmonic modulators with b) a hybrid silicon-plasmonic waveguide (Adapted with permission.[263] Copyright 2016, Optica Publishing
Group.), c) a localized plasmon resonance structure (Adapted with permission.[266] Copyright 2018, Optica Publishing Group.), d) a metal nanoparticle
chain (Adapted with permission.[267] Copyright 2019, Institute of Electrical and Electronics Engineers.), and e) an orthogonal hybrid silicon-plasmonic
waveguide (Adapted with permission.[268] Copyright 2020, De Gruyter and Science Wise Publishing.).

confinement of the electric field, with a confinement ratio over a subwavelength scale, which also implies the need to control the
1000 times higher compared to a silicon waveguide without the geometry of these structures at a similar level. Precisely fabricat-
MNC. Due to this ultra-high confinement, a modulation depth of ing these plasmonic structures with guaranteed performance is a
20.9 dB·μm−1 modulation depth could be achieved by a 1.05 μm significant challenge. Furthermore, integrating metal processes
long modulator under a 7.25 V driving voltage, resulting in a in the FEOL of a silicon photonic platform is very difficult. How-
very high static modulation efficiency ≈2880 × 10−3 dB·μm−1 ·V−1 . ever, with the advances in nanofabrication techniques, we can an-
However, the theoretical bandwidth estimated from the capaci- ticipate that high-performance graphene-based silicon photonic
tance and resistance drops to ≈39 GHz. plasmonic modulators will eventually be realized.
In 2020, Sun et al. proposed an orthogonal hybrid silicon-
plasmonic waveguide for silicon photonic plasmonic modula- 5. Graphene-based Silicon Photonic
tors, enabling the realization of both ultra-high modulation ef- Photodetectors
ficiency and ultra-high bandwidth simultaneously.[268] The hy-
brid silicon-plasmonic waveguides are arranged in two orthog- 5.1. Fundamentals of Silicon Photonic Photodetectors
onal directions on the cross-section of the proposed modulator
(See Figure 16(e)). This configuration allows for the confinement A photodetector is an essential component of silicon photon-
of optical mode fields and reduces the size of the modulator. After ics that converts optical signals into electrical signals. To assess
optimizing the parameters, they achieved a remarkable modula- the performance of a photodetector, three key figures of merit
tion efficiency of ≈10 234 × 10−3 dB·μm−1 ·V−1 with a bandwidth (FOMs) are commonly used. The first one is responsivity, mea-
of ≈462 GHz in a 3 μm long modulator. sured in units of A W−1 (amperes per watt). Responsivity indi-
While graphene-based silicon photonic plasmonic modulators cates the amount of electrical current generated per unit of optical
have been predicted to outperform traditional graphene-based power coupled into the photodetector. For photodetectors built
silicon photonic modulators, limited experimental results reveal with semiconductors, responsivity often varies with wavelength.
that several challenges exist in implementing these promising The second one is bandwidth, which signifies the speed at which
designs. For instance, plasmonic structures can confine light on a photodetector can respond to changes in optical power. The

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Figure 17. a) Normal incidence, b) butt coupling, and c) evanescent coupling configurations of Ge photodetectors. Ge photodetectors with d) lateral
homojunction, e) lateral heterojunction, and f) vertical heterojunction PINs.

3-dB bandwidth is widely adopted as a standard, representing the lenging to simultaneously enhance light absorption, which re-
frequency at which the response of a photodetector is attenuated quires a thicker Ge layer, and reduce carrier transition time,
by half. The last one is the dark current, which refers to the cur- which prefers a thinner Ge layer. To overcome this trade-off,
rent generated by a photodetector in the absence of input optical waveguide-coupled photodetectors have been introduced. Typi-
power. Minimizing dark current is crucial to reduce noise in a cally, light is guided by a silicon waveguide and then coupled
photodetector. through butt coupling[16] (see Figure 17(b)) or evanescent cou-
It would be ideal if silicon could be directly used as the ma- pling to a Ge region[273–275] (see Figure 17(c)). The Ge region
terial for photodetectors, as it would greatly reduce the complex- typically has a PIN structure, with the intrinsic absorption re-
ity of fabrication. Unfortunately, silicon is an inefficient light ab- gion sandwiched between doped p-type and n-type regions. Three
sorber in bulk at datacom wavelengths (C-band and O-band) due mainstream configurations of the PIN structure have been imple-
to its relatively large bandgap of 1.12 eV, which corresponds to the mented: lateral homojunction,[276] lateral heterojunction,[277] and
energy of a photon at ≈ 1107 nm. As a result, other techniques vertical heterojunction[18] (see Figure 17(d,e)). The homojunction
such as III-V material bonding,[269] plasmonics,[270] and epitax- enables bias-free operation but suffers from low responsivity. The
ial Ge growth[271] have been developed to build photodetectors heterogeneous counterparts can significantly enhance the con-
in silicon photonics. Among these approaches, epitaxially grown finement of optical modes in the intrinsic region, thereby increas-
Ge has emerged as the dominant technology for silicon photonic ing the responsivity. In the lateral heterojunction, a high voltage
photodetectors due to its CMOS compatibility, along with its rela- must be applied to sweep the carriers out of the intrinsic region
tively high responsivity (0.8–1.1 A W−1 ), small footprint, and high in a timely manner, as the two metal contacts for the p-type and n-
speed (>40 GHz 3-dB bandwidth).[17] type regions are both at the top. On the other hand, in the vertical
While Ge is a CMOS-compatible material and can be grown heterojunction, the required bias can be significantly reduced to
in CMOS pilot lines using CVD, the large lattice mismatch meet the CMOS-compatible driving voltage requirements. A re-
(≈4%) poses severe challenges in achieving high-quality Ge film verse bias of 1–2 V is sufficient for most vertical heterojunction
growth on silicon. What is wore, the low thermal budget of Ge Ge photodetectors. However, in the vertical approach, the current
presents significant hurdles in the silicon photonics process. The generated by the intrinsic absorption region has to travel across
fabrication-induced defects can lead to a remarkable increase the Si/Ge interface, resulting in higher dark current and lower
in the dark current of Ge photodetectors. Extensive efforts have responsivity due to interfacial defects.
been dedicated to addressing these issues, particularly the lattice
mismatch. A widely adopted solution is the utilization of a low-
temperature SiGe or Ge buffer layer, which helps confine the de- 5.2. Graphene-based Silicon Photonic Photodetectors
fects to a small region and provides support for a low-defect top
layer for photodetectors.[272] The spectral bandwidth of a photodetector is typically determined
Two configurations of Ge photodetectors are commonly used by the band gap of the materials.[93] Ge and III-V materials,
in silicon photonics. The first one is the normal incidence con- for example, have limited absorption for photons with energies
figuration, where the optical signals from optical fibers or free- smaller than their respective band gaps. However, graphene,
space directly couple into the photodetectors, as illustrated in with its zero-bandgap nature, exhibits frequency-independent
Figure 17(a). The normal incidence configuration has a simple absorption.[278] This unique characteristic allows graphene to ab-
structure, but it suffers from an intrinsic dilemma: it is chal- sorb light across a wide range of frequencies, spanning from

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Figure 18. Graphene-based silicon photonic photodetectors. a) The SLG photodetector on HSQ planarized silicon waveguide. Adapted with
permission.[287] Copyright 2014, American Chemical Society. b) The SLG photodetector with hBN-encapsulated graphene. Adapted with permission.[288]
Copyright 2015, American Chemical Society. c) The SLG photodetector on SiN waveguide. Adapted with permission.[289] Copyright 2015, American In-
stitute of Physics. d) The SLG photodetector on SiN waveguide with a metal contact. Adapted with permission.[290] Copyright 2018, Optica Publishing
Group. e) The SLG photodetector on SiN waveguide with interdigital metal contacts. Adapted with permission.[291] Copyright 2018, American Institute
of Physics.

UV to far-IR regimes, using a single material. Furthermore, figuration. In 2014, Schall et al. from AMO demonstrated an
the exceptional carrier mobility of graphene enables ultrafast SLG photodetector on top of a silicon waveguide[287] (see Figure
photo-detection. In recent developments, graphene-based pho- 18(a)). The SLG was transferred onto an HSQ partially pla-
todetectors integrated with metamaterial perfect absorbers have narized silicon waveguide using a PMMA method. Subsequently,
showcased bandwidths exceeding 500 GHz.[279] These advance- a 30 μm long SLG absorption region was patterned with oxygen
ments highlight the potential of graphene-based silicon photonic plasma, which absorbed ≈ 35% of the incident light. The op-
photodetectors in achieving high-speed photodetection across a eration speed of the SLG photodetectors was quantified using
broad spectrum. a heterodyne measurement method, and a 41 GHz 3-dB band-
The working principle of a graphene-based photodetector dif- width was achieved. However, the responsivity of the SLG pho-
fers from that of a semiconductor with a band gap. In graphene, todetectors was relatively small, ranging from 0.006 to 0.046 A
the generation of photocurrent can be attributed to two main W−1 , which is much lower than that of typical Ge photodetec-
effects: the photovoltaic effect and the photo-thermoelectric tors. However, graphene-based photodetectors offer the distinct
effect.[92,280,281] The photovoltaic effect relies on the presence of advantage of operating without bias, rendering them immune to
a built-in electric field in the graphene material. When photons the effects of a dark current. This represents a notable advance-
are absorbed, electron-hole pairs are created, and the built-in elec- ment compared to Ge photodetectors. Later in 2015, Shiue et al.
tric field separates them, resulting in a photocurrent. On the from MIT successfully increased the responsivity to 0.35A W−1
other hand, the photo-thermoelectric effect occurs when there is by utilizing hBN-encapsulated graphene[288] (see Figure 18(b)).
a photon-induced temperature gradient across an interface be- To optimize the transfer process, the silicon PIC was planarized
tween two materials with different Seebeck coefficients. This ef- with CMP, and the vdW assembly approach was used to trans-
fect leads to the generation of a local photovoltage in graphene. fer the hBN/SLG/hBN stack. In addition to the improved respon-
Compared to conventional photovoltaic detectors which generate sivity, the photodetector also exhibited a high 3-dB bandwidth of
a photocurrent, graphene-based photodetectors have the advan- 42 GHz.
tage of directly generating a voltage. This means that the compli- Graphene-based photodetectors also offer a promising solu-
cated transimpedance amplifier (TIA) typically required to con- tion for photodetection in SiN PICs as they do not require Ge
vert the photocurrent into a voltage in optical transceivers may epitaxy. In 2015, Wang et al. from The Chinese University of
be replaced by a simpler voltage amplifier. This potential simpli- Hong Kong demonstrated graphene-based photodetectors on top
fication can contribute to reducing costs and power consumption of SiN waveguides.[289] The SLG photodetector configuration in-
in next-generation optical interconnects.[100] volved a metal-SLG-metal structure (see Figure 18(c)). The SLG
On-chip integrated graphene photodetectors compatible with photodetector exhibited a responsivity of 0.126 A W−1 , but its
silicon photonics have been reported in several studies.[282–286] bandwidth was limited to only 1 KHz. The authors attributed
These photodetectors typically utilize a normal incidence con- the slow response to the large capacitance of the metal contacts

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Table 6. Graphene-based silicon photonic detectors.

Reference Type Responsivity [A W−1 ] 3-dB bandwidth [GHz]

[287] SLG on Si waveguide 0.006–0.064 41

[288] SLG on Si waveguide 0.35 42
[289] SLG on SiN waveguide 0.126 0.001
[290] SLG on SiN waveguide 0.015 30
[291] SLG on SiN waveguide 0.032 ≈33

used in the device. In 2018, the same research team employed a performance and integration capabilities are expected, making
metal-graphene junction on top of a SiN waveguide to enhance graphene an exciting prospect for the future of photodetection in
the light-matter interaction between graphene and the optical silicon photonics.
mode[290] (see Figure 18(d)). This approach resulted in a substan-
tial increase in the 3-dB bandwidth of the SLG photodetectors 6. Summary and Outlook
to 30 GHz. However, the responsivity of the photodetectors de-
creased to 0.015 A W−1 . Furthermore, the researchers proposed The telecom and datacom industries are indeed facing a signifi-
and demonstrated SLG photodetectors on SiN waveguides with cant increase in bandwidth requirements due to the “Zettabyte
interdigital metal contacts to improve the performance[291] (see Era” and the emergence of 5G communication driven by the
Figure 18(f)). These photodetectors exhibited a relatively high re- Internet of Things (IoT). To address this demand while also
sponsivity of 0.032 A W−1 and a bandwidth of ≈ 33 GHz. Table 6 considering environmental concerns, it is crucial to make ad-
provides a summary of the aforementioned graphene-based sil- vancements in photonics hardware for high-performance op-
icon photonic detectors. It is observed that the graphene-based tical interconnects. Graphene-based silicon photonics offers a
photodetectors on SiN waveguides generally have worse perfor- promising solution in this evolving landscape. By combining
mance compared to those on silicon waveguides, which can be graphene with silicon photonics, it becomes possible to achieve
explained by a weaker light-matter interaction in SiN waveguides. enhanced performance in optical interconnects. One key advan-
While graphene-based silicon photonic detectors currently do tage of graphene-based silicon photonics is its capability for post-
not exhibit comparable performance to Ge photodetectors, which processing on a passive PIC. This means that active function-
typically possess a responsivity of 0.8–1.1 A W−1 with a band- alities such as modulation and detection can be realized by in-
width exceeding 50 GHz, the unique characteristics of graphene corporating graphene-based silicon photonic devices onto pas-
make it a promising candidate for photodetectors in silicon pho- sive waveguides. The separation of the PICs for optical guiding
tonics. Graphene offers an impressive ultra-high bandwidth ca- from active functionalities results in a technology that does not
pability, with experimental demonstrations surpassing 500 GHz. necessitate a full integration approach, which is not tightly linked
Additionally, one of the key advantages of graphene is its sim- to conventional CMOS processing and provides more freedom
ple fabrication process, which eliminates the need for complex for optical designers. On the other hand, due to their compact
epitaxy and doping processes. This simplicity streamlines the size, broadband operational capabilities, and compatibility with
production of graphene-based silicon photonic photodetectors, CMOS-standard driving voltages, graphene-based silicon pho-
making them more accessible and potentially cost-effective for tonic modulators, and detectors have the potential to meet the
practical applications in various fields. Moreover, the integra- increasing demands of the next generation of data communica-
tion of graphene-based detector arrays with CMOS electronics tion.
has been successfully demonstrated.[292] This achievement high- While graphene-based silicon photonics offers a synergistic
lights the compatibility of graphene with CMOS technology, al- blend of benefits in terms of both performance and manufac-
lowing for the seamless integration of graphene-based detec- turing, it remains crucial to maintain the ultrahigh carrier mo-
tors with existing electronic systems. This integration opens up bility of graphene, which serves as the foundation for achieving
new possibilities for the development of advanced and compact high-performance graphene-based silicon photonic modulators
photonic devices with enhanced functionalities and improved and photodetectors. Achieving this high mobility can be facili-
performance. Finally, graphene stands out as a highly promis- tated through the use of single crystals, optimized transfer pro-
ing material for the development of ultra-broadband photode- cesses, and encapsulation techniques. It is imperative to combine
tectors. One of its most remarkable attributes lies in its gap- these aspects with an optimized process that minimizes contact
less band structure.[278] For instance, graphene-based photode- resistance. The remaining fabrication steps for graphene align
tectors with ultra-broadband operation from visible to the mid- with those used for silicon and SiN PICs.
infrared range and high responsivity(>1A W−1 ) at room temper- Considering these factors, we believe that graphene-based sil-
ature have been successfully demonstrated.[286] This remarkable icon photonics offer a unique and promising pathway for the de-
combination of ultra-broadband sensitivity and high responsivity velopment of optical interconnects. By leveraging the advantages
positions graphene-based photodetectors as leading contenders of graphene, it becomes possible to enhance the performance and
in various applications, including telecommunications, imaging, capabilities of optical communication systems, paving the way
sensing, and beyond. As research and development in graphene- for future advancements in high-speed, energy-efficient, and en-
based photodetectors continue, further advancements in their vironmentally friendly optical interconnect technologies.

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Zheng Wang received his B.S. degree in Mathematics and Physics from Tsinghua University and his
Ph.D. in Materials Sciences and Engineering from The University of Texas at Austin. He is currently an
Associate Professor in Microelectronics and Solid-state Electronics at the Shanghai Institute of Mi-
crosystem and Information Technology (SIMIT), Chinese Academy of Sciences (CAS). Before joining
SIMIT, CAS, he served as a Deputy Director at the Shanghai Industrial Technology Research Institute
and worked as an R&D Project Leader at IMEC in Belgium. His research primarily focuses on photonic
integrated circuits and low-dimensional materials.

Zengfeng Di received his B.S. degree in Biochemistry from Nanjing University and his Ph.D. in Micro-
electronics and Solid-state Electronics from the Shanghai Institute of Microsystem and Information
Technology (SIMIT), Chinese Academy of Sciences (CAS). He is currently a Professor in Microelec-
tronics and Solid-state Electronics, the Director of the National Key Laboratory of Materials for Inte-
grated Circuits at SIMIT, CAS, and the Deputy Director of SIMIT, CAS. Prior to joining SIMIT, CAS, he
worked as a Director’s Postdoctoral Fellow at the Los Alamos National Laboratory in the United States.
His research interests encompass advanced silicon-on-insulator materials, two-dimensional materi-
als, as well as microelectronic and optoelectronic devices.

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