COMPLEX ENGINEERING PROBLEM

COMPUTER ARCHITECTURE

Submitted By:
GROUP#1
2020-EE-626
2020-EE-634(L)
2020-EE-642
Submitted To:
Engr. Osama Bin Naeem

DEPARTMENT OF ELECTRICAL ENGINEERING

UNIVERSITY OF ENGINEERING AND TECHNOLOGY
LAHORE, NAROWAL CAMPUS
 DESIGN OF 32-BIT R-TYPE PROCESSOR
1. INTRODUCTION
The aim of this report is to present the design and implementation of a 32-bit RISC R-type
processor with three-stage pipelines. The report provides a comprehensive overview of the
design process, including the choice of instruction set architecture (ISA), the design of the
processor's datapath and control unit, and the implementation of the processor using Verilog
HDL.The report also covers the testing and verification of the processor, including the use of
simulation and functional verification techniques to ensure that the processor functions correctly.
Finally, the report discusses the performance of the processor, including its clock frequency,
power consumption, and other relevant metrics.

Figure 1-1 3 Stage Pipelining

2. 3 STAGE PIPELINE
A pipeline is a technique used in computer architecture to increase the throughput of a processor
by dividing the execution of instructions into multiple stages. A 3-stage pipeline is a type of
pipeline in which the instruction execution is divided into three stages: fetch, decode, and
execute. Here are the details of each stage:

a. Fetch stage:
In this stage, the processor fetches the instruction from the memory. The program
counter (PC) is used to determine the address of the instruction to be fetched, and the
instruction is then read from memory into the instruction register (IR). At the end of this
stage, the PC is incremented to point to the next instruction.
b. Decode stage:
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 In this stage, the processor decodes the instruction that was fetched in the previous stage.
The instruction is decoded to determine the operation to be performed and the operands
involved. The instruction decoder generates control signals that are used to control the
datapath and the execution of the instruction.
c. Execute stage:
In this stage, the processor performs the operation specified by the instruction. This
involves accessing the required operands from the registers or memory, performing the
operation, and storing the result in the appropriate register or memory location. At the
end of this stage, the pipeline is ready to fetch the next instruction.

3. EXPLANATION
The design and implementation of a 32-bit RISC R-type processor with three-stage pipelines
involves several key components and considerations. Here is an overview of the main aspects
involved:
a. Instruction Set Architecture (ISA):
The first step in designing the processor is to select an appropriate ISA that defines the
instructions that the processor will support. A RISC (Reduced Instruction Set Computer)
ISA is often used for this purpose as it provides a simpler and more regular instruction set
that is easier to decode and execute.
b. Datapath design:
The datapath of the processor is responsible for performing the actual computation and
data movement operations required by the instructions. The datapath consists of a set of
registers, an arithmetic logic unit (ALU), and other functional units such as a memory
unit. The datapath is divided into three stages, each of which is responsible for a specific
part of the instruction execution.
c. Control unit design:
The control unit is responsible for generating the control signals required to control the
datapath and execute the instructions correctly. The control unit receives the instruction
from the instruction register and decodes it to generate the appropriate control signals for
the datapath.
d. Pipelining:
The three-stage pipeline is used to increase the throughput of the processor by allowing
multiple instructions to be executed simultaneously. Each instruction is executed in three
stages, allowing the processor to execute up to three instructions simultaneously.
e. Verification and testing:
The processor design is thoroughly verified and tested using simulation and functional
verification techniques to ensure that the processor functions correctly and meets the
design requirements.
f. Implementation:
The processor is implemented using a hardware description language such as Verilog
HDL. The design is synthesized, placed and routed to produce a physical layout that can
be fabricated into a chip.
Overall, the design and implementation of a 32-bit RISC R-type processor with three-stage
pipelines requires a thorough understanding of computer architecture, digital logic design, and

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hardware description languages. It is a complex process that involves careful consideration of the
design trade-offs and requires expertise in several areas of computer engineering. However, with
careful planning and attention to detail, it is possible to produce a high-performance and reliable
processor that meets the requirements of a wide range of applications.

4. XILINX SIMULATIONS
Code:
module RISCV(
input wire clk,
input wire reset,
input wire [31:0] instruction,
output reg [31:0] result
);

// Register File
reg [31:0] reg_file [31:0];
wire [31:0] rs1_data, rs2_data;
reg [4:0] wr_addr;
reg [31:0] wr_data;

// Register File Read

assign rs1_data = reg_file[instruction[19:15]];
assign rs2_data = reg_file[instruction[24:20]];

// ALU
reg [31:0] alu_out;
always @* begin
case (instruction[6:0])
7'b0110011: alu_out = rs1_data + rs2_data; // ADD
7'b0010011: alu_out = rs1_data - rs2_data; // SUB
7'b0000011: alu_out = rs1_data & rs2_data; // AND
7'b1100011: alu_out = rs1_data | rs2_data; // OR
7'b1110011: alu_out = rs1_data ^ rs2_data; // XOR
default: alu_out = 0;
endcase
end

// Control Unit
wire [2:0] alu_op;
wire [4:0] reg_wr_addr;
wire [31:0] reg_wr_data;

// Control Signal Assignments

assign alu_op = instruction[6:0];
assign reg_wr_addr = instruction[11:7];
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 assign reg_wr_data = alu_out;

// Writing to Register File

always @(posedge clk) begin
if (reset) begin
wr_addr <= 0;
wr_data <= 0;
end
else begin
wr_addr <= reg_wr_addr;
wr_data <= reg_wr_data;
end
reg_file[wr_addr] <= wr_data;
end

// Output
always @(posedge clk) begin
if (reset)
result <= 0;
else
result <= alu_out;
end

endmodule
Xilinix Simulations:

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 Figure 4-2 RTL Schmetic

COMPLETE SCREENSHOT

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CONCLUSION
The three-stage pipeline architecture provides a good balance between performance and
complexity for RISC processors. With the fetch, decode, and execute stages split into separate
pipeline segments, the processor can achieve high clock rates and low latency without requiring
extensive hardware resources.The R-type instruction set is a widely used and versatile set of
commands that can handle many common operations in computer arithmetic and logic. By
implementing a processor that supports this instruction set, designers can ensure compatibility
with existing software and tools that rely on RISC architectures. The use of Verilog HDL and
FPGA technology offers a flexible and cost-effective way to prototype and test processor
designs. By simulating the processor behavior and running test programs on an FPGA-based
board, designers can validate the correctness and performance of the design before committing to
a full-scale fabrication.The implementation of a 32-bit RISC processor with three-stage pipelines
can serve as a basis for further optimization and customization. By tweaking the pipeline stages,
adding specialized hardware units, or integrating additional instruction sets, designers can tailor
the processor to specific applications or performance goals.
Overall, the study on designing and implementing a 32-bit RISC R-type processor with three-
stage pipelines demonstrates the feasibility and advantages of using a streamlined architecture
and standardized instruction set for building efficient and adaptable processors. The findings can
be useful for researchers, engineers, and educators who are interested in computer architecture,
digital design, or embedded systems

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