UNIT I

INTRODUCTION TO 8085 ARCHITECTURE

1.With the help of neat diagram explain the architecture of 8085
microprocessor in detail.

 8085 consists of various units as shown in Figure and

each unit performs its own functions. The various units of a microprocessor are listed
below
 Accumulator
 ArithmeticandlogicUnit
 Generalpurposeregister
 Programcounter
 Stackpointer
 Temporaryregister
 Flags
 InstructionregisterandDecoder
 TimingandControlunit
 Interruptcontrol
 AddressbufferandAddress-Databuffer
 Address bus andDatabus
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Accumulator
 Accumulator is nothing but a register which can hold 8-bit data. Accumulator aids
in storing two quantities. The data to be processed by arithmetic and logic unit is
stored in accumulator.
 It also stores the result of theoperation carried out by the Arithmetic and Logic
unit. The accumulator is alsocalled an 8-bit register.
 The accumulator is connected to Internal Data bus andALU (arithmetic and logic
unit). The accumulator can be used to send or receivedatafromthe Internal Data
bus.

ArithmeticandLogicUnit
 There is always a need to perform arithmetic operations like +, -, *, / and
toperform logical operations like AND, OR, NOT etc. So, there is a necessity
forcreating a separate unit which can perform such types of operations.
TheseoperationsareperformedbytheArithmeticandLogicUnit(ALU).
 ALUgetsitsinputfromaccumulatorandtemporaryregister.Afterprocessingthenecess
aryoperations,theresultisstoredbackinaccumulator.

GeneralPurposeRegisters
 Apart from accumulator 8085 consists of six special types of registers
calledGeneral Purpose Registers. These general-purpose registers are used to
holddata like any other registers.
 The general-purpose registers in 8085 processorsare B, C, D, E, H and L. Each
register can hold 8-bit data. Apart from the abovefunction these registers can
also be used to work in pairs to hold 16-bit data.
 They can work in pairs such as B-C, D-E and H-L to store 16-bit data.
 The H-Lpair works as a memory pointer. A memory pointer holds the address of
aparticularmemorylocation.Theycanstore16-bitaddressas theyworkinpair.

Program Counter
 It is a 16-bit special purpose register. It is used to hold the address of memory of
the next instruction to be executed. It keeps the track of the instruction in a
program while they are being executed.
 The microprocessor increments the content of the next program counter during
the execution of an instructionso that at the end of the execution of an
instruction it points to the next instructions address in the program.

Stack pointer
 It is a 16-bit special function register used as memory pointer. A stack is nothing
but a portion of RAM. In the stack, the contents of only those registers are saved,
which are needed in the later part of the program.
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  The stack pointer (SP) controls the addressing of the stack. The Stack Pointer
contains the address of the top element of data stored in the stack.

Temporary register

a) Temporary Data Register : The ALU has two inputs. One input is supplied by the
accumulator and other from temporary data register. The programmer cannot
access this temporary data register. However, it is internally used for execution of
most of the arithmetic and logical instructions.

For example:

 ADD B is the instruction in the arithmetic group of instructions which adds the
contents of register A and register B and stores result in register A.

 The addition operation is performed by ALU. The ALU takes inputs from register
A and temporary data register. The contents of register B are transferred to
temporary data register for applying second input to the ALU.

b) W and Z registers: W and Z registers are temporary registers. These registers

are used to hold 8-bit data during execution of some instructions. These registers
are not available for programmer, since 8085 Microprocessor Architecture uses
them internally.

Use of W and Z registers:

 The CALL instruction is used to transfer program control to a subprogram or

subroutine. This instruction pushes the current PC contents onto the stack and
loads the given address into the PC. The given address is temporarily stored in
the W and Z registers and placed on the bus for the fetch cycle. Thus the
program, control is transferred to the address given in the instruction.

 XCHG instruction exchanges the contents of H with D and L with E, At the time of
exchange W and Z registers are used for temporary storage of data.

Flags Register
 It is an 8-bit register, in which five of the bits carry significant information in the
form of flags: S (Sign flag), Z (Zero flag), AC (Auxiliary carry flag), P (Parity flag),
and CY (carry flag)

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 a) S-Sign flag : After the execution of arithmetic or logical operations, if bit D7 of
the result is 1,the sign flag is set. In a given byte if D 7 is 1, the number will be
viewed as negative number. If D7 is 0, the number will be considered as positive
number.

Example:
 MVI A 30 (load 30H in register A)
MVI B 40 (load 40H in register B)
SUB B (A = A – B)
These set of instructions will set the sign flag to 1 as 30 – 40 is a negative
number.

 MVI A 40 (load 40H in register A)

MVI B 30 (load 30H in register B)
SUB B (A = A – B)
These set of instructions will reset the sign flag to 0 as 40 – 30 is a positive
number.

b) Zero Flag (Z) :After any arithmetical or logical operation if the result is 0
(00)H, the zero flag becomes set i.e. 1, otherwise it becomes reset i.e. 0.
00H zero flags is 1. from 01H to FFH zero flag is 0 1- zero-result 0- non-zero
result.

Example:
 MVI A 10 (load 10H in register A)
SUB A (A = A – A)
These set of instructions will set the zero flag to 1 as 10H – 10H is 00H

c) Auxiliary Carry Flag (AC): This flag is used in the BCD number system (0-9). If
after any arithmetic or logical operation D(3) generates any carry and passes it
on to D(4) this flag becomes set i.e. 1, otherwise, it becomes reset i.e. 0. This
is the only flag register that is not accessible by the programmer 1-carry out from
bit 3 on addition or borrows into bit 3 on subtraction 0-otherwise.

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 Example:
 MVI A 2BH (load 2BH in register A)
MVI B 39H (load 39H in register B)
ADD B (A = A + B)

These set of instructions will set the auxiliary carry flag to 1, as on adding 2B and
39, the addition of lower-order nibbles B and 9 will generate a carry.

d) Parity Flag (P) : If after any arithmetic or logical operation the result has even
parity, an even number of 1 bit, the parity register becomes set i.e. 1, otherwise it
becomes reset i.e. 0. 1-accumulator has an even number of 1 bits 0-accumulator
has odd parity.

Example:
 MVI A 05 (load 05H in register A)

This instruction will set the parity flag to 1 as the BCD code of 05H is 00000101,
which contains an even number of ones i.e. 2.

e) Carry Flag (CY) : Carry is generated when performing n bit operations and the
result is more than n bits, then this flag becomes set i.e. 1, otherwise, it becomes
reset i.e. 0. During subtraction (A-B), if A>B it becomes reset, and if (A<B) it
becomes set. Carry flag is also called the borrow flag. 1-carry out from MSB bit on
addition or borrow into MSB bit on subtraction 0-no carry out or borrow into MSB
bit.
Example:
 MVI A 30 (load 30H in register A)
MVI B 40 (load 40H in register B)
SUB B (A = A – B)

These set of instructions will set the carry flag to 1 as 30 – 40 generates a

carry/borrow.

 MVI A 40 (load 40H in register A)

MVI B 30 (load 30H in register B)
SUB B (A = A – B)

These set of instructions will reset the sign flag to 0 as 40 – 30 does not generate
any carry/borrow.
Instruction register and Decoder

 Instructionregisteris8-bitregisterjustlikeeveryotherregisterofmicroprocessor.
Consider an instruction. The instruction may be anything likeadding two data's,

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 moving a data, copying a data etc.
 When such an instructionis fetched from memory, it is directed to Instruction
register. So, the
instructionregistersarespecificallytostoretheinstructionsthatarefetchedfrommemo
ry.ThereisanInstructiondecoderwhichdecodestheinformationpresentinthe
Instructionregisterfor further processing.

Timing and Control unit

 Timing and control unit is a very important unit as it synchronizes the registers
and flow of data through various registers and other units. This unit consists of an
oscillator and controller sequencer which sends control signals needed for
internal and external control of data and other units.
 The oscillator generates two-phase clock signals which aids in synchronizing all
the registers of 8085 microprocessor.
 Signals that are associated with Timing and control unit are:

a) Control Signals: RD’, WR’, ALE

 ALE is used for provide control signal to synchronize the components of

microprocessor and timing for instruction to perform the operation.
 RD (Active low) and WR (Active low) are used to indicate whether the operation is
reading the data from memory or writing the data into memory respectively.

b) StatusSignals: S0, S1, IO/M’

 IO/M (Active low) is used to indicate whether the operation belongs to the
memory or peripherals.
S1 S2 DataBusStatus(Outpu
t)
0 0 Halt
0 1 WRITE
1 0 READ
1 1 Opcode fetch

c) DMA Signals: HOLD, HLDA, READY

HOLD:
 Indicates that another master is requesting the use of theaddress and data
buses. The CPU, upon receiving the hold request,will relinquish the use of the
bus as soon as the completion of
thecurrentbustransfer.Internalprocessingcancontinue.

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  Theprocessor can regain the bus only after the HOLD is removed. Whenthe
HOLD is acknowledged, the Address, Data RD, WR and IO/M’lines are tri-
stated.

HLDA:
 Hold Acknowledge: Indicates that the CPU has received theHOLD request and
that it will relinquish the bus in the next clockcycle HLDA goes low after the
Hold request is removed. The CPUtakesthe bus onehalf-clockcycle
afterHLDAgoes low.

READY:
 This signal synchronizes the fast CPU and the slow memory, peripherals. If
READY is high during a read or write cycle, it indicates that the memory or
peripheral is ready to send or receivedata.
 If READY is low, the CPU will wait an integral number of clock cycle for READY
to go high before completing the read or write cycle. READY must conform to
specified setup and hold times.

Interrupt control

 Whenever the interrupt signal is enabled or requested the microprocessor

shifts the control from main program to process the incoming request and
after the completion of request, the control goes back to the main program.
 For example, an Input/output device may send an interrupt signal to notify
that the data is ready for input. The microprocessor temporarily stops the
execution of main program and transfers control to I/O device. After
collecting the input data, the control is transferred back to main program.
 Interrupt signals present in 8085 are:
a) INTR
b) RST 7.5
c) RST 6.5
d) RST 5.5
e) TRAP

Address buffer and Address-Data buffer

 The contents of the stack pointer and program counter are loaded into the
address buffer and address-data buffer. These buffers are then used to drive
the external address bus and address-data bus.
 As the memory and I/O chips are connected to these buses, the CPU can
exchange desired data to the memory and I/O chips.
 The address-data buffer is not only connected to the external data bus but
also to the internal data bus which consists of 8-bits. The address data buffer

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 can both send and receive data from internal data bus.

Address bus and Data bus

 The 8 most significant bits of the address are transmitted with the help of
address bus and the 8 least significant bits are transmitted with the help of
multiplexed address/data bus.

2.With the help of neat diagram explain the pin diagram of 8085
microprocessor in detail.

 The signals can be grouped as follows

1. Power supply and clock signals
2. Address bus
3. Data bus
4. Control and status signals
5. Interrupts and externally initiated signals
6. Serial I/O ports

Power supply and Clock frequency signals

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  Vcc + 5-volt power supply
 Vss Ground
 X1, X2: Crystal or R/C network or LC network connections to set the frequency
of internal clock generator. The frequency is internally divided by two. Since
the basic operating timing frequency is 3 MHz, a 6 MHz crystal is connected
externally.
 CLK (output) – Clock Output is used as the system clock for peripheral and
devices interfaced with the microprocessor.
Data Bus and Address Bus

 The address bus is a group of sixteen lines i.e A0-A15. The address bus is
unidirectional, i.e., bits flow in one direction from the microprocessor unit to
the peripheral devices and uses the high order address bus.

Control and Status Signals

 These signals are used to determine the type of operation being performed.
There are three control and three status signals.
 RD, WR, and ALE are the three control signals.

RD indicates that the selected IO or memory device is to be read and is ready

to accept data from the data bus.

WR This signal indicates that the data on the data bus is about to be written
into a specific memory or IO location.

ALE is a positive going pulse generated by the microprocessor when a new

operation is initiated. When the pulse becomes high, it denotes the address.
When the pulse falls, it indicates that data has been received.

Interrupts and Peripheral Initiated Signals

 The 8085 has five interrupt signals that can be used to stop the execution of a
program.

(i) INTR I (ii) RST 7.5 (iii) RST 6.5 (iv) RST 5.5 (v) TRAP

 The INTA signal is used by the microprocessor to acknowledge Interrupt

Request.
 There are three externally initiated signals in addition to Interrupts: RESET,
HOLD, and READY. It has one signal called HLDA that responds to HOLD
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 requests.
 INTR stands for interrupt request.
 INTA’ – A microprocessor interrupt acknowledgment sent after INTR is
received.
Reset Signals
 RESET IN -When the signal on this pin is low(0), the program counter is reset,
the buses are tri-stated, and the microprocessor unit is reset.
 RESET OUT – Indicates that the MPU is being reset. Other devices can be reset
using the signal.
DMA Signals
 HOLD – This indicates that another device wants to use the address and data
bus. When a HOLD request is received, the microprocessor relinquishes the use
of the buses as soon as the current machine cycle is completed. Internal
processing may be resumed. The processor regains bus access after the HOLD
signal is removed.
 HLDA – This is a signal that indicates that a HOLD request has been received.
When a HOLD request is removed, the HLDA goes low.
Serial I/O Ports:
 There are two serial signals, SID and SOD, that are used for serial
communication.
 SOD (Serial output data line) The SIM instruction sets/resets the output SOD.
 SID (Serial input data line): When a RIM instruction is executed, the data on
this line is loaded into the accumulator.

3. Explain about the memory organization in 8085-based system.

 A microprocessor-based system requires both EPROM and RAM. Hence the

available memoryspace has to be divided between EPROM and RAM.
 The 8085 has 64kb of addressable memory space and allotting this address
space for EPROM and RAM depends on the system designer aswell as the
application for which the system is designed.
 Some systems may require large memory space. So, the full memory space is
utilized. But in some systems the memory requirement may be less and in this
case the full memory space willnot be utilized.
 When the full memory space is not utilized, the unused memory addresses can
be
used for addressing IO devices. Such IO devices are called memory-mapped IO
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 devices and theycan be accessed similar to that of a memory device.
 The required EPROM memory capacity of the system can be implemented in
one IC or in multiple ICs. Similarly, the RAM capacity of the system can be
implemented in one IC or in multipleICs. This choice depends on the availability
of memory IC and the system designer.
 Consider a system in which the full memory space 64kb is utilized for EPROM
memory. In this system the entire 16 address lines of the processor are
connected to address input pins of memory IC in order to address the internal
locations of memory and Chip Select (CS) pin of EPROM is permanently tied to
logic low (i.e., tied to ground) as shown in Fig.1.Now therange of address for
EPROM is 0000H to FFFFH.

Fig. 1: Example of implementing 64 kb EPROM in the 8085 system

 Consider a system in which the available 64 kb memory space is equally divided
between EPROM and RAM. Let us implement 32 kb memory capacity of EPROM
using single IC 27256. Similarly, 32 kb RAM capacity is implemented using single
IC 62256.
 The 32 kb memory requires 15 address lines and so the address lines A0 - A14 of
the processor are connected to 15 address pins of both EPROM and RAM as shown
in Fig. 2. The unused address line A15 is used as a chip select signal for selecting
either EPROM or RAM. The A15 line is directly connected to the CS pin of EPROM
and it is inverted and connected to CS pin of RAM. Therefore, the EPROM is
selected when A15 = 0 and RAM is selected when A15 = 1. The address range of
EPROM will be 0000H to7FFFH and that of RAM will be 8000H to FFFFH.

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Fig.2: Example of implementing 32 kb EPROM and 32 kb RAM in an 8085 system

Relation between number of address pins and memory capacity

 A semiconductor memory IC will have naddress pins and m data pins. Such a
memoryhas 2nlocations and each location can store m-bit data. The size of data
stored in each memory location is called memory word size. In INTEL 8085-based
systems normally memories with word size of 1-byte are used. (But we can even
interface memories with word size 1-bit, 2-bit and 4-bit.)
 The memory capacity is specified in kilo bytes. If the memory IC has m data pins
and n address pins, then the memory IC will have a capacity of 2n × m bits. When
m = 8, the memory capacity is 2 n bytes. One kilo-byte is 1024 10 (= 400H) bytes.
The relation between address pins andcapacity of memory ICs are listed in Table.

4. Interface two numbers of 4 kb EPROM and one number of 8 kb RAM with

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 8085 processor. Explain the interface diagram and allocate binary
addresses to memory ICs.

Solution:

 The IC 2732 is selected for EPROM memory and the IC 6264 is selected for RAM
memory. Both the memory IC's have time compatibility with 8085 processors.
 The 4 kb EPROM IC requires 12 address lines (2 12 = 4 k). The 8 kb RAM IC requires
13 address lines (213 = 8 k). The address lines A0 - A11 are connected to both
EPROM and RAM address input pins.
 The address lines A13, A14 and A15 are not used for memory address. Hence by
decoding these address lines we can generate chip select signals.
 The 3-to-8 decoder, 74LS138 is employed to produce the chip select signals for
the system. The decoder has 8-output lines which can be used as 8-chip select
signals.
 In this, three chip select signals are used for selecting memory ICs and the
remaining five can be used for selecting other peripheral ICs in the system or for
future expansion of the memory capacity.

 The interface diagram is shown in Fig. Address allotted to memory ICs are shown
in Table. The EPROM's are mapped in the beginning of memory space. The
remaining addresses can be allotted to RAM's. The EPROM memory is mapped
from 0000H to 0FFFH and 2000H to 2FFFH. The RAM memory is mapped from 4000 H
to 5FFFH.
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 Address Allocation Table

X indicates the unused address line for the particular memory IC and they
areconsidered as zero.
5. In a microprocessor system using 8085, the memory requirement is 8 kb
EPROM and 8 kb RAM. For interfacing IO devices, three numbers of 8255
are required. Select suitable memories and explain how they are
interfaced to the system. Interface the 8255 by memory mapping.

Solution:

 The IC 2764 is selected for EPROM memory and the IC 6264 is selected for RAM
memory. Both the memory IC's have time compatibility with 8085 processor.
 The 8 kb EPROM, 2764 requires 13 address lines (2 13 = 8 k). The 8 kb RAM, 6264
also requires 13address lines (2 13 = 8 k). The address lines A0 to A12 are
connected to both EPROM and RAM memory ICs.
 The 8255 requires four internal addresses. Let us connect A1 of 8085 to A0 of
8255 and A2 of 8085 to A1 of8255. The 8255 is memory-mapped in the system.
 For the memories and 8255's we require 5 chip select signals. Hence we can
use a 3-to-8 decoder74LS138 for generating eight chip select signals by
decoding the unused address lines A13, A14 and A15.
 The decoder enabled pins are permanently tied to appropriate levels. In the
eight chip select signals, five are used for selecting memory ICs and 8255 and
the remaining three can be used for future expansion. Thememory/8255
interface diagram is shown in Fig.

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Address Allocation Table

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Note : The X indicates that the address line is not used for the particular device and
they are considered as zero.

 The EPROM is mapped at the starting of memory space. The RAM is mapped at
the end of memory space. The EPROM is mapped from 0000H to 1FFFH. The RAM
is mapped from E000H to FFFFH.
 The four internal devices of 8255 are control register, port-A, port-B and port-C. A
16-bit address is allotted to each internal device of 8255 as shown in Table.

6. Draw and explain the timing diagram of 8085 microprocessor.

 The timing diagram provides information about the various condition (high state
or low state or high impedance state) of the signals while a machine cycle is
executed.
 The timing diagrams are supplied by the manufacturer of the microprocessor. The
timing diagrams are essential for a system designer. Only from the knowledge of
timing diagrams, the matched peripheral deviceslike memories, ports, etc., can be
selected to form a system with microprocessor as CPU.
 The 8085 microprocessor has seven basic machine cycles. They are as follows:
a) Opcode fetch cycle (4T or 6T)
b) Memory read cycle (3T)
c) Memory write cycle (3T)
d) IO read cycle (3T)
e) IO write cycle (3T)
f) Interrupt acknowledge cycle (6T or 12T)
g) Bus idle cycle (2T or 3T)
a) Opcode Fetch Machine Cycle
 Each instruction of the processor has one-byte opcode. The opcodes are stored
in memory. The opcode fetch machine cycle is executed by the processor to
fetch the opcode from memory.Hence, every instruction starts with opcode
fetch machine cycle.
 The time taken by the processor to execute the opcode fetch cycle is either 4T
or 6T.
 In this time, the first 3T states are used for fetching the opcode from memory
and the remaining T states are used for internal operations by the processor.
The timings of various signals during opcode fetch cycle are shown in Fig.

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  At the falling edge of first T-state (T 1), the microprocessor outputs the low byte
address on AD0-AD7 lines and high byte address on A8 to A15 lines. ALE is
asserted high to enable the external address latch. The other control signals
are asserted as follows. IO/M=0, S 0= 1, S1= 1. (IO/M is asserted low to indicate
memory access.)
 At the middle of T1, the ALE is asserted low and this enables the external
address latch to take low byte of the address and keep on its output lines.
 In the second T-state (T 2), the memory is requested for read by asserting read
line low. When read is asserted low, the memory is enabled for placing the
opcode on the data bus. The time allowed for memory to output the opcode is
the time during which read remains low.
 In the third T-state (T3), the read signal is asserted high. On the rising edge of
read signal, the opcode is latched into microprocessor. Other control signals
remain in the same state until the next machine cycle.
 The fourth T-state (T4) is used by the processor for internal operations to
decode the instruction and encode into various machine cycles, and also for
completing the task specified by 1-byte instruction. During this state (T 4) the
address and data bus will be inhigh impedance state.

b) Memory Read Machine Cycle

 The memory read machine cycle is executed by the processor to read a data
bytefrom memory. The processor takes 3T states to execute this cycle. The
timings of various signals during memory read cycle are shown in Fig.

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  At the falling edge of T1, the microprocessor outputs the low byte address on
AD0- AD7lines and high byte address on A8to A15lines. ALE is asserted high to
enable the external address latch.The other control signals are asserted as
follows.IO/M=0, S0= 0, S1= 1. (IO/M is asserted low to indicate memory access)
 At the middle of T1, the ALE is asserted low andthis enables the external
address latch to takelow byte of address and keep on its output lines.
 In the second T-state (T2), the memory isrequested for read by asserting read
line low.When read is asserted low, the memory is enabledfor placing the data
on the data bus. The timeallowed for memory to output the data is the
timeduring which read remains low.
 At the end of T3, the read signal is asserted high.On the rising edge of read
signal, the data is latchedinto microprocessor. Other control signals remainin
the same state until the next machine cycle.
c) Memory Write Machine Cycle
 The memory write machine cycle isexecuted by the processor to write a data
bytein a memory location. The processor takes3T states to execute this
machine cycle. Thetimings of various signals during memory writecycle are
shown in Fig.

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 At the falling edge of T1, the microprocessor outputs the low byte address on AD 0-
AD7lines and high byte address on A8to A15lines. ALE is asserted high to enable
the external address latch. The other control signals are assertedas
follows.IO/M=0, S0= 1, S1= 0. (IO/M is asserted low to indicate memory access.)
 At the middle of T1, the ALE is asserted low and this enables the external address
latch for latching the low byteaddress into its output lines.
 In the falling edge of T2, the processor output data on AD 0to AD7lines and then
request memory for write operationby asserting the write control signal WR to
low.
 At the end of T3, the processor asserts WR high. This enables the memory to latch
the data into it. The memoryshould prepare itself to accept the data within the
time duration in which write control signal remains low. Othercontrol signals
remain in the same state until the next machine cycle.

d) IO Read Cycle
 The IO read cycle is executed by the processorto read a data byte from IO port or
from the peripheralwhich is IO-mapped in the system. The processortakes 3T
states to execute this machine cycle. Thetimings of various signals during this
machine cycleare shown in Fig.

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 At the falling edge of T 1, the microprocessor output the 8-bit port address on both
the low order address lines (AD0-AD7) and high order address lines (A8to A15). ALE
is asserted high to enable the external address latch. The other control signals
are asserted as follows. IO/M=1, S0= 0 and S1= 1. (IO/M is asserted high
toindicate IO access.)
 At the middle of T1, the ALE is asserted low and this enables the external address
latch to take the port addressand keep on its output lines.
 In the second T-state (T2) the IO device is requested for read by asserting read
line low. When read is asserted low, the IO port is enabled for placing the data on
the data bus.The time allowed for IO port to output the data is the time during
which read remains low.
 At the end of T3, the read signal is asserted high. On the rising edge of read
signal the data is latched intomicroprocessor. Other control signals remains in the
same state until the next machine cycle.

e) IO Write Cycle
 At the falling edge of T1, the microprocessor outputs the 8-bit port address on low
order address line(AD0- AD7) and high order address lines (A8 to A15). ALE is
asserted high to enable the external address latch. Theother control signals are
asserted as follows: IO/M=1, S0= 1 and S1= 0. (IO/M is asserted high to indicate
IO access.)
 At the middle of T1, the ALE is asserted low and this enables the external address
latch for latching the port address into its output lines.
 In the falling edge of T2, the processor output data on AD0 - AD7 lines and then
request IO port for write operation by asserting the write control signal WR to low.
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  At the end of T3, the processor asserts WR high. This enables the IO port to latch
the data into it. The IO port should prepare itself to accept the data within the
time duration in which write control signal remains low. Other control signals
remains in the same state until the next machinecycle.

7. Draw and explain the timing diagram of CALL instruction in 8085

microprocessor.
 The "CALL addr16" instruction is used to execute a subroutine/procedure stored
at addr16,after saving the address of the next instruction in the stack memory.
On execution of this instruction,the addr16 is loaded in the Program Counter (PC)
and the previous value of the PC is stored in thestack memory pointed by the
Stack Pointer (SP). Let the address of the subroutine be 4F50 H andthe content of
SP be 4100H.
 The CALL addr16 is a three-byte instruction. The first byte is the opcode of the
instructionCDH. The second byte is the low byte of address 50 H and the third byte
is the high byte of address4FH. Let the three bytes of the instructions be stored in
memory locations 4200H, 4201Hand 4202H.
 In order to execute this instruction, the 8085 microprocessor will first execute
theopcode fetch machine cycle to get the opcode of the instruction CD H, followed
by twomemory read cycles to get the address of the subroutine (i.e., to read the
second and third byte ofinstruction).
 At the end of the second memory read cycle, the content of the PC will be 4203 H.
After theread cycles, the processor executes two memory write cycles to store
this content (4203H) of PCin the stack. During the memory write cycles, the

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 content of the SP is used as the memory address.
 In the first write cycle, the content of the SP is decremented by one (4100 H− 1 =
40FFH) andoutput on the address lines and in this address, the high byte of PC
(42H) is stored. In the secondwrite cycle, the content of the SP is again
decremented by one (40FFH− 1 = 40FEH) and output onthe address lines and in
this address the low byte of PC (03 H) is stored. The status of varioussignals during
execution of this instruction are shown in Fig.

8. Draw and explain the timing diagram of STA instruction in 8085

microprocessor.
 The "STA addr16" instruction is used to store the content of the accumulator to a
memory location. This instruction employs direct addressing. Let the content of
the accumulator be C7Hand it is desired to store the content of the accumulator to
a memory location 526AH.
 The STA addr16 instruction is a three-byte instruction. The first byte is the opcode
of theinstruction 32H. The second byte is low byte address 6AH and the third byte
is high byte address 52H.
 Let the three bytes of the instructions be stored in memory locations 41FF H, 4200H
and 4201H.
 In order to execute this instruction, the 8085 microprocessor will first execute
opcode
fetch machine cycle to get the opcode, followed by two memory read cycles to
read the addressof data (i.e., to read second and third byte of instruction). Then,
the processor executes thememory write cycle to store the content of the
accumulator in the memory. The status of varioussignals during execution of this

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 instruction are shown in Fig.

9. Describe the different types of interrupts in 8085 microprocessor.

 When microprocessor receives any interrupt signal from peripheral(s) which are
requesting its services, it stops its current execution and program control is
transferred to a sub-routine by generating CALL signal and after executing sub-
routine by generating RET signal again program control is transferred to main
program from where it had stopped.
 Mainly in the microprocessor-based system the interrupts are used for data
transfer between the peripheral and the microprocessor.
 The processor will check the interrupts always at the 2nd T-state of last machine
cycle.
 If there is any interrupt it accepts the interrupt and send the INTA (active low)
signal to the peripheral.
 The vectored address of particular interrupt is stored in program counter.
 The processor executes an Interrupt Service Routine (ISR) addressed in
program counter.
 It returned to main program by RET instruction.
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Classification of Interrupts
Interrupts are classified in two ways:
a) Maskable and Non-Maskable Interrupts
b) Vectored and Non-Vectored Interrupts
c) Hardware and Software Interrupts

a) (i) Maskable Interrupts

 Maskable interrupts are those interrupts that can be delayed or denied. Any
interrupt which can be disabled by giving appropriate instructions is termed
as maskable interrupts. Masking prevents the interrupt from disturbing the
main program execution. Very useful in cases of interrupts that are low
priority and don’t need to disturb the original program.
(ii) Non-Maskable Interrupts
 These interrupts cannot be disabled using any instructions. The TRAP interrupt
is one of the non-maskable interrupts. It is used in critical power failure
situations.

b) (i) VectoredInterrupts
 Vectored Interrupts have fixed vector addresses, which is the starting address
of the sub-routine. Once the microprocessor encounters this, it jumps to the
sub-routine and executes the instructions. After executing these, the program
control shifts back to the normal program’s instruction address and continues
running.

(ii) Non-Vectored Interrupts

 Non-Vectored Interrupts are those that do not have a predefined vector
address. The INTR interrupt is the only non-vectored interrupt in the Intel
8085 microprocessor.

c)(i) Hardware Interrupts

 The hardware interrupts in the 8085 are initiated (or raised) by an external
device by applying an appropriate signal at the interrupt pin of the
microprocessor.
 If the interrupt gets accepted, the processor attends the request and
executes the respective Interrupt Service Routine (ISR).

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  The Intel 8085 are five distinct interrupt pins (pins 6 to 10 in the Pin Diagram)
which are used as the Hardware Interrupts:
a) TRAP
b) RST 7.5
c) RST 6.5
d) RST 5.5
e) INTR
 The Vector Addresses of these interrupts are listed below:

Interrupt Vector Address

RST7.5 003CH
RST6.5 0034H
RST5.5 002CH
TRAP 0024H

TRAP
 The TRAP is a non-maskable, edge & level-triggered processor interrupt. It
has the highest priority compared to all the other interrupts. This interrupt
can only be masked by resetting the processor itself. Else it cannot be
ignored. Instead, it can be delayed a bit using the HOLD signal. Upon
attending the request, the interrupt transfers the program control to the
location 0024H, which holds the instructions for servicing it.
 Edge & level-triggered interrupt means that once the TRAP interrupt is raised
acknowledge goes high, it remains high until it is serviced/acknowledged.
 In case there is any unexpected power failure, it executes an ISR and then
sends the data from the Main Memory to the Backup Memory.
RST 7.5
 This is the second-highest priority interrupt. It is a maskable one and an
edge-sensitive interrupt. The vector address of RST 7.5 is 003C H. Like the
TRAP, this interrupt can also be reset or masked by resetting the processor
itself.
RST 6.5 and RST 5.5
 These two are level-triggered, and maskable processor interrupts. When the
RST 6.5 pin is at logic 1 (set to high), the IE flip-flop is then set. The RST 6.5
has the third-highest priority, followed by the RST 5.5 having the fourth
highest. These can be masked by using the DI and SIM instructions, or by
simply resetting the microprocessor.
INTR
 It is, again, a level- triggered &maskable interrupt. It holds the least
priority and can be disabled by using the DI or SIM instruction or simply
resetting the 8085.

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(ii) Software Interrupts
 The software interrupts are interrupt instructions that pop up during the
program execution. These instructions are placed at desired locations in
between a program. Thus, while the program is running, if such software
interrupts are encountered, the 8085 executes the respective interrupt
service routine for that interrupt. These software interrupts cannot be masked
or disabled.

 The Intel 8085 has eight software interrupts

a) RST 0
b) RST 1
c) RST 2
d) RST 3
e) RST 4
f) RST 5
g) RST 6
h) RST 7

 The Vector Addresses of these eight interrupts are listed below:

Interrupt Vector Address
RST 0 0000H
RST 1 0008H
RST 2 0010H
RST 3 0018H
RST 4 0020H
RST 5 0028H
RST 6 0030H
RST 7 0038H

Interrupt Priorities
 When the 8085 microprocessor receives multiple interrupt requests at the
same time, it will attend and execute the interrupt service routine (ISR)
according to the priority levels of these interrupts.
 The TRAP has the highest interrupt, and the INTR has the least.

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Enabling of Interrupts
 Inside the Intel 8085, there is a flip-flop called the IE flip-flop. Here, IE stands
for Interrupt Enable. When this flip-flop is reset to the 0 state, the 8085
interrupt system gets disabled. That is, even if there is a situation where an
external interrupt pin gets activated, the corresponding interrupt signal isn’t
activated. The internal architecture of the Intel 8085 interrupt structure is
shown below.

 From the architecture, we see that the IE flip-flop state has no control over
the internal interrupt signal corresponding to the TRAP interrupt. As
mentioned earlier, the TRAP is the highest priority interrupt, which cannot be
masked. Thus, whenever the external TRAP pin gets activated, the

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 corresponding interrupt signal is activated.
 The interrupt process is enabled by using the EI instruction in the processor’s
instruction execution. The EI is a 1-byte instruction that enables the interrupt
process. Enabling interrupts will allow the processor to save the current
instruction in the stack and jump to the interrupt service routine. Once the
interrupt has been attended, the program control returns to the normal
program.

Disabling of Interrupts
 Apart from the TRAP interrupt, the interrupt system can be disabled by
managing the IE flip-flop. The IE flip-flop is reset to 0 state by the given
conditions,
a) Execution of the DI instruction
b) Recognizing an interrupt request;
c) Resetting of the Intel 8085
 The DI instruction in 8085 stands for “Disable Interrupts.” DI is a 1-Byte
instruction which resets the IE flip-flop when executed. This disables the
entire 8085 interrupt system except for the TRAP pin.
 Once the 8085 recognizes an interrupt raised, it executes its ISR. Without a
doubt, the processor would not like being interrupted again amidst executing
the ISR. Thus, the 8085 will place itself under the DI state once an interrupt is
recognized. Nonetheless, the TRAP interrupt can still interrupt an ongoing ISR.
There is no necessity to specify the DI instruction at the beginning of an ISR.
It is disabled by default.
Set Interrupt Mask (SIM)
 The Intel 8085 provides an additional facility for masking for the interrupts
RST 7.5, RST 6.5 and RST 5.5. The Set Interrupt Mask (SIM) is used to
implement the 8085 hardware interrupts (RST 7.5, RST 6.5, RST 5.5). This is
carried out by setting certain bits to form ‘masks’ or by generating output
data through the Serial Output Data (SOD) line. The required mask value
is first loaded in the accumulator register – the SIM will then take the bit
pattern from it. The status of the interrupts can be read by running the RIM
instruction.

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Read Interrupt Mask (RIM)
 The status of all pending interrupts can be read by using the Read Interrupt
Mask (RIM) instruction. RIM performs the following tasks:
a) Reads the interrupt mask (bit 2, bit 1, bit 0)
b) Identify the pending interrupts (bit 6, bit 5, bit 4)
c) Receive the Serial Input Data bit (bit 7)
 When the RIM instruction gets executed, a byte of information is loaded into
the accumulator, which can be accurately interpreted as given below.

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