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(EE 211) Assignment 4

This document is an assignment for the course EE/CE – 211 – Basic Electronics at Habib University, due on March 25th, 2024. It outlines the course learning outcomes and includes two main questions focusing on the analysis and design of BJT configurations, with specific parameters provided for calculations. The assignment emphasizes proper submission guidelines and requires students to show all workings clearly.

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alishba zaidi
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16 views9 pages

(EE 211) Assignment 4

This document is an assignment for the course EE/CE – 211 – Basic Electronics at Habib University, due on March 25th, 2024. It outlines the course learning outcomes and includes two main questions focusing on the analysis and design of BJT configurations, with specific parameters provided for calculations. The assignment emphasizes proper submission guidelines and requires students to show all workings clearly.

Uploaded by

alishba zaidi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Habib University

School of Science & Engineering


Course EE/CE – 211 – Basic Electronics
Semester Spring 2024
Assignment 4
Due Date March 25th, 2024
Instructor Ahmad Usman
Total Marks 50
Name: ___________________________________________Student ID: _________________
Note:
▪ Take a print of the assignment and solve on the space provided after every question. You can use extra
sheets for your answers. Attach them properly.
▪ No assignment shall be graded if submitted late and don’t comply the guidelines as mentioned above.
▪ Show all working properly.

Course Learning Outcomes


After the completion of the course the student should be able to
CLOs Description Learning-
domain level
CLO - 1 Explain and understand the working and behavior of semiconductor diodes, Cog – 3
BJTs and MOSFETs in the modern electronic systems.
CLO - 2 Ability to analyze DC and AC the behavior of the semiconductor diodes, Cog – 4
BJTs, and MOSFETs in the modern electronic systems.
CLO - 3 Develop an ability to design DC power supplies, DC biasing circuits and Cog – 3
single stage amplifier circuits based on the concepts learned pertaining to
semiconductor diodes, BJTs, and MOSFETs, for various modern electronic
applications.

Question PLO CLO - LDL Points


Question 1 2 2 – Cog – 4 /20
Question 2 3 3 – Cog – 3 /30
Total /50

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Question # 1 (CLO – 2, Points: 20, 5 + 5 + 10)
Calculate Q-point parameters i.e., IC, and VCE, and VCB for the following cases. Assume VBE =
0.7V for the analysis purposes. Also, identify whether the transistor is working in forward active
region i.e., as an amplifier or not? Assume common-emitter topology for the analysis. Draw the
respective circuit diagrams as well.

a) An emitter degeneration-based biasing scheme having VCC = 20V, RB = 430kΩ, RC = 2kΩ, RE


= 1kΩ, β = 50.

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b) A self-bias (feedback bias) scheme having VCC = 10V, RB = 180kΩ, RC = 1.5kΩ, β = 100.

3
c) A voltage divider network-based biasing scheme having VCC = 10V, R1 = 18kΩ, R2 = 4.7kΩ,
RE = 1.1kΩ, RC = 3kΩ, β = 50.
1. Use approximate approach for analysis

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2. Use accurate approach for analysis

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Question # 2: (CLO – 3, Points: 30, 5 + 20 + 5)
a) Design an emitter-bias BJT configuration with the following specifications:
IC,Q = (½) Isat, ICsat = 8 mA, VCC = 28V, VC = 18V, VBE = 0.7V and β=110. Determine RC, RE,
and RB. Assume VE as 10% of VCC.

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b) Design an voltage divider-bias BJT configuration with the following specifications:
IC,Q = 10mA, VCC = 20V, VCE,Q = 8V, VBE = 0.7V, and β = 80. Determine RC, RE, and RB. Use
both approaches (use notes uploaded on LMS) to design the biasing stage. Assume VE as 10%
of VCC.

1. Accurate Approach

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2. Approximate Approach

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c) Design a self-bias (collector feedback bias) BJT configuration with the following
specifications:
IC,Q = 10mA, VCC = 20V, VCE,Q = 8V, VBE = 0.7V, and β = 80. Determine RC, RE, and RB.
Assume VE as 10% of VCC.

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