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DCO Part B Codes - UPDATED

The document contains Verilog code for various digital circuits including a demultiplexer, JK flip-flop, D flip-flop, RS flip-flop, and both synchronous and asynchronous Mod-8 up counters. Each module is defined with inputs, outputs, and behavior specified using always blocks and case statements. The code illustrates fundamental concepts in digital design such as state changes and counter operations.

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Daksh malik
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29 views2 pages

DCO Part B Codes - UPDATED

The document contains Verilog code for various digital circuits including a demultiplexer, JK flip-flop, D flip-flop, RS flip-flop, and both synchronous and asynchronous Mod-8 up counters. Each module is defined with inputs, outputs, and behavior specified using always blocks and case statements. The code illustrates fundamental concepts in digital design such as state changes and counter operations.

Uploaded by

Daksh malik
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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//Demul plexer: 1:4 is given, similarly prac ce 1:2 and 1:8 demux

Module demux (d,s,q);


Input d;
Input [1:0]q;
Output reg [3:0]q;
always @(q,s) begin
case ({s})
2’b00:
q[0]=d; q[3:1]=0;
2’b01:
q[1]=d; q[0]=0;
2’b10:
q[2]=d; q[1:0]=0;
2’b11:
q[3]=d; q[2:0]=0;
end
endmodule

//JK Flip op

module jk_ ip_ op (j,k,clk,q);


input j,k; //no reset
output reg q;

always @(posedge clk) begin


case ({j, k})
2'b00: q <= q; // No change “<= is called non blocking assignment operator”
2'b01: q <= 0; // Reset -> “No need for reset”
2'b10: q <= 1; // Set
2'b11: q <= ~q; // Toggle
end
endmodule

// D Flip-Flop
module jk_ ip_ op (d,clk,q);
input d,clk;
output reg q;
always @(posedge clk) begin
If (d=1)
q <= 1;
else
q<=0;
end
endmodule

// RS Flip-Flop
module sr_ ip_ op (s,r,clk,q);
input s,r,clk;
output reg q;
ti
fl
fl
fl
fl
fl
fl
fl
ti
always @(posedge clk) begin
case ({s, r})
2'b00: q <= q; // No change
2'b01: q <= 0; // Reset
2'b10: q <= 1; // Set
2'b11: q <= 0; // indeterminate
end
endmodule

// Mod-8 Synchronous Up Counter -> RESET NEEDED HERE


module mod8_up_counter (q,clk,reset);
input clk,reset;
output reg [2:0] q;
always @(posedge clk or posedge reset) begin
if (reset)
q <= 3'b000; // Reset counter to 0
else
q <= q + 1; // Increment counter
end
endmodule

//Mod-8 Asynchronous Up Counter

module mod8_async_counter (clk,reset,q);


input clk, reset;
output reg [2:0] q ;

always @(posedge clk or posedge reset) begin


if (reset)
q[0] <= 1'b0;
else
q[0] <= ~q[0];
end

always @(negedge q[0] or posedge reset) begin


if (reset)
q[1] <= 1'b0;
else
q[1] <= ~q[1];
end

always @(negedge q[1] or posedge reset) begin


if (reset)
q[2] <= 1'b0;
else
q[2] <= ~q[2];
end
endmodule

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