PLACEMENT.

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INPUTS FOR PLACEMENT.
▪ Netlist (.v)
▪ SDC and MCMM.
▪ Scandef.
▪ .lib.
▪ .lef.
▪ .tf.
▪ .tlup.

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PRE-PLACEMENT CHECKS
▪ Port/pin placement.
▪ We will check whether the ports/pins are aligned
properly (overlaps).
▪ Checks for any missing port/pins.

▪ Macro placement.
▪ Check whether all the macros are placed according
to the guidelines.
▪ Macros are aligned to site row or not.
▪ Proper channel spacing with no notches .
▪ Check whether keepout margins and blockages are
given properly.
▪ Proper orientation of macros.
▪ No overlapping of macros.
▪ Check for any unfixed macros.

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PRE-PLACEMENT CHECKS
▪ Boundary / endcap cells.
▪ Check whether any end cap cells are missing.

▪ Well tap cells

▪ Check whether any tap cells are placed properly.

▪ There should be no power planning issues.

▪ pg drc
▪ pg connectivity
▪ pg missing vias

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PRE-PLACEMENT REQUIREMENTS
▪ Fix all the macros and preplacement cells.
▪ Delay models must be removed and MCMM should
be added.
▪ Set don’t touch and don’t use on tie cells.
▪ Placement constraints.
▪ Use advance legalizer.
▪ Search and repair.
▪ set max fanout.
▪ set max local density
▪ Make the clock ideal

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COMMANDS
▪ Check_pin_placement.

▪ Check_boundary_cells.

▪ Check_legality.

▪ Check_pg_drc

▪ Check_pg_connectivity.

▪ Check_pg_missing_vias.

▪ set_fixed_objects [get_flat_cells -filter "is_hard_macro"]

▪ set_attribute [get_lib_cells *TIE*] dont_touch false

▪ set_attribute [get_lib_cells *TIE*] dont_use false

▪ set_app_options -name place.legalize.enable_advanced_legalizer -value true

▪ set_app_options -name place.legalize.legalizer_search_and_repair -value true

▪ set_app_options -name place.coarse.max_density -value 0.7

▪ set_app_options -name opt.common.max_fanout -value 30

▪ set_ideal_network -no_propagate [all_fanout -clock_tree ]

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PLACEMENT
S TA G E S

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PLACEMENT
▪ Placement is the process of placing the standard cells inside the core boundary in
an optimal location. The tool tries to place the standard cell in such a way that the
design should have minimal congestions and the best timing. Every PnR tool
provides various commands/switches so that users can optimize the design in a
better way in terms of timing, congestion, area, and power as per their
requirements.

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INPUT FILES
▪ Netlist
▪ SDC
▪ Library files (.lib ,lef)
▪ Technology file
▪ Mcmm file
▪ Scan def file
▪ Floorplan C Power plan (DEF)

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PRE-PLACEMENT STAGE
▪ Checks :
▪ Perform checks on port placement
▪ Perform checks on end-cap cells and tap-cells placement
▪ Perform checks on macro-placement and use blockages at required places.
▪ Set local density limit (G-cell density)
▪ Perform Power planning check
▪ Check_pg_drc
▪ Check_pg_connectivity
▪ Check_pg_missing_vias

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PLACEMENT STAGES
▪ Pre-placement stage
▪ Initial placement /global placement/ coarse placement.
▪ Legalization
▪ HFNS (High fanout net synthesis)
▪ Iteration for timing, congestion, DRVs and power optimization
▪ Multibit flop conversion
▪ Timing, Power, Area optimization iterations .
▪ Scan-chain reorder.

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 Initial Placement /Coarse Placement
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LEGALIZATION
▪ During legalization, the tool moves the cells to legal locations on the placement
grid and eliminate any overlap between cells.
▪ These small changes to cell location cause the lengths of the wire connections to
change, possibly causing new timing violations.
▪ Such violations can often be fixed by incremental optimization, for
▪ example: by resizing the driving cells.

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 Legalization
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 TIE CELL
INSERTION
Sometimes in netlist some unusual
inputs are tied to VDD/VSS ,It is not
recommended to connect directly to
the power network, so we connect
gate to TIEH or TIELO cells
Placement tool also does Tie cell
optimization , which places Tie cells
near to parent cell.

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SCAN-CHAIN REORDER
▪ If block contains scan chains by default Placement and CTS tools perform DFT
optimization.
▪ During initial placement, the tool focuses on the QOR for the function nets by
ignoring the scan chains. After initial placement, the tool further improves the QOR
by repartitioning and reordering the scan chains based on the initial placement.
▪ Scan chains reordering reduces wire length so timing will improve.
▪ Scan chains reordering minimize congestions and improves routability

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 Scan-chain reorder.

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HIGH FANOUT NET SYNTHESIS
▪ The process of buffering the high fan-out to reduce the fanout load is called as
High fanout net Synthesis. because if design has too many loads then it affects
delay and transition time.
▪ High fanout nets are mainly reset, preset, scan enable etc. these nets are not
synthesized in the synthesis stage, also make sure you set an appropriate fan-out
limit for your library

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 High Fanout Net Synthesis
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MULTIBIT FLOP CONVERSION

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PLACEMENT OPTIMIZATION STAGE:
▪ In this stage tool tries to optimize placement to reduce congestion , improve timing
and to fix timing DRVs .
▪ Tool optimizes timing DRVs and setup violation by different methods like
▪ Cell sizing
▪ Vt swapping
▪ Buffering
▪ Cloning
▪ Pin-swapping
▪ Logical restructuring

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STAGE BY STAGE
THROUGH ICC2 TOOL

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 INITIAL_DRC

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 END OF INITIAL_DRC

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 INITIAL_OPTO

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PLACEMENT BLOCKAGES

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WHAT IS THE NEED OF THE PLACEMENT
BLOCKAGES ?
▪ These act as guidelines for placing std cells in the design.
▪ Blockages are specific locations where placing of cells are prevented or blocked.

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TYPES OF BLOCKAGES.
▪ They are three types :
▪ Soft blockage
▪ Hard blockage
▪ Partial blockage

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HARD BLOCKAGE
▪ Hard blockages never allow any cells to place where the region is defined.
▪ If they are any notches present in the design we will define hard blockages.
▪ create_placement_blockage -type hard
▪ -boundary { {lrx lry} {urx ury} }
▪ -name Hard_PB

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SOFT PLACEMENT BLOCKAGE
▪ Soft Blockage specifies a region where only buffers can be placed. That means
standard cells cannot be placed in this region.
▪ It blocks (prevents) the placement tool from placing non-buffer cells such as
standard cells in this region.
▪ Command :
▪ create_placement_blockage -type soft -boundary {{x1 y1} {x2 y2}}
▪ -name soft_pb

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▪ create_placement_blockage -type soft -boundary -
boundary { {lrx lry} {urx ury} } -name soft_pb

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PARTIAL BLOCKAGE
▪ It allows both standard cells ,buffers and inverters .
▪ The blockage factor for any blockage is 100% by default.
▪ Partial placement blockage is used to control the cell density at a particular area in
the block.
▪ The percentage which we mention that much it blocks and allow s the remaining
area for placement of cells.

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CREATE_PLACEMENT_BLOCKAGE -TYPE PARTIAL -
BLOCKED_PERCENTAGE 50 -BOUNDARY {{LLX LLY} {URX
URY}} -NAME PARTIAL

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Difference b/n 100% Partial And Hard
Placement Blockages

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 PLACEMENT
CONSTRAINTS

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BOUNDS
▪ Bound is a constraint that controls the placement of groups of leaf cells and
hierarchical cells. It allows to group the cells and minimize the wire length.
▪ It helps to place the cells at the most appropriate location.
▪ Types of bounds
Move Bounds: It restricts the placement of the cells to the specific location of
the design area. A move bound is a fixed region within which to place a set of cells,
which can be abutted or disjoint.
-coordinate {coordinates} to define boundaries
▪ Soft
▪ Hard
▪ Exclusive

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• Soft move bounds
For soft move bounds, the tool tries to place the cells within the specified
region
however, there is no guarantee that the cells are placed inside the bounds.
create_bounds -name name -coordinate {coordinates} [-type soft]
[bound_objects]
• Hard move bounds
For hard move bounds, the tool must place the cells within the specified
region, but allows other cells to place inside the bounds
create_bounds -name name -coordinate {coordinates} -type hard
[bound_objects]
• Exclusive move bounds
For exclusive move bounds, the tool must place the cells within the
specified region and must place all other cells outside of the region.
create_bounds -name name -coordinate {coordinates} -exclusive
[bound_objects]
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• Group Bounds These are floating region constraints. Cells in the same
group bound are placed within a specified bound but the absolute
coordinates are not fixed. Instead, these are optimized by the placer.
-dimension {height width} to defines dimensions
• Soft
• Hard
• Dimensionless

• Soft group bound

We specify the width and height of the rectangles that comprise the bound.
The tool determines the best location for the group bound and tries to place
the objects within the specified dimensions however, there is no guarantee
that the cells are placed inside the bounds.
create_bounds -name name -dimension {height width} [-type soft]
[bound_objects]

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• Hard group bound
We specify the width and height of the rectangles that comprise the bound.
The tool determines the best location for the group bound and must place
the objects within the specified dimensions.
create_bounds -name name -dimension {height width} -type hard
[bound_objects]

• Dimensionless group bound

For dimensionless group bounds, we specify the effort used to bring the
objects closer together inside the group bound. The tool determines the
shape and location of the group bound. The default effort is medium, we can
also specify low, high, or ultra.
create_bounds -name name -effort effort_level [bound_objects]

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DIAMOND BOUND.
▪ A diamond bound constrains the placement of cells to be within a specified
Manhattan distance from a specific cell, port, or pin. We specify the central object
and the maximum distance. The tool determines the best location of the diamond
bound and tries to place the cells within the constraints.
▪ create_bounds [-name bound_name]
▪ -diamond object -dimension distance {cell_list}

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CELLS TO INCLUDE IN A BOUND
▪ The cells which are coming in the path of Worst Negative Slack of the design will
come under the bound. After highlighting these paths to create a bound, we will
check the Startpoint and Endpoint of those paths and will consider only those cells.

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TO DECIDE THE LOCATION OF BOUND
▪ We will check the timings by placing the bound in appropriate position and then
slightly move it. Then observe the difference in the timings. Whenever the timing
meets, then we’ll stick to that position and place the bound.

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TO DECIDE THE SIZE OF BOUND.
▪ To decide the size of the bound, we have to decide the cells which needs to be
pulled inside the bound and calculate the total area of the cells. According to the
area of the cells, the total area of the bound would be decided

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FENCE
▪ A fence does not allow the assigned cell to sit outside the box defined, also doesn’t
allow the other cells to sit inside the box also. So the area is exclusively reserved
for the assigned cells.
▪ It is a hard constraint.

createFence obj_name box

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GUIDE
▪ The guide allows to assigned cell sit outside the box, also allows the other cells to
sit inside the box.
▪ It is a soft constraint.

createGuide obj_name box

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REGION
▪ A region does not allow the assigned cell to sit outside the box defined.
▪ It may cause congestion in the area assigned if not chosen the area wisely.
▪ The only difference between the region and the fence is that it allows the other
cells to sit inside the box.
▪ It is a hard constraint.

createRegion obj_name box

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ICC2
• update_bounds
• report_bounds
It will report the bounds in the design that were created by the command
create_bounds. Bounds from an input PDEF file are not reported by this
command.
• get_bounds
• remove_bounds
• add_to_bound

Innovus
• Delete module guide
unplaceGuide

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HFNS & SCAN CHAIN
REORDERING

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HIGH FANOUT NET SYNTHESIS (HFNS)
▪ In VLSI design, high fanout net synthesis refers to the process of designing and
optimizing nets or wires that drive a large number of loads.
▪ High fanout nets can cause significant issues in a design due to increased
capacitance, which can lead to signal integrity problems, timing violations, and
power consumption issues.
▪ Proper synthesis and optimization of these nets are crucial for the performance
and reliability of a VLSI chip.

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CHALLENGES WITH HIGH FANOUT NETS
▪ Increased Capacitance: High fanout nets connect to many gates, increasing the
total capacitive load. This can slow down signal propagation.
▪ Timing Violations: The increased load can lead to delays in signal propagation,
causing timing violations which affect the overall performance of the chip.
▪ Signal Integrity: The integrity of the signal can degrade due to the high load,
leading to glitches and noise issues.
▪ Power Consumption: Driving a high capacitive load requires more power, leading
to increased dynamic power consumption.

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TECHNIQUES TO REDUCE FANOUT
▪ Reducing fanout in High Fanout Net Synthesis (HFNS) during the placement stage
in VLSI design is critical for optimizing timing, reducing power consumption, and
minimizing routing complexity.
▪ Various techniques are employed during the placement stage to manage and
reduce the fanout of high fanout nets. Here are the primary techniques used:
▪ Buffer Insertion
▪ Cloning

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BUFFER INSERTION
▪ Inserting buffers or repeaters along the high fanout
net is a common method to divide the capacitive
load among multiple drivers.
▪ By breaking down the load into smaller segments,
each buffer drives a reduced number of gates,
effectively lowering the fanout per segment.
▪ Buffers are strategically placed to balance the load
distribution and minimize the overall delay.

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CLONING
▪ Cloning involves duplicating the driver (gate or flip-
flop) of a high fanout net so that multiple drivers are
created, each with a lower fanout.
▪ The fanout is reduced by dividing the original load
among multiple clones.
▪ The clones are placed near their respective loads to
minimize wire length and delay, avoiding unnecessary
congestion

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SCAN CHAINS
▪ Scan chains are a critical component in the design and testing of VLSI circuits,
particularly for improving the testability of digital circuits.
▪ They facilitate the process of testing and debugging (ICs) integrated circuits by
making it easier to observe and control the state of internal flip-flops.
▪ Scan chains are used to apply test vectors and capture the resulting states of the
circuit, aiding in the detection of manufacturing defects and logic faults.

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STRUCTURE OF SCAN CHAIN

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STRUCTURE OF SCAN CHAIN
▪ A flip-flop is typically preceded by a multiplexer, which selects between the
normal data path and the scan data path.
▪ A scan chain involves connecting these flip-flops in a serial fashion to create a
"scan path," allowing data to be shifted in and out of the circuit for testing
purposes.
▪ During normal operation, these flip-flops are connected in a manner that supports
the desired circuit functionality.
▪ When in test mode, the flip-flops are connected in series, forming a long shift
register. Test data can be shifted in through the Scan-In pin, and the output can be
observed through the Scan-Out pin.

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SCAN CHAIN REORDERING
▪ Scan chain reordering is an important technique in the design and testing of VLSI
circuits. It involves rearranging the sequence of flip-flops in a scan chain to
optimize various parameters, such as test time, power consumption, and routing
complexity.

▪ Advantages of Scan Chain Reordering:

▪ Improved Timing
▪ Lower Power Consumption
▪ Simplified Routing
▪ Reduced Wire Length

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SCAN CHAIN REORDERING

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 TIMING ISSUES IN
PLACEMENT STAGE

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REASONS FOR TIMING VIOLATIONS IN
PLACEMENT STAGE
▪ Bad floorplan
▪ Module splitting
▪ Logic Depth
▪ DRV’s

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BAD FLOORPLAN
▪ Same hierarchy macros are not placed
near and placed apart means then it
lead to the timing violations because in
hierarchy, a lot communication is
happen in between macros.
▪ Runtime increases , to meet the timing by
buffering
▪ Power consumption
▪ Area increases
▪ Lead to congestion

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FIX
▪ We should place macros of
same hierarchy together to not
lead timing violations in
placement stage

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https://www.linkedin.com/in/viishnurs/
ORIENTATION

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MODULE SPLITTING
▪ In hierarchy , cell to cell communications are more
▪ So in placement stage, same hierarchy cells are splitted then it lead to the timing
violations
▪ During the opt, tool place the a lot of buffers to meet the timing but it degrades the
power and area
▪ Example

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 FIXES
• A placement bound is a constraint that controls
the placement of groups of leaf cells and
hierarchical cells. It allows us to group the
cells and minimize the wire length. It helps us
to place the cells at the most appropriate
location.

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TIMING DRV’S
▪ Max Tran
▪ Max Cap
▪ Max Fanout

▪ Causes:
▪ 1. HVT cells give slower transition
▪ 2. Weak Driver
▪ 3. Load
▪ 4. Net length is large
▪ 5. Fanout is too large

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FIXES
▪ Max Tran:
▪ Replace HVT cells with LVT cells.
▪ Up size the driver.
▪ Reduce the net length by adding buffers.
▪ Reduce the load by reducing fanout.
▪ Max Cap:
▪ Up size the driver.
▪ Split long nets by buffering.
▪ Reduce the load by reducing the fanout (by load splitting)

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➢Max Fanout:
Reduce the fanout by load splitting or by buffering or cloning.

a) Cloning b) Buffering

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https://www.linkedin.com/in/viishnurs/
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REPORT CONSTRAINTS

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LOGIC DEPTH
➢ The combinational path will be offering more delay .
Example

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FIXES
▪ Group path : path groups are used for timing optimization to solve violations.
▪ RTL Coding Practices: Adopting efficient RTL coding practices such as reducing
fanout, and minimizing logic levels can help in optimizing timing paths during
synthesis.
▪ Pipeline Registers: Introducing pipeline registers can break down long
combinational paths into shorter segments, reducing the critical path delay and
improving overall performance.

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CONGESTION

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 WHAT IS CONGESTION ?
• Congestion occur when no of available routing resources is less than
required routing recourses.
• This condition we will see in global routing.
• High congestion causes detours and leads to worse results.
• A congestion map shows in GUI with different colours.
• Vertical and horizontal congestion

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• Placement congestion • Routing congestion

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 WHAT ARE THE REASONS FOR CONGESTION?
• High standard cell density in a small area
• Routing blockages over standard cells
• placement of standard cells near the macros
• High pin density at the edges of macros due to high fan in cells like AOI OAI

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 What are the reasons for congestion?

• Bad floorplan (no proper blockages,halos are present)

• Macros/standard cell might have used all the metal layers inside and routing resources will
be less
.
• Placing macros at the centre instead of boundary
• Scan chain reordering and mixing/swapping are restricted.
• Improper optimization of netlist during synthesis.

• High port density

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HOW TO CONTROL THE CONGESTION
• Congestion Driven Placement :- To distance standard cell instances from each other such
that more routing tracks are created between them.
• Cell density control by using app options
• Scan-chain reordering helps to reduce congestion.
• Placement blockages

create_placement_blockage -type partial -blocked_percentage 50

-boundary {{llx lly} {urx ury}} -name Partial_PB
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• Cell padding
• Keep out margin/HALO.
• Try different techniques during
synthesis like logical synthesis,
.
topographical synthesis.
• SPG and non-SPG placement.
•set_app_options -name place_opt.flow.do_spg -value true

•create_keepout_margin -type hard -outer {5 5

5 5 } [get_cells *macro_name*]
•create_keepout_margin -type hard -outer
{3.9200 3.9200 3.9200 3.9200} [get_cells
cell_name]
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Modify PG grid: To have maximum routing resources, one can try to reduce the number of PG
stripes or the width of stripes. However, this has a trade-off with electromagnetic (EM) and IR
drop.
.
•set_app_options -name place_opt.place.congestion_effort -value high
•set_app_options -name place.coarse.cong_restruct_effort -value ultra
•set_app_options -name place.coarse.congestion_layer_aware -value true

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Cell density Pin density
.

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 SOME OF OBSERVATIONS IN LOG FILE

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In the default congestion report,

• “H routing” refers to results for horizontal routes only and “V routing” refers to results for
vertical routes only.
• The total overflow value is the total number of wires in the block that do not have
a corresponding track available. The max overflow value is the highest number of
overutilized wires in a single global routing cell.
• The GRCs overflow value is the total number of overcongested global routing cells in
the design. The GRCs max overflow value is the number of global routing cells that
have the maximum overflow.

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