lOMoAR cPSD| 38078257

lOMoAR cPSD| 38078257

VISION INSTITUDE OF TECHNOLOGY

ALIGARH
COMPUTER ORGANIZATION LAB

List of Experiments:

1. Implementing HALF ADDER, FULL ADDER using basic

logic gates.

2. Implementing Binary -to -Gray, Gray -to -Binary code

conversions.

3. Implementing 3-8 line DECODER.

4. Implementing 4x1 and 8x1 MULTIPLEXERS.

5. Verify the excitation tables of various FLIP-FLOPS.

6. Design of an 8-bit Input/ Output system with four 8-bit

Internal Registers.

7. Design of an 8-bit ARITHMETIC LOGIC UNIT.

8
 lOMoAR cPSD| 38078257

EXPERIMENT - 1

OBJECT:

Implementing HALF ADDER, FULL ADDER using basic logic gates.

APPARATUS REQUIRED:
Sl. No. COMPONENT SPECIFICATION QTY.
1. AND GATE IC 7408 1
2. X-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
4. OR GATE IC 7432 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 23

THEORY:

HALF ADDER:
A half adder has two inputs for the two bits to be added and two outputs one from the
sum ‘ S’ and other from the carry ‘ c’ into the higher adder position. Above circuit is
called as a carry signal from the addition of the less significant bits sum from the XOR
Gate the carry out from the AND gate.
FULL ADDER:
A full adder is a combinational circuit that forms the arithmetic sum of input; it consists
of three inputs and two outputs. A full adder is useful to add three bits at a time but a
half adder cannot do so. In full adder sum output will be taken from X-OR Gate, carry
output will be taken from OR Gate.

LOGIC DIAGRAM:
 lOMoAR cPSD| 38078257

HALF ADDER

TRUTH
TABLE:

A B CARRY SUM

0 0 0 0

0 1 0 1

1 0 0 1

K-Map for SUM: K-Map for CARRY:

SUM = A’B + AB’ CARRY = AB

S= A + B
LOGIC DIAGRAM:

10
 lOMoAR cPSD| 38078257

FULL ADDER USING TWO HALF ADDER

TRUTH TABLE:
A B C CARRY SUM
0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

K-Map for SUM:

 lOMoAR cPSD| 38078257

SUM = A’B’C + A’BC’ + ABC’ + ABC

= A’ (B’C+BC’) + A( BC’+BC)

= A’( B + C) + A(B + C)

=A+B+C

12
 lOMoAR cPSD| 38078257

K-Map for CARRY:

CARRY
= A’BC+ABC+ABC’+AB’C
= AB+A’BC+AB’C
= AB+C(A+B)
= AB+BC+AC.
PROCEEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
RESULT:

The half adder, full adder circuits are design and constructed and verify the truth
tables.

PRECAUTIONS:

• All connections should be made neat and tight.

• Digital lab kits and ICs should be handled with utmost care.
• While making connections main voltage should be kept switched off.
• Never touch live and naked wires.
 lOMoAR cPSD| 38078257

EXPERIMENT NO. 2
OBJECT:

Implementing Binary -to -Gray, Gray -to -Binary code conversions.

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY
.
1. X-OR GATE IC 7486 1
2. AND GATE IC 7408 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. IC TRAINER KIT - 1
6. PATCH CORDS - 35

THEORY:

The availability of large variety of codes for the same discrete elements of information
results in the use of different codes by different systems. A conversion circuit must be
inserted between the two systems if each uses different codes for same information.
Thus, code converter is a circuit that makes the two systems compatible even though
each uses different binary code.
The bit combination assigned to binary code to gray code. Since each code uses four
bits to represent a decimal digit. There are four inputs and four outputs. Gray code is
a non-weighted code.
The input variable are designated as B3, B2, B1, B0 and the output variables are
designated as G3, G2, G1, Go. from the truth table, combinational circuit is designed.
The Boolean functions are obtained from K-Map for each output variable. A code
converter is a circuit that makes the two systems compatible even though each uses a
different binary code. To convert from binary code to Excess-3 code, the input lines
must supply the bit combination of elements as specified by code and the output lines
generate the corresponding bit combination of code. Each one of the four maps
represents one of the four outputs of the circuit as a function of the four input
variables.
A two-level logic diagram may be obtained directly from the Boolean expressions
derived by the maps. These are various other possibilities for a logic diagram that
implements this circuit. Now the OR gate whose output is C+D has been used to
implement partially each of three outputs.

2
 lOMoAR cPSD| 38078257

LOGIC DIAGRAM: BINARY TO GRAY C ODE CONVERTOR

K-Map for G3:

G 3 = B3
K-Map for G2:
 lOMoAR cPSD| 38078257

K-Map for G1:

K-Map for G0:

TRUTH TABLE:
| Binary input | Gray code output |

B3 B2 B1 B0 G3 G2 G1 G0
 lOMoAR cPSD| 38078257

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1
4

LOGIC DIAGRAM:

GRAY C ODE TO BINARYC ONVERTOR

 lOMoAR cPSD| 38078257

K-Map for B3:

B3 = G3

5
 lOMoAR cPSD| 38078257

K-Map for B2:

K-Map for B1:

7
 lOMoAR cPSD| 38078257

K-Map for B 0:

TRUTH TABLE:
| Gray Code | Binary Code |
G3 G2 G1 G0 B3 B2 B1 B0

8
 lOMoAR cPSD| 38078257

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 1 0 0 1 0

0 0 1 0 0 0 1 1

0 1 1 0 0 1 0 0

0 1 1 1 0 1 0 1

0 1 0 1 0 1 1 0

0 1 0 0 0 1 1 1

1 1 0 0 1 0 0 0

1 1 0 1 1 0 0 1

PROCEDURE
(i) Connections were given as per circuit diagram.
(ii) Logical inputs were given as per truth table.
(iii) Observe the logical output and verify with the truth tables.

RESULT:

The Binary to gray, Gray to binary, converter Combinational circuits are constructed and
their truth tables have been checked

PRECAUTIONS:

(i) All the IC’s should be checked before use the apparatus.
(ii) All LED’s should be checked.
(iii) All connections should be tight.
(iv) Always connect GROUND first and then Vcc.
(v) The circuit should be off before change the connections.
(vi) After completing t e experiment switches off the supply to apparatur

9
 lOMoAR cPSD| 38078257

EXPERIMENT NO-3

OBJECT:

Implementing 3-8 line DECODER.

APPARATUS REQUIRED:

Sr. No. COMPONENT SPECIFICATION QTY.

1. 3 I/P AND GATE IC 7411 2

2. OR GATE IC 7432 1

3. NOT GATE IC 7404 1

2. IC TRAINER KIT With IC 74LS138 1

3. PATCH CORDS - 32

THEORY:

DECODER:

A decoder is a multiple input multiple output logic circuits which converts coded input into
coded output where input and output codes are different. The input code generally has fewer
bits than the output code. Each input code word produces a different output code word i.e.
there is one to one mapping can be expressed in truth table. In the block diagram of decoder
n n
circuit the encoded information is present as n input producing 2 possible outputs. 2 output
n
values are from 0 through out 2 – 1.

LOGIC DIAGRAM FOR 3X8 LINE DECODER:

10
 lOMoAR cPSD| 38078257

TRUTH TABLE:

TRUTH TABLE

Input Output

A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 1 0

0 1 0 0 0 0 0 0 1 0 0

0 1 1 0 0 0 0 1 0 0 0

1 0 0 0 0 0 1 0 0 0 0

1 0 1 0 0 1 0 0 0 0 0

1 1 0 0 1 0 0 0 0 0 0

1 1 1 1 0 0 0 0 0 0 0

11
 lOMoAR cPSD| 38078257

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram. (iii)
Observe the output and verify the truth table.
RESULT:

Thus the design and implementation of decoder and multiplexer using logic gates and study
of IC 74138 has done.

PRECAUTIONS:

(vii) All the IC’s should be checked before use the apparatus.
(viii) All LED’s should be checked.
(ix) All connections should be tight.
(x) Always connect GROUND first and then Vcc.
(xi) The circuit should be off before change the connections.
(xii) After completing t e experiment switches off the supply to
apparatus.

12
 lOMoAR cPSD| 38078257

EXPERIMENT NO-4
OBJECT:

Implementing 4x1 and 8x1 MULTIPLEXERS.

APPARATUS REQUIRED:

Sr. No. COMPONENT SPECIFICATION QTY.

1. 3 I/P AND GATE IC 7411 2
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
2. IC TRAINER KIT With IC 74151 1
3. PATCH CORDS 7404 - 32

THEORY:

MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a
smaller number of channels or lines. A digital multiplexer is a combinational
circuit that selects binary information from one of many input lines and directs
it to a single output line. The selection of a particular input line is controlled by
n
a set of selection lines. Normally there are 2 input line and n selection lines
whose bit combination determine which input is selected.

BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

13
 lOMoAR cPSD| 38078257

FUNCTION TABLE:

S1 S0 INPUTS Y
0 0 D0 → D0 S1’ S0’
0 1 D1 → D1 S1’ S0
1 0 D2 → D2 S1 S0’
1 1 D3 → D3 S1 S0

Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0

14
 lOMoAR cPSD| 38078257

PROCEDURE:

(iv) Connections are given as per circuit diagram.

(v) Logical inputs are given as per circuit diagram. (vi)
Observe the output and verify the truth table.
RESULT:

Thus the design and implementation of decoder and multiplexer using logic
gates and study of IC 74153 has done.

PRECAUTIONS:

(xiii) All the IC’s should be checked before use the apparatus.
(xiv) All LED’s should be checked.
(xv) All connections should be tight.
(xvi) Always connect GROUND first and then Vcc.
(xvii) The circuit should be off before change the connections.
(xviii) After completing t e experiment switches off the supply to apparatus.

15
 lOMoAR cPSD| 38078257

EXPERIMENT NO. – 5
OBJECT:

Verify the excitation tables of various FLIP-FLOPS.

APPARATUS REQUIRED:

IC 7400 (NAND Gate), IC 7402 (NOR Gate), IC 7408 (AND Gate).

BRIEF THEORY:

In case of sequential circuits the effect of all previous inputs on the outputs is represented by a
state of the circuit. Thus, the output of the circuit at any time depends upon its current state and
the input. These also determine the next state of the circuit .The relationship that exists among
the inputs, outputs, present states and next states can be specified by either the state table or
the state diagram.
State Table: The state table representation of a sequential circuit consists of three
sections labeled present state next state and output . The present state designates the
state of flip - flops before t h e occurrence of a clock pulse. The next state shows the
states of flip -flop s after the clock pulse , and the output section lists the value of the
output variables during the present state.
Flip-Flop: The basic one bit digital memory circuit is known as flip-flop. It can store either
0 or 1. Flip-flops are classifieds according to the number of inputs.
R-S Flip-Flop: The circuit is similar to SR latch except enable signal is replaced by clock
pulse.
Logic Diagram for S-R flip flop

Characteristic table for S-R flip flop

16
 lOMoAR cPSD| 38078257

D Flip-Flop: The modified clocked SR flip- flop is known as D-flip-flop. From the truth table of
SR flip-flop we see that the output of the SR flip-flop is in unpredictable state when the inputs
are same and high. In many practical applications, these input conditions are not required. These
input conditions can be avoided by making then complement of each other.

Logic Diagram for D flip flop

Characteristic table for D flip flop

J-K Flip-Flop : In a RS flip-flop the input R=S=1 leads to an indeterminate output.

The RS flip-flop circuit may be re-joined if both inputs are 1 than also the outputs
are complement of each other.
Logic Diagram for J-K flip flop

17
 lOMoAR cPSD| 38078257

Characteristic table for J-K flip flop

T Flip-Flop:-T flip-flop is known as toggle flip-flop. The T flip-flop is modification of

the J-K flip - flop . Both t h e J K inputs of t h e J K flip - flop are held at logic 1 and the clock
signal continuous to change.

Logic Diagram for T flip flop

Characteristic table for T flip flop

18
 lOMoAR cPSD| 38078257

PROCEDURE:

1. Connections are made as per circuit diagram.

2. Verify truth-tables for various combinations of input.

RESULT:-

Study and verified truth-tables of various flip-flops.

PRECAUTIONS:

1. All the IC’s should be checked before use the apparatus.

2. All LED’s should be checked.
3. All connections should be tight.
4. Always connect GROUND first and then Vcc
5. The circuit should be off before change the connections.
6. 6. After completing t e experiment switches off the supply to apparatus.

19
 lOMoAR cPSD| 38078257

EXPERIMENT NO. – 6

OBJECT: Design and study of 4/8-bit Input/ Output system shift register.

APPARATUS REQUIRED:

1. Experimental trainer board.

2. Bread board.
3. ICs 7495/74594/74161.
4. Connecting leads.

BRIEF THEORY:

Serial-in parallel-out (SIPO)

This configuration allows conversion from serial to parallel format. Data input is serial, as
described in the SISO section above. Once the data has been clocked in, it may be either read
off at each output simultaneously, or it can be shifted out.
In this configuration, each flip-flop is edge triggered. All flip-flops operate at the given clock
frequency. Each input bit makes its way down to the nth output after N clock cycles, leading
to parallel output.
In cases where the parallel outputs should not change during the serial loading process, it is
desirable to use a latched or buffered output. In a latched shift register (such as the 74595) the
serial data is first loaded into an internal buffer register, then upon receipt of a load signal the
state of the buffer register is copied into a set of output registers. In general, the practical
application of the serial-in/parallel-out shift register is to convert data from serial format on a
single wire to parallel format on multiple wires.

CIRCUIT DIAGRAM:

Pining Diagram for 4-bit SIPO:

20
 lOMoAR cPSD| 38078257

State table for 4-bit SIPO:

Clock Serial I/P Q0 Q1 Q2 Q3

1 0 0 x x x

2 1 1 0 x x

3 1 1 1 0 x

4 1 1 1 1 0

PROCEDURE:

1. Connections are made as per circuit diagram.

2. Apply the data at serial input.
3. Apply one clock pulse at clock 1 (right shift), observe this data at Q0.
4. Apply the next data at serial input.
5. Apply one clock pulse at clock 2 (right shift), observe that the data on Q0 will shift to Q1
and the new data applied will appear at Q1.
6. Repeat steps 2 and 3 till the 4- bits data are entered one by one into the shift register.

CIRCUIT DIAGRAM:

Circuit diagram of 4-bit SIPO shift resister:

21
 lOMoAR cPSD| 38078257

Timing waveform of SIPO shift resister:

22
 lOMoAR cPSD| 38078257

Circuit diagram of 8-bit SIPO shift resister:

RESULT:-

Shift register using IC 7495 in SIPO mode is verified.

PRECAUTIONS:

7. All the IC’s should be checked before use the apparatus.

8. All LED’s should be checked.
9. All connections should be tight.
10. Always connect GROUND first and then Vcc.
11. The circuit should be off before change the connections.
12. 6. After completing t e experiment switches off the supply to apparatus.

23
 lOMoAR cPSD| 38078257

EXPERIMENT NO. –7
OBJECT:

Design of a 4-bit ARITHMETIC LOGIC UNIT.

APPARATUS REQUIRED:

1. IC-74181.
2. Digital trainer.
3. Connecting leads.

BRIEF THEORY:

In computing, an arithmetic logic unit (ALU) is a digital circuit that performs arithmetic and
logical operations. The ALU is a fundamental building block of the central processing unit
(CPU).
ALU stands for the arithmetic and logical unit and is one of the important units in almost all
the calculating machine these days be it with the hand-held mobile, or computers. All the
computational work in the system is carried out by this unit. The typical ALU sizes are:
4-bit ALU: ALU that processes two 4-bit numbers.
8-bit ALU: ALU that processes two 8-bit numbers.
When the size of 4-bit ALU is to be increased to 8-bit operations two 74181 can be cascaded
and Cn+4 will be used as input to Cn line of next stage. The cascading is shown in figure-4.

CIRCUIT DIAGRAM

24
 lOMoAR cPSD| 38078257

Fig. 1: Experimental circuit diagram of ALU IC-74181.

Fig. 2: Pinning Diagram of ALU IC-74181.

Fig. 3: Connection diagram & pin description of ALU IC-74181.

25
 lOMoAR cPSD| 38078257

Fig. 4: Cascading of ALU IC-74181.

Function tables of ALU IC-74181:

26
 lOMoAR cPSD| 38078257

PROCEDURE:

As seen in figure-3, the ALU has two 4-bit input lines A3-A0, B3-B0, a 4-bit function select
lines S3-S0, one mode select line ‘M’ that is used to select ALU for either arithmetic or the
logical function. It has four output lines f3-f0, carry-in Cn is used in cascade mode. When the
size of 4-bit ALU is to be increased to 8-bit operations two 74181 can be cascaded and Cn+4
will be used as input to Cn line of next stage. The cascading is shown in figure-4.
1. Connections are made as shown in fig.1.
2. Change the values of the inputs and verify at least 5 functions given in the function
table.

RESULT:

The above circuit when connected to power supply gives correct result as per the function table.

PRECAUTIONS:

13. All the IC’s should be checked before use the apparatus.
14. All LED’s should be checked.
15. All connections should be tight.
16. Always connect GROUND first and then Vcc
17. The circuit should be off before change the connections.
18. 6. After completing the experiment switches off the supply to apparatus.

27