1. Explain in detail Architecture of 8086.

The 8086 microprocessor, designed by Intel and introduced in 1978, is a 16-bit microprocessor, which
means it can process 16 bits of data at a time. It has a 20-bit address bus, enabling it to access a memory
range of 1MB (2^20 bytes). It is known for its use in embedded systems, personal computers, and other
electronic applications. Here's a detailed explanation of its architecture:
Architecture of 8086:
The 8086 microprocessor consists of several components that work together to perform various
operations. These components include:
Execution Unit (EU)
Bus Interface Unit (BIU)
Registers
Flags Register
ALU (Arithmetic and Logic Unit)
Let's break down each part:

1. Execution Unit (EU):

The Execution Unit (EU) is responsible for executing instructions and performing arithmetic and logic
operations. It handles the actual data processing and control logic required for executing instructions.
The EU consists of the following parts:
Arithmetic and Logic Unit (ALU):
Performs arithmetic operations like addition, subtraction, multiplication, division, etc.
Handles logical operations like AND, OR, XOR, NOT.
Also manages the shift operations.
Control Unit:
Decodes and directs the operation of the microprocessor.
It fetches instructions from memory, decodes them, and manages their execution.
Controls the sequence of operations based on the instructions it gets.

2. Bus Interface Unit (BIU):

The Bus Interface Unit (BIU) is responsible for interfacing with the system's buses and handling
communication between the microprocessor and external components like memory and input/output
devices. It consists of:
Segment Registers: These registers (CS, DS, SS, and ES) hold the addresses of the segments in memory.
The 8086 processor uses segment addressing for memory access. Each segment is 64KB in size, and the
CPU can address up to 1MB of memory.
Instruction Queue:
The BIU has a 6-byte instruction queue that pre-fetches instructions from memory.
This improves the performance of the 8086 by enabling it to fetch the next instruction while the
previous one is being executed. This mechanism is called pipelining.
Address Generation Unit (AGU):
Responsible for generating memory addresses by combining the contents of segment registers and an
offset.
Data Bus Buffer:
Responsible for transferring data between the processor and external devices.

3. Registers:
The 8086 has 14 registers, divided into several categories:
General Purpose Registers (8-bit and 16-bit):
AX (Accumulator Register): Used for arithmetic, logic, and data transfer operations. It is often used for
I/O operations.
BX (Base Register): It is used for addressing data in memory.
CX (Count Register): Often used for loop control and repeated operations.
DX (Data Register): Used in operations that require a larger range (e.g., multiplication and division).
The 16-bit versions of these registers can be broken into two 8-bit registers:
AH, AL (for AX)
BH, BL (for BX)
CH, CL (for CX)
DH, DL (for DX)
Pointer and Index Registers (16-bit):
SP (Stack Pointer): Points to the top of the stack. It helps in the operation of function calls and returns.
BP (Base Pointer): Used to access data in the stack.
SI (Source Index): Used for string operations and points to the source of data.
DI (Destination Index): Used for string operations and points to the destination of data.
Segment Registers (16-bit):
CS (Code Segment): Contains the base address of the code segment.
DS (Data Segment): Contains the base address of the data segment.
SS (Stack Segment): Contains the base address of the stack segment.
ES (Extra Segment): Used as an additional data segment.
Flags Register (16-bit):
The 8086 has a 16-bit flag register (also called the status register) that contains individual flag bits that
represent the outcome of operations and help control the execution flow.
Sign Flag (SF): Set if the result of the operation is negative.
Zero Flag (ZF): Set if the result of the operation is zero.
Auxiliary Carry Flag (AF): Used in BCD arithmetic operations.
Parity Flag (PF): Set if the result has an even number of 1-bits.
Carry Flag (CF): Set if there is a carry in or out of the most significant bit during arithmetic operations.
Overflow Flag (OF): Set if there is a signed overflow in an arithmetic operation.

4. ALU (Arithmetic and Logic Unit):

The ALU is the core of the processor’s ability to perform operations. It performs operations like:
Arithmetic Operations: Addition, subtraction, multiplication, division.
Logical Operations: AND, OR, XOR, NOT.
Shift Operations: Shift left, shift right.
Comparisons: Used for branching based on conditions.

5. Instruction Set and Pipelining:

The 8086 microprocessor supports a rich instruction set that includes a variety of data transfer,
arithmetic, logic, branching, and control instructions.
Pipelining: The instruction queue in the BIU allows for pipelining, where the next instruction is fetched
while the current instruction is being executed. This increases the processor’s efficiency and reduces idle
time.

6. Memory Segmentation:
One of the distinctive features of the 8086 architecture is its segmented memory model. The processor
uses 20-bit addressing to access 1MB of memory. This memory is divided into segments, each of which
is 64KB in size. The 8086 uses segment registers (CS, DS, SS, and ES) to handle different parts of
memory.
The processor calculates memory addresses using a combination of segment registers and offset
addresses. For example:
Physical Address = (Segment * 16) + Offset
This allows the processor to access different parts of memory efficiently.
2. Explain register organization/programmers model of 8086.
It is one of the most important chips ever created due to its part in the development of x86-based
architecture. One significant aspect of this microprocessor is that it contains general registers. Efficiency
and speed of computations in the processor are influenced by these registers since they determine
arithmetic operations execution and data manipulations. Understanding such registers is important for
code optimization as well as assembly language programming and system design.
The 8086 microprocessor contains a set of 16-bit general-purpose registers which are used for
performing various arithmetic, logical, and data movement operations. Since these registers are flexible
and can assume different combinations to perform various functions, they form the basic operation
units of the processor itself.

General-purpose registers are used to store temporary data within the microprocessor
There are 8 general-purpose registers in the 8086 microprocessor.
1. AX: This is the accumulator. It is of 16 bits and is divided into two 8-bit registers AH and AL to also
perform 8-bit instructions. It is generally used for arithmetical and logical instructions but in 8086
microprocessor it is not mandatory to have an accumulator as the destination operand. Example:
ADD AX, AX (AX = AX + AX)
2. BX: This is the base register. It is of 16 bits and is divided into two 8-bit registers BH and BL to also
perform 8-bit instructions. It is used to store the value of the offset. Example:
MOV BL, [500] (BL = 500H)
3. CX: This is the counter register. It is of 16 bits and is divided into two 8-bit registers CH and CL to also
perform 8-bit instructions. It is used in looping and rotation. Example:
MOV CX, 0005
LOOP
4. DX: This is the data register. It is of 16 bits and is divided into two 8-bit registers DH and DL to also
perform 8-bit instructions. It is used in the multiplication and input/output port addressing. Example:
MUL BX (DX, AX = AX * BX)
5. SP: This is the stack pointer. It is of 16 bits. It points to the topmost item of the stack. If the stack is
empty the stack pointer will be (FFFE)H. Its offset address is relative to the stack segment.
It is AB and manage the present position of the top of the stack.
Example: To push or pop data from the stack in a function call, the SP is altered.
PUSH R1 ; Decrement the SP and then store the value of R1 that is at SP.
R1 = POP; R1 = increment SP; R1 = get value in SP
6. BP – This is the base pointer. It is of 16 bits. It is primarily used in accessing parameters passed by the
stack. Its offset address is relative to the stack segment.
MOV AX, [BP+4] ; Access a parameter passed to the function
(4 bytes above BP in the Stack)
7. SI – This is the source index register. It is of 16 bits. It is used in the pointer addressing of data and as a
source in some string-related operations. Its offset is relative to the data segment.
MOV AL, [SI] ; Move the byte at the address pointed to by SI into the AL
register
(used as a pointer to source data).
8.DI – This is the destination index register. It is of 16 bits. It is used in the pointer addressing of data and
as a destination in some string-related operations. Its offset is relative to the extra segment.
MOV [DI], AL; Move the byte in AL to the address pointed to by DI
(serves as the destination for the data).

3.Explain memory banking.

The 8086 processor provides a 16-bit data bus. So It is capable of transferring 16 bits in one
cycle but each memory location is only of a byte(8 bits), therefore we need two cycles to access
16 bits(8 bit each) from two different memory locations. The solution to this problem is
Memory Banking. Through Memory banking, our goal is to access two consecutive memory
locations in one cycle(transfer 16 bits).
The memory chip is equally divided into two parts(banks). One of the banks contains even
addresses called Even bank and the other contains odd addresses called Odd bank. Even bank
always gives lower byte So Even bank is also called Lower bank(LB) and Odd bank is also
called Higher bank(HB).
This banking scheme allows to access two aligned memory locations from both banks
simultaneously and process 16-bit data transfer. Memory banking doesn’t make it compulsory
to transfer 16 bits, it facilitates the 16-bit data transfer.
The choice between 8 bit and 16-bit transfer depends on the instructions given by the
programmer.
Example:
The Least Significant bit of address (A0 is not used for byte selection) is reserved for bank
selection. Therefore A0=0 will select Even bank. The BHE signal is used for the selection of odd
banks. The processor will use a combination of these two signals to decide the type of data
transfer.

BHE A0 types of Transfer

0 0 16-0bit data transfer from both HB and LB
0 1 8-bit data transfer from HB
1 0 8-bit data transfer from LB
1 1 None(Idle)
In this case, the first machine cycle generates an odd address (A0=1) transfer lower order 8 data
bits on a higher-order data bus. In the second machine cycle, the higher-order data bus will be
transferred to the lower-order data bus.
4. Explain memory segmentation.
Segmentation is the process in which the main memory of the computer is logically divided into
different segments and each segment has its own base address. It is basically used to enhance the speed
of execution of the computer system, so that the processor is able to fetch and execute the data from
the memory easily and fast.
Need for Segmentation –
The Bus Interface Unit (BIU) contains four 16 bit special purpose registers (mentioned below) called as
Segment Registers.
Code segment register (CS): is used for addressing memory location in the code segment of the
memory, where the executable program is stored.
Data segment register (DS): points to the data segment of the memory where the data is stored.
Extra Segment Register (ES): also refers to a segment in the memory which is another data segment in
the memory.
Stack Segment Register (SS): is used for addressing stack segment of the memory. The stack segment is
that segment of memory which is used to store stack data.
The number of address lines in 8086 is 20, 8086 BIU will send 20bit address, so as to access one of the
1MB memory locations. The four segment registers actually contain the upper 16 bits of the starting
addresses of the four memory segments of 64 KB each with which the 8086 is working at that instant of
time. A segment is a logical unit of memory that may be up to 64 kilobytes long. Each segment is made
up of contiguous memory locations. It is an independent, separately addressable unit. Starting address
will always be changing. It will not be fixed.
Note that the 8086 does not work the whole 1MB memory at any given time. However, it works only
with four 64KB segments within the whole 1MB memory.
Below is the one way of positioning four 64 kilobyte segments within the 1M byte memory space of an
8086.
Types Of Segmentation –
Overlapping Segment – A segment starts at a particular address and its maximum size can go up to
64kilobytes. But if another segment starts along with this 64kilobytes location of the first segment, then
the two are said to be Overlapping Segment.
Non-Overlapped Segment – A segment starts at a particular address and its maximum size can go up to
64kilobytes. But if another segment starts before this 64kilobytes location of the first segment, then the
two segments are said to be Non-Overlapped Segment.
Rules of Segmentation Segmentation process follows some rules as follows:
The starting address of a segment should be such that it can be evenly divided by 16.
Minimum size of a segment can be 16 bytes and the maximum can be 64 kB.

5. Explain minimum mode with read and write cycle timing

diagram.
Control signals provided by 8086 for memory operations and i/o interfacing :
They are used to identifying whether the bus is carrying a valid address or not , in which
direction data is needed to be transferred over the bus, when there is valid write data on the
data bus and when to put read data on the system bus. Therefore, their sequence pattern
makes all the operations successful in a particular machine cycle.
Min mode circuit
8282 (8 bits) latch :
The latches are buffered D FF. They are used to separate the valid address from the multiplexed
Address/data bus by using the control signal ALE, which is connected to strobe(STB) of 8282.
The ALE is active high signal. Here three such latches are required because the address is 20
bits.
8286 (8 bits) transceivers :
They are bidirectional buffers and also known as data amplifiers. They are used to separate the
valid data from multiplexed add/data bus. Two such transceivers are needed because the data
bus is 16 bits long. 8286 is connected to DT/R’ and DEN’ signals. They are enabled through the
DEN signal .The direction of data on the data bus is controlled by the DT/R’ signal. DT/R’ is
connected to T and DEN’ is connected to OE’.

Direction of data flow

8284 clock generator is used to provide the clock.
M/IO’= 1,then I/O transfer is performed over the bus. and when M/IO’ = 0, then I/O operation
is performed.
The signals RD’ and write WR’ are used to identify whether a read bus cycle or a write bus cycle
is performing. When WR’ = 0 ,then it indicates that valid output data on the data bus.
RD’ indicates that the 8086 is performing a read data or instruction fetch process is occurring
.During read operations, one other control signal is also used, which is DEN ( data enable) and it
indicates the external devices when they should put data on the bus.
Control signals for all operations are generated by decoding M/IO’, RD’, WR’. They are decoded
by 74138 3:8 decoder.

INTR and INTA :

When INTR = 1,then there is an interrupt to 8086 by other devices for their service. When
INTA’= 0,then it indicates that the processor is ready to service them.
The bus request is made by other devices using the HOLD signal and the processor
acknowledges them using the HLDA output signal.
For more details about the 8086 minimum mode pins please refer(this article).
Timing diagram :
The working of min mode can be easily understood by timing diagrams.
All processors bus cycle is of at least 4 T-states(T1,T2,T3,T4) .The address is given by processor in
the T1 state. It is available on the bus for one T-state.
In T2, the bus is tristated for changing the direction of the bus( in the case of a data read cycle.)
The data transfer takes place between T3 and T4.
If the addressed device is slower, then the wait state is inserted between T 3 and T4.

Opcode fetch or read timing diagram

At T1 state ALE =1 ,this indicates that a valid address is latched on the address bus and also M /
IO’= 1, which indicates the memory operation is in progress.
In T2, the address is removed from the local bus and is sent to the addressed device. Then the
bus is tristated.
When RD’ = 0 , the valid data is present on the data bus.
During T2 DEN’ =0, which enables transceivers and DT/R’ = 0 ,which indicates that the data is
received.
During T3, data is put on the data bus and the processor reads it.
The output device makes the READY line high. This means the output device has performed the
data transfer process. When the processor makes the read signal to 1, then the output device
will again tristate its bus drivers.

Write memory cycle

At T1 state ALE =1 ,this indicates that a valid address is latched on the address bus and also M /
IO’= 1, which indicates the memory operation is in progress.
In T2, the processor sends the data to be written to the addressed location.
The data is buffered on the bus until the middle of T4 state.
The WR’=0 becomes at the beginning of T2.
The BHE’ and A0 signals are used to select the byte or bytes of memory or I/O word.
During T2 DEN’ =0, which enables, transceivers and DT/R’ = 1 ,which indicates that the data is
transferred by the processor to the addressed device.
6. Explain maximum mode with read and write cycle timing
diagram.
The 8086 microprocessor is an 8-bit/16-bit microprocessor designed by Intel in the late 1970s. It is the
first member of the x86 family of microprocessors, which includes many popular CPUs used in personal
computers. The architecture of the 8086 microprocessor is based on a complex instruction set computer
(CISC) architecture, which means that it supports a wide range of instructions, many of which can
perform multiple operations in a single instruction.
8086 Microprocessor Characteristics
It contains 20 bit address bus.
It contains 16-bit data bus, therefore 8086 is called as 16-bit microprocessor.
It is 2-stage pipelined processor. It can prefetch 6 bytes from memory and store into queue to increase
the speed of the execution.
It’s control bus carries signals for executing operations such as read ,write etc.
It has Memory Banks. 2 banks of 512KB each. These banks are called as lower Bank (even) and higher
Bank (odd).
In 8086 the entire memory is divided into four memory segments which are code ,stack, data and extra
segment.
8086 has 16 bit IO address.
It has 256 interrupts.
Operating Modes of 8086
Minimum Mode
In this 8086 is the only processor in the system . In a minimum mode 8086 system.
8086 is operated in minimum mode when MN/MX’ pin to logic 1.
In this mode, all the control signals are given out by the 8086 itself.
Maximum Mode
In this we can connect more processors to 8086 (8087/8089).
8086 max mode is basically for implementation of allocation of global resources and passing bus control
to other coprocessor(i.e. second processor in the system), because two processors can not access
system bus at same instant.
All processors execute their own program.
The resources which are common to all processors are known as global resources.
The resources which are allocated to a particular processor are known as local or private resources.

Maximum mode circuit

Circuit Explanation
When MN/ MX’ = 0 , 8086 works in max mode.
Clock is provided by 8284 clock generator.
8288 bus controller- Address form the address bus is latched into 8282 8-bit latch. Three such latches
are required because address bus is 20 bit. The ALE(Address latch enable) is connected to STB(Strobe)
of the latch. The ALE for latch is given by 8288 bus controller.
The data bus is operated through 8286 8-bit transceiver. Two such transceivers are required,
because data bus is 16-bit. The transceivers are enabled the DEN signal, while the direction of data is
controlled by the DT/R signal. DEN is connected to OE’ and DT/ R’ is connected to T. Both DEN and DT/
R’ are given by 8288 bus controller.

Control signals for all operations are generated by decoding S’2, S’1 and S’0 using 8288 bus controller.
Bus request is done using RQ’ / GT’ lines interfaced with 8086. RQ0/GT0 has more priority than
RQ1/GT1.
INTA’ is given by 8288, in response to an interrupt on INTR line of 8086.
In max mode, the advanced write signals get enabled one T-state in advance as compared to normal
write signals. This gives slower devices more time to get ready to accept the data, therefore it reduces
the number of cycles.
Advantages of Max Mode of 8086
It helps to interface more devices like 8087.This interface is also called a closely coupled co-Processor
configuration. In this 8086 is called as the host and 8087 as Co-processor.
It supports multiprocessing, Therefore it helps to increase the efficiency.
The 8087 was the first floating-point coprocessor for the 8086 series of microprocessors. The purpose of
the 8087 was to increase calculations for floating point operations, such as add, sub, multiply, divide,
and square root.
Disadvantages of Max Mode Over Min Mode
It has more complex circuit than min mode.
The increased complexity of max mode leads to higher costs due to the need for additional components
like the 8288 bus controller and potentially more sophisticated circuitry.
Applications of 8086
Microcomputer are built using 8086. For example : IBM PC, used the Intel 8088, a version of the 8086
with 8-bit data bus.
It is used in calculators.
It is used for control purposes like in traffic signals(uses micro controllers which are nothing but contains
one or more CPUs along with memory and programmable I/O peripherals)
7. Explain Interrupt structure of 8086
An interrupt is a condition that halts the microprocessor temporarily to work on a different task and
then returns to its previous task. An interrupt is an event or signal that requests the CPU’s attention.
This halt allows peripheral devices to access the microprocessor. Whenever an interrupt occurs, the
processor completes the current instruction and starts the implementation of an Interrupt Service
Routine (ISR) or Interrupt Handler. ISR is a program that tells the processor what to do when the
interrupt occurs. After the ISR execution, control returns to the main routine where it was interrupted.
In the 8086 microprocessor following tasks are performed when the microprocessor encounters an
interrupt:
The value of the flag register is pushed into the stack. It means that first, the value of SP (Stack Pointer)
is decremented by two then the value of the flag register is pushed to the memory address of the stack
segment.
The value of starting memory address of CS (Code Segment) is pushed into the stack.
The value of IP (Instruction Pointer) is pushed into the stack.
IP is loaded from word location (Interrupt type) * 04.
CS is loaded from the following word location.
Interrupt, and Trap flags are reset to 0.
The different types of interrupts present in the 8086 microprocessor are given by:
Hardware Interrupts – Hardware interrupts are those interrupts that are caused by any peripheral
device by sending a signal through a specified pin to the microprocessor. There are two hardware
interrupts in the 8086 microprocessor. They are:
NMI (Non-Maskable Interrupt): It is a single pin non-maskable hardware interrupt that cannot be
disabled. It is the highest priority interrupt in the 8086 microprocessor. After its execution, this interrupt
generates a TYPE 2 interrupt. IP is loaded from word location 00008 H, and CS is loaded from the word
location 0000A H.
INTR (Interrupt Request): It provides a single interrupt request and is activated by the I/O port. This
interrupt can be masked or delayed. It is a level-triggered interrupt. It can receive any interrupt type, so
the value of IP and CS will change on the interrupt type received.
Software Interrupts – These are instructions inserted within the program to generate interrupts. There
are 256 software interrupts in the 8086 microprocessor. The instructions are of the format INT type,
where the type ranges from 00 to FF. The starting address ranges from 00000 H to 003FF H. These are 2-
byte instructions. IP is loaded from type * 04 H, and CS is loaded from the following address given by
(type * 04) + 02 H. Some important software interrupts are:
TYPE 0 corresponds to division by zero(0).
TYPE 1 is used for single-step execution for debugging the program.
TYPE 2 represents NMI and is used in power failure conditions.
TYPE 3 represents a break-point interrupt.
TYPE 4 is the overflow interrupt.