INTRODUCTION

TO
MICROPROCESSOR
8086 and 8088
 Topics Covered

Introduction to 8086 and 8088

TOPICS Pin Diagram of 8086 and 8088

Pin Functions (Key Signals)

Minimum and Maximum Mode

Configurations

Read/ Write Bus Cycle

Introduction to 8086 and 8088

The 8086 and 8088 are 16-bit microprocessors developed by Intel.

8086 was released in 1978, while 8088 was introduced later with a modified data
bus.

Used in early personal computers, including the IBM PC.

They employ segmented memory architecture, dividing memory into

segments for code, data, and stack operations.
PIN
CONFIGURATION
of 8086 and 8088
The 8086 has 40 pins and operates in minimum or maximum mode.

The 8086 has an 16 bit data bus and 20 bit address bus .

The 8088 also has a 40 pins and operates in minimum and maximum mode
.
The 8088 has an 8 bit data bus and 20 bit address bus .

The key difference between these

two devices is in their hardware
architecture .
FULL FORMS :
VCC (Voltage Common Collector)

GND (Ground reference).

CLK (Clock Input)

AD0-AD15 in 8086 / AD0-AD7 in 8088 (Address/Data bus)

A16-A19(Address Bus)

ALE (Address Latch Enable)

DT/R (Data Transmit/Receive)

DEN (Data Enable)

RD (Read Control Signal)

FULL FORMS :
WR (Write Control Signal)

M/IO (Memory/IO Select)

INTR (Interrupt Request)

NMI (Non-Maskable Interrupt)

INTA (Interrupt Knowledge)

HOLD (Hold Request )

HLDR (Hold Acknowlegde)

SSO (Status Line )

BHE(Bus High Enable)

Pin Functions
VCC : Power Supply

GND – Ground reference.

CLK (Clock Input) – Provides timing for processor operations.

AD0-AD15 (8086) / AD0-AD7 (8088) – Multiplexed Address/Data lines.

A16-A19 – Higher address lines used for memory addressing.

ALE (Address Latch Enable) – Differentiates address and data phase.

DT/R (Data Transmit/Receive) – Indicates direction of data flow.

DEN (Data Enable) – Enables external data bus.

Pin Functions
RD (Read Control Signal) – Used for memory read operation.

WR (Write Control Signal) – Used for memory write operation.

M/IO (Memory/IO Select) – Differentiates between memory and I/O access.

INTR (Interrupt Request) – Used for interrupt-driven processing.

NMI (Non-Maskable Interrupt) – High priority interrupt.

INTA (Interrupt Acknowledge) – Acknowledges an interrupt request.

HOLD (Hold Request) – Indicates that another device is requesting control of

the system bus.
HLDA (Hold Acknowledge) – Acknowledges the HOLD signal and grants the
bus control.
Pin Functions
SSO (System Status Output) – Used in maximum mode to indicate processor
status.

WR (Write Control Signal) – Used for memory write operation.

RESET – Resets the processor.

Minimum and Maximum Mode Configurations
Minimum Mode (Single Processor Mode):

Used when only one processor is present in the system.

Control signals are internally generated by the processor.

Suitable for small systems where a simple design is preferred.

Key signals used: M/IO, WR, RD, ALE, DT/R, DEN, INTA.

No need for an external bus controller.

Address bus is used to carry address information to the memory . AD is 20 bit long and
consist of signal lines A0 - A19

In 8088 , D0-D7 multiplexed with address line A0-A7 .For this reason they are denoted as
AD0-AD7
Minimum and Maximum Mode Configurations
Minimum Mode (Single Processor Mode):

In 8086, data lines are multiplexed with address line A0-A15 and therefore denoted as
AD0 -AD15
Status bits are the output on the bus at the same times that data are transferred over
the other bus line

STATUS BITS

S3-S4 S6
Identify which of the internal segment was used to generate the Always at the o logic level
physical address that was output on the the address bus during the
current bus cycle

S5
Reflect the status of other internal characterstic of MPU
Minimum Mode (Single Processor Mode):
Minimum and Maximum Mode Configurations

Maximum Mode (Multiprocessor Mode):

Used in systems with multiple processors or co-processors.

Requires an external bus controller (Intel 8288) to generate necessary control signals.

Supports coprocessing and multitasking, allowing the use of external devices like DMA
controllers.
Additional control signals are introduced: S0, S1, S2 (Status Signals), RQ/GT0, RQ/GT1
(Request/Grant Signals).
Minimum and Maximum Mode Configurations

Maximum Mode (Multiprocessor Mode):

Bus Commands in Maximum Mode:

In maximum mode, the 8086/8088 processor uses bus commands to communicate with
memory and I/O devices via the 8288 bus controller. These commands are decoded from
status signals (S0, S1, S2) and control the overall system operation. The key bus commands
include:

Interrupt Acknowledge – Used when the processor acknowledges an interrupt request.

Read I/O Port – Reads data from an input/output device.

Write I/O Port – Writes data to an input/output device.

Maximum Mode (Multiprocessor Mode):

Control Signals in Maximum Mode:

MRDC (Memory Read Command) – Initiates a memory read cycle.

MWTC (Memory Write Command) – Initiates a memory write cycle.

IORC (I/O Read Command) – Used to read data from an I/O device.

IOWC (I/O Write Command) – Used to write data to an I/O device.

INTA (Interrupt Acknowledge) – Acknowledges an interrupt request.

ALE (Address Latch Enable) – Helps differentiate address and data phases.

DT/R (Data Transmit/Receive) – Controls data direction.

DEN (Data Enable) – Enables external data bus during read/write operations

RQ/GT0 and RQ/GT1 (Request/Grant Signals) – Used to request and grant access to
the system bus in multiprocessor environments.
Maximum Mode (Multiprocessor Mode):

Lock Signals in Maximum Mode:

LOCK – Prevents other processors from accessing the system bus during critical operations.

Queue Status Signals (QS0, QS1)

Indicate the status of the internal instruction queue:

QS0 = 00: Queue is empty.

QS0 = 01: First byte of the instruction is fetched.

QS0 = 10: Subsequent bytes are being fetched.

QS0 = 11: Queue is full.

READ AND WRITE BUS CYCLE
A Read and Write Bus Cycle refers to the sequence of operations involved when a processor
or other device communicates with memory or an I/O device over a bus. These cycles are
fundamental to computer architecture and help in transferring data between components.

Signals & functions

we will be using

BUS CYCLE is the time required to make

a single read or write operation between
microprocessors , memory, I/O devices
READ BUS CYCLE 8088 MINIMUM
READ BUS CYCLE 8086 MINIMUM
READ BUS CYCLE 8086 MAXIMUM
WRITE BUS CYCLE 8088
MINIMUM
WRITE BUS CYCLE 8086
MAXIMUM
Thank you!