M1 – Introduction

Architecture vs. Organization

 Outline
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Components of the System
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Instructions
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Architecture vs. Organization
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The Compute Stack
 Computer
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Programs
– Instructions and Data
 Computer
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Programs
– Instructions and Data
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Computer: An electronic device which is capable
of receiving information (data) and performing a
sequence of operations defined by instructions
(program) to produce a result in the form of
information
 Instructions
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Tasks that a processor can execute
– eg. add, mul, beq, load, store, call, ...
 Instructions
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Tasks that a processor can execute
– eg. add, mul, beq, load, store, call, ...
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Defined in the “Instruction Set Architecture
(ISA)”
 Instructions
●
Tasks that a processor can execute
– eg. add, mul, beq, load, store, call, ...
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Defined in the “Instruction Set Architecture
(ISA)”
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Several ISAs exist
– RISC-V, POWER, MIPS, ARM, x86, ...
 Instructions
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Which instructions to implement?
 Instructions
●
Which instructions to implement?
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Desktop publishing vs. Gaming
– Integer operations vs. Floating point operations
 Instructions
●
Which instructions to implement?
●
Desktop publishing vs. Gaming
– Integer operations vs. Floating point operations
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Database program vs. Video processing
– I/O processing vs. Floating point operations
 Instructions
●
Which instructions to implement?
●
Desktop publishing vs. Gaming
– Integer operations vs. Floating point operations
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Database program vs. Video processing
– I/O processing vs. Floating point operations
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Some fundamental instructions exist
– Arithmetic, Logic, Memory transfer, Control
statements, Privileged instructions, ...
 Instruction Tasks
aa == bb ++ c;
c;

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Compiler converts a=b+c into a list of tasks
the processor can accomplish
 Instruction Tasks
aa == bb ++ c;
c;

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Compiler converts a=b+c into a list of tasks the
processor can accomplish
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Inputs: b and c. Output: a. Operation: addition.
 Instruction Tasks
aa == bb ++ c;
c;

●
Compiler converts a=b+c into a list of tasks the
processor can accomplish
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Inputs: b and c. Output: a. Operation: addition.
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Addition operations is performed in the
Processor
– Arithmetic and Logic Unit
 Instruction Tasks
aa == bb ++ c;
c;

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Compiler converts a=b+c into a list of tasks the
processor can accomplish
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Inputs: b and c. Output: a. Operation: addition.
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Addition operations is performed in the Processor
– Arithmetic and Logic Unit
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a, b, and c are in the Memory
– Assume: they have to be inside the processor for
addition to begin
Minor
MinorDetour
Detour--
Memory
Memory
 The Program in Memory
Simplified View

Last Byte

DATA
DATA

Data begins here

Instructions end here

INSTRUCTIONS
INSTRUCTIONS

Byte 0
 The Program in Memory
Simplified View

DATA
DATA

a b c

INSTRUCTIONS
INSTRUCTIONS

a, b, and c identify unique

More details later !
locations in program memory!
 Instruction Tasks
aa == bb ++ c;
c;

PROCESSOR
PROCESSOR MEMORY
MEMORY

Interconnect
Interconnect

I/O
I/ODevices
Devices I/O
I/ODevices
Devices I/O
I/ODevices
Devices
 Instruction Tasks
aa == bb ++ c;
c;

PROCESSOR MEMORY

Interconnect
Interconnect
1
Instruction Tasks
aa == bb ++ c;
c;

PROCESSOR MEMORY

(1)

Interconnect
Interconnect

(1) Processor requests for value at location ‘b’ from memory

1
Instruction Tasks
aa == bb ++ c;
c;

PROCESSOR MEMORY

(1) (2)

(1) Processor requests for value at location ‘b’ from memory

(2) Memory sends value at location ‘b’ to the processor
1
Instruction Tasks
aa == bb ++ c;
c; LOAD
LOADbb

PROCESSOR MEMORY

(1) (2)

(1) Processor requests for value at location ‘b’ from memory

(2) Memory sends value at location ‘b’ to the processor
2
Instruction Tasks
aa == bb ++ c;
c; LOAD
LOADcc

PROCESSOR MEMORY

(1) (2)

(1) Processor requests for value at location ‘b’ from memory

(2) Memory sends value at location ‘b’ to the processor
3
Instruction Tasks
aa == bb ++ c;
c;

b
c
+ b+c MEMORY

Add values from ‘b’ and ‘c’

4
Instruction Tasks
aa == bb ++ c;
c; STORE

b+c
+ MEMORY

Processor sends the sum to memory to put in location ‘a’

 Instruction Tasks
aa == bb ++ c;
c;

●
Load value from memory location b
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Load value from memory location c
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Add these values
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Store sum into memory location ‘a’

Load
Loadand
andStore
Storeare
arememory
memorytransfer
transferoperations.
operations.
Add
Addisisan
anALU
ALUoperation
operation
 Instruction Tasks
Load
Load bb
Load
Load cc
aa == bb ++ c;
c;
Add
Add
Store
Store aa

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Load value from memory location b
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Load value from memory location c
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Add these values
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Store sum into memory location ‘a’
 Instruction Tasks

aa == bb ++ c;
c;
dd == bb ++ cc ++ a;
a;
ff == dd ++ aa ++ e;
e;

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List the fundamental tasks.
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Observations?
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Can you improve on the design?
 Instruction Tasks

aa == bb ++ c;
c;
dd == bb ++ cc ++ a;
a;
ff == dd ++ aa ++ e;
e;

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Loads are repeated – b, c, a.
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Store and Load pairs – a, d.
 Instruction Tasks

aa == bb ++ c;
c;
dd == bb ++ cc ++ a;
a;
ff == dd ++ aa ++ e;
e;

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Loads are repeated – b, c, a.
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Store and Load pairs – a, d.
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Eliminate repetitive/redundant operations
– Store intermediate results
– Register File (RF)
 x0
x1
Register File ...
x31

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Fast storage for quick access by the processor
 x0
x1
Register File ...
x31

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Fast storage for quick access by the processor
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Small number of data elements Eg. 32.
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Accessed as registers x0, x1, x2, … x31.
 x0
x1
Register File ...
x31

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Fast storage for quick access by the processor
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Small number of data elements Eg. 32.
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Accessed as registers x0, x1, x2, … x31.
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“load from memory into the processor” = “fetch
data from memory and write into Register File”
 x0
x1
Register File ...
x31

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Fast storage for quick access by the processor
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Small number of data elements Eg. 32.
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Accessed as registers x0, x1, x2, … x31.
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“load from memory into the processor” = “fetch
data from memory and write into Register File”
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Loaded values go in the RF; Results of
computations go into the RF; Values from RF
can be stored into memory
Instruction Tasks
Load x1, b
Load x2, c
aa == bb ++ c;
c; Add x3, x1, x2
Store x3, a
 Instruction Tasks
Load x1, b
Load x2, c
aa == bb ++ c;
c; Add x3, x1, x2
Store x3, a

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Load value from memory location b into x1
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Load value from from memory location c into x2
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Add contents of x1 and x2 and save the sum into
x3
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Store contents of x3 into memory location ‘a’
The Computer System

+ RF
MEMORY
MEMORY
ALU

Interconnect
Interconnect

I/O
I/ODevices
Devices I/O
I/ODevices
Devices I/O
I/ODevices
Devices
 Assembly Level Language
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Expression of high level language statements as
their fundamental tasks
 Assembly Level Language
●
Expression of high level language statements as
their fundamental tasks
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1-to-1 mapping to the binary code
 Assembly Level Language
●
Expression of high level language statements as
their fundamental tasks
●
1-to-1 mapping to the binary code
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ISA – list of instructions implemented in the
processor
 Assembly Level Language
●
Expression of high level language statements as
their fundamental tasks
●
1-to-1 mapping to the binary code
●
ISA – list of instructions implemented in the
processor
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Specific to a processor
 Assembly Level Language
Assembly Level
High Level Language Statements Binary Code
Language
Statement Load
Loadx1,
x1,bb 10010111000011110000111100001111
10010111000011110000111100001111
Load
Loadx2,
x2,cc 01100011001001001111110000111001
01100011001001001111110000111001
aa==bb++c;
c; 00100100110110011000111100001111
Add
Addx3,
x3,x1,
x1,x2
x2 00100100110110011000111100001111
Store 01001100110000111100010110010111
Storex3,
x3,aa 01001100110000111100010110010111
 Instruction Set Architecture
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Also called “Architecture”
●
Informally, a list of capabilities of the processor
 Instruction Set Architecture
●
Also called “Architecture”
●
Informally, a list of capabilities of the processor
– What operations are supported by this processor?
 Instruction Set Architecture
●
Also called “Architecture”
●
Informally, a list of capabilities of the processor
– What operations are supported by this processor?
– What kind of data does the operation act on?
 Instruction Set Architecture
●
Also called “Architecture”
●
Informally, a list of capabilities of the processor
– What operations are supported by this processor?
– What kind of data does the operation act on?
– Where does the data for the operation come from?
 Instruction Set Architecture
●
Also called “Architecture”
●
Informally, a list of capabilities of the processor
– What operations are supported by this processor?
– What kind of data does the operation act on?
– Where does the data for the operation come from?
– Which types of data are valid for an operation.
 Instruction Set Architecture
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Also called “Architecture”
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Defines instructions (operations) the processor
implements (supports)
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Input operands – number, size, type
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Input from Memory or from Registers
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Data Representation – Types/Sizes
ADD x3, x2, x1
 ADD x3, x2, x1
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Operation: ADD. Input operands: x1, x2. Output
Operand: x3
 ADD x3, x2, x1
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Operation: ADD. Input operands: x1, x2. Output
Operand: x3.
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Both input operands are 32b signed integers (x1
and x2)
– vs. ADDU, ADDI
 ADD x3, x2, x1
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Operation: ADD. Input operands: x1, x2. Output
Operand: x3.
●
Both input operands are 32b signed integers (x1
and x2)
– vs. ADDU, ADDI
●
Both input operands come from the Register File
 ADD x3, x2, x1
●
Operation: ADD. Input operands: x1, x2. Output
Operand: x3.
●
Both input operands are 32b signed integers (x1
and x2)
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Both input operands come from the Register File
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Processor contains hardware to feed the ALU
from the RF
 ADD x3, x2, x1
●
Operation: ADD. Input operands: x1, x2. Output
Operand: x3.
●
Both input operands are 32b signed integers (x1
and x2)
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Both input operands come from the Register File
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Processor contains hardware to feed the ALU
from the RF
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ALU contains hardware to add two numbers
(Adder)
 ADD x3, x2, x1
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Operation: ADD. Input operands: x1, x2. Output
Operand: x3.
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Both input operands are 32b signed integers (x1
and x2)
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Both input operands come from the Register File
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Processor contains hardware to feed the ALU from
the RF
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ALU contains hardware to add two numbers (Adder)
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Processor contains hardware to connect the ALU to
update the RF with the result
 Organization
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Also called Microarchitecture
 Organization
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Also called Microarchitecture
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Several Adder circuits exist
– Each with different gate counts and costs
 Organization
●
Also called Microarchitecture
●
Several Adder circuits exist
– Each with different gate counts and costs
●
Choosing one adder that fits the space and cost
constraints is an organization challenge
 Organization
●
Also called Microarchitecture
●
Several Adder circuits exist
– Each with different gate counts and costs
●
Choosing one adder that fits the space and cost
constraints is an organization challenge
●
Informally, Organization is the way a given ISA is
implemented in hardware on a processor
 Organization
●
Also called Microarchitecture
●
Several Adder circuits exist
– Each with different gate counts and costs
●
Choosing one adder that fits the space and cost
constraints is an organization challenge
●
Informally, Organization is the way a given ISA is
implemented in hardware on a processor
●
Architecture describes what the computer does
and organization describes how it does it.
Same Architecture, Different Microarchitectures
●
AMD Athlon II X4 ●
Intel Atom
– –

David Wentzlaff, ELE 475 – Computer Architecture, Princeton University

Same Architecture, Different Microarchitectures
●
AMD Athlon II X4 ●
Intel Atom
– X86 Instruction Set, Quad – X86 Instruction Set, Single
Core, Out-of-order, 2.9GHz, Core, In-order, 1.6GHz, 2W
125W – Decode 2 Instructions/Cycle /
– Decode 3 Core
Instructions/Cycle/Core – 32KB L1 I Cache, 24KB L1 D
– 64KB L1 I Cache, 64KB L1 D Cache, 512KB L2 Cache
Cache, 512KB L2 Cache

David Wentzlaff, ELE 475 – Computer Architecture, Princeton University

The Compute Stack

Application

Physics
The Compute Stack

Application

Physics
The Compute Stack

Application

Algorithm

Physics
The Compute Stack

Application

Algorithm
Programming Language

Physics
The Compute Stack

Application

Algorithm
Programming Language
Operating System/Virtual Machines

Physics
The Compute Stack

Application

Algorithm
Programming Language
Operating System/Virtual Machines

Devices
Physics
The Compute Stack

Application

Algorithm
Programming Language
Operating System/Virtual Machines

Circuits
Devices
Physics
The Compute Stack

Application

Algorithm
Programming Language
Operating System/Virtual Machines

Gates
Circuits
Devices
Physics
The Compute Stack

Application

Algorithm
Programming Language
Operating System/Virtual Machines
Instruction Set Architecture
Organization/Microarchitecture
Register-Transfer Level
Gates
Circuits
Devices
Physics
Memory Detour