2/5/2025

AV-314
Embedded Systems Design

Lecture No 21-23

“PIC-EUSART Modules”
References
• Lecture Notes
• Milan Verle Chapter-6

Instructor : Gp Capt Dr Mujahid Mohsin

Slides : 56

Learning Objectives

To understand the capabilities and operations

of EUSART modules in PIC 16F8xx
Micorcontroller

To learn transmission, reception and baud

rate control through configurations of
EUSART modules

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PIC 16F8xx : EUSART

EUSART - Enhanced Universal Sync Async Rxr

Txr

Supports both Sync. and Async. communication

Contains all clock generators, shift registers and

data buffers for serial I/O data transfer

PIC EUSART Features

Full-duplex async. Communication

Half-duplex sync. communication
Both Master or Slave
Programmable 8 or 9 bit character length
Address detection in 9-bit mode
Input buffer overrun error detection
Received character framing error detection
Two character input buffer and 01 character
output buffer

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PIC16F887 Pinouts: EUSART

EUSART Asynchronous Mode

In Idle state data line has high voltage level

(Logic 1)
Start bit initiates data transmission
Always a 0 (Logic Low)
Each data is 8 or 9 bit wide
LSB is transmitted first
Stop Bit is Logic High (1)

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EUSART SFRs

EUSART
Transmission

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EUSART Asynchronous
Transmitter

TXREG Register

EUSART Transmit Data Register

Data to be sent is written into TXREG
Byte will immediately be transferred to the TSR
register
After TXREG is empty TXIF Flag is automatically set
Cannot be cleared by software but automatically by
writing new data (read-only bit)
Can generate an interrupt if
GIE is enabled
PEIE is enabled
TXIE is enabled
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TSR Register

Transmit Shift Register

Not directly accessible by software
Obtains its data from transmit buffer (TXREG)
Transmit bit by bit serial data through output
port, LSB first
As soon as TSR becomes empty the TRMT bit
of TXSTA register is automatically set

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TXREG and TSR Registers

If TSR is completely flushed only then TXREG

will write the next character to it
If TSR is not empty and TXREG receives new
character, it will wait until the stop bit is
transmitted
Data transmission (Start, Data & Stop bits) will
immediately commence as soon as the new
data is loaded in TSR

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EUSART Asynchronous
Transmitter

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TXSTA Register

CSRC: Clock Source Select Bit

Only for Sync mode

TX9: 9-Bit Transmit Enable Bit

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TXSTA Register

TXEN: Transmission Enabled Bit

SYNC: EUSART Mode Select Bit

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EUSART Asynchronous
Transmitter

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TXSTA Register

TRMT: Transmit Shift Register Status Bit

1: TSR register is empty
0: TSR register is not empty

TX9D: Ninth Bit of Transmit Data

Can be used as address or parity bit

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EUSART Transmitter Gate Level

Overview

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EUSART Asynchronous
Transmitter
For Async Transmission mode
TXEN=1 for enabling transmission
Sync=0 for enabling asynchronous transmission
SPEN=1 for automatically configuring TX/RC6 pin
as output and enabling EUSART
All other EUSART control bits are assumed to be at
default stage

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EUSART 9-Bit Transmission

9th bit can be parity bit

Must be written at TX9D

before writing to TXREG

All 9-bits will be transferred

to TSR register

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Async Transmission

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Async Transmission
Back to Back

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EUSART Async
receiver

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EUSART Asynchronous
Receiver

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EUSART Asynchronous
Receiver
RSR register serially (bit-by-bit) receives each
character
Shifts it to 02-character FIFO memory
FIFO and RSR not directly accessible
Data can only be accessed through RCREG
register
Enabled by:
CREN=1
SYNC=0
SPEN=1

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EUSART Receive Interrupt

Immediately after the stop bit is received by

RSR register
All data bits are transferred to RCREG register
9th bit, if enabled, moves to RX9D bit of RCSTA
register
RCIF flag is set
Interrupt is generated if INTCON, PEIE and RCIE
bits are set.
RCIF interrupt is read only (cannot be cleared in
software)

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EUSART Asynchronous
Receiver

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Receive Framing Error

FERR Framing error bit in RCSTA register

Indicates that a stop bit was not seen at the
expected time.
Applies to the top unread character in the
FIFO
Read-only bit
Does not hinder reception of additional
characters
Does not generate any interrupt

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Receive Overrun Error

Receiver FIFO can hold two characters
Overrun Error will occur if
3rd character (including Stop bit) is received in RSR and
FIFO is full
Sets the OERR bit of RCSTA register
Two FIFO characters can be read
No additional characters can be read until the error is
cleared
Can only be cleared by:
Clearing the CREN bit or
Resetting EUSART by SPEN bit

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RCSTA Register

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RCSTA Register

In Synchronous mode

Enables Rxr in Asynchronous mode

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Address Mode

9 bits will be taken as address

Slave devices will identify and attempt to match the
address

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Address Mode

Data communication will start from the matched

receiver

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EUSART baud rate

generator

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Baud Rate Generator

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EUSART Baud Rate Generator

8-bit or 16-bit timer

Default is 8-bit mode
Supports both Async and Sync EUSART operations

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Baud Rate Selection

BRGH: High Baud Rate Select Bit

1: EUSART operates at high speed
0: EUSART operates at low speed

• BRG16: 16 bit Baud Rate Generator

– 1: 16 bit timer is enabled
– 0: 8-bit timer is enabled
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Baud Rate Selection Formulae

Warning: There are errors in the table given in Milan Verle’s book
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Baud Rate Generator

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Setting the Registers for the

Desired Baud Rate
For a device with FOSC of 16 MHz in
Asynchronous mode and 8-bit BRG, calculate
the value of SPBRG register if the desired
baud rate is 9600 bps

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Setting the Registers for the

Desired Baud Rate
For the baud rate calculated before find out the
error percentage

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BAUD Control Register :

BAUDCTL

ABDOVF: Auto Baud Detect Overflow Bit

Used in Async. mode only during auto baud rate
detection

ABDEN: Auto Baud Detect Enable Bit

Used in Async mode only

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BAUD Control Register :

BAUDCTL

RCIDL: Receive Idle Flag Bit

Used in Async. mode only

Automatically set if RSR is empty (after stop bit, if

there is no start bit)

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BAUD Control Register :

BAUDCTL

SCKP: Synchronous Clock Polarity Select Bit

Acts differently depending on the EUSART mode.
Asynchronous Mode

Synchronous Mode

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BAUD Control Register :

BAUDCTL

WUE: Wake-Up Enable Bit

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Electrical Characteristics
USART Vs RS-232
USART:
USART uses TTL i.e. 0V (bit 0) and +5V (bit 1)
RS-232:
Logic 1 is represented by a negative voltage
between -3V and -25V (typically -15V)
Logic 0 is represented by a positive volts between
3V and 25V (typically +15V)
Communication requires external up/down
convertors
MAX232 is the most commonly deployed IC

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MAX232 IC

Establish serial communication between a

microcontroller and a computer

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MAX232: USART to PC (RS232)

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MAX232: PC to USART

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Interface Diagram

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PIC EUSART : Relevant Registers

Summary

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Hardware Vs Software UART

Hardware UART Library

Initializes hardware UART module with the desired

baud rate.
Refer to the device data sheet for baud rates allowed
for specific Fosc.
If you specify the unsupported baud rate, compiler
will report an error.
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Hardware Vs Software UART

Software UART library: enables use of any

digital port for serial communication.
char Soft_UART_Init(char *port, char rx_pin,
char tx_pin, unsigned long baud_rate, char
inverted);
Returns:

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EUSART Lecture Summary

Studied the basic of Serial communication

Sync Vs Async
Duplex Vs Simplex
PIC EUSART basic functionality
Transmission and Reception Configurations
9-bit mode
Error detection
Address mode
Baud rate generation
RS-232 to/from EUSART conversion

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End of Lecture

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